Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	606946	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

365611

1

T3

140

T4

1081

T6

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	518925	1			T3	186		T4	1500		T5	1
values[0x0]	226497	1			T3	90		T4	850		T6	8
values[0x1]	227135	1			T3	103		T4	850		T6	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	509616	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

462941

1

T3

177

T4

1409

T6

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2589	1			T3	1		T4	27		T7	12
valid_sources[0x01]	3356	1			T4	1		T7	12		T11	1
valid_sources[0x02]	3138	1			T3	3		T4	15		T7	9
valid_sources[0x03]	3618	1			T3	2		T4	7		T7	9
valid_sources[0x04]	3377	1			T4	25		T7	12		T8	4
valid_sources[0x05]	3322	1			T3	1		T4	5		T7	9
valid_sources[0x06]	3570	1			T3	4		T4	17		T7	20
valid_sources[0x07]	2730	1			T3	2		T4	17		T7	6
valid_sources[0x08]	4046	1			T4	4		T6	1		T7	8
valid_sources[0x09]	2973	1			T4	2		T7	3		T8	4
valid_sources[0x0a]	3544	1			T3	3		T4	6		T7	19
valid_sources[0x0b]	3554	1			T4	14		T7	9		T8	4
valid_sources[0x0c]	3422	1			T3	1		T4	18		T7	17
valid_sources[0x0d]	3672	1			T4	8		T7	9		T8	1
valid_sources[0x0e]	4325	1			T3	2		T4	33		T7	16
valid_sources[0x0f]	4387	1			T3	2		T7	12		T10	18
valid_sources[0x10]	2764	1			T3	1		T4	11		T7	6
valid_sources[0x11]	3368	1			T4	3		T7	11		T8	1
valid_sources[0x12]	3570	1			T3	3		T4	12		T7	15
valid_sources[0x13]	4018	1			T3	1		T4	19		T7	13
valid_sources[0x14]	3512	1			T3	2		T4	16		T7	16
valid_sources[0x15]	3845	1			T3	1		T4	11		T7	13
valid_sources[0x16]	3716	1			T3	2		T4	10		T7	8
valid_sources[0x17]	6263	1			T3	2		T4	7		T7	4
valid_sources[0x18]	3886	1			T3	1		T4	10		T7	16
valid_sources[0x19]	3650	1			T3	1		T4	5		T7	11
valid_sources[0x1a]	3046	1			T3	4		T4	5		T7	11
valid_sources[0x1b]	2910	1			T3	1		T4	12		T7	11
valid_sources[0x1c]	6334	1			T4	16		T7	7		T8	1
valid_sources[0x1d]	2894	1			T3	2		T4	19		T7	10
valid_sources[0x1e]	3597	1			T3	1		T4	10		T7	14
valid_sources[0x1f]	4106	1			T3	2		T4	28		T7	12
valid_sources[0x20]	4293	1			T3	2		T4	15		T7	16
valid_sources[0x21]	3541	1			T3	1		T4	35		T7	15
valid_sources[0x22]	3959	1			T3	3		T4	7		T7	11
valid_sources[0x23]	7017	1			T3	1		T4	4		T7	10
valid_sources[0x24]	4278	1			T3	4		T4	14		T7	18
valid_sources[0x25]	3064	1			T3	1		T4	14		T7	12
valid_sources[0x26]	3304	1			T3	2		T4	22		T7	16
valid_sources[0x27]	4279	1			T3	1		T4	9		T7	13
valid_sources[0x28]	4330	1			T3	1		T4	6		T7	5
valid_sources[0x29]	3649	1			T3	2		T4	13		T7	4
valid_sources[0x2a]	3357	1			T3	1		T4	20		T7	15
valid_sources[0x2b]	3082	1			T3	1		T4	1		T7	5
valid_sources[0x2c]	4807	1			T3	1		T4	13		T7	14
valid_sources[0x2d]	3967	1			T3	1		T4	4		T7	18
valid_sources[0x2e]	6051	1			T4	11		T7	16		T8	2
valid_sources[0x2f]	3789	1			T4	16		T7	11		T8	3
valid_sources[0x30]	3462	1			T3	2		T4	4		T7	15
valid_sources[0x31]	4152	1			T3	2		T4	4		T7	10
valid_sources[0x32]	4258	1			T3	1		T4	4		T7	8
valid_sources[0x33]	3982	1			T3	1		T4	9		T7	8
valid_sources[0x34]	3483	1			T4	9		T7	7		T8	1
valid_sources[0x35]	4343	1			T3	1		T4	15		T7	9
valid_sources[0x36]	3204	1			T4	13		T7	9		T10	15
valid_sources[0x37]	3499	1			T3	1		T4	9		T7	11
valid_sources[0x38]	3573	1			T3	3		T4	8		T7	9
valid_sources[0x39]	3851	1			T3	4		T4	19		T7	12
valid_sources[0x3a]	2950	1			T3	1		T4	20		T7	9
valid_sources[0x3b]	3841	1			T3	1		T4	15		T7	6
valid_sources[0x3c]	3148	1			T3	3		T4	6		T7	7
valid_sources[0x3d]	3558	1			T4	8		T7	8		T12	1
valid_sources[0x3e]	3538	1			T4	25		T7	14		T10	11
valid_sources[0x3f]	3902	1			T4	20		T7	11		T10	32
valid_sources[0x40]	6226	1			T3	4		T4	10		T7	12
valid_sources[0x41]	3899	1			T3	2		T4	10		T7	13
valid_sources[0x42]	3035	1			T4	10		T7	14		T12	2
valid_sources[0x43]	3596	1			T3	2		T4	4		T7	12
valid_sources[0x44]	3633	1			T3	1		T4	6		T7	13
valid_sources[0x45]	5188	1			T4	17		T7	11		T12	2
valid_sources[0x46]	6693	1			T3	1		T4	21		T7	13
valid_sources[0x47]	3502	1			T3	1		T4	8		T7	9
valid_sources[0x48]	3294	1			T3	2		T4	5		T7	11
valid_sources[0x49]	3427	1			T3	2		T4	15		T7	11
valid_sources[0x4a]	3443	1			T3	2		T4	21		T7	6
valid_sources[0x4b]	3425	1			T4	8		T7	16		T8	2
valid_sources[0x4c]	3321	1			T3	2		T4	19		T7	14
valid_sources[0x4d]	3001	1			T4	12		T7	10		T8	2
valid_sources[0x4e]	3923	1			T3	2		T4	14		T7	10
valid_sources[0x4f]	3445	1			T3	2		T4	21		T7	11
valid_sources[0x50]	2964	1			T3	3		T4	8		T7	14
valid_sources[0x51]	4357	1			T3	2		T4	18		T7	6
valid_sources[0x52]	5315	1			T3	1		T4	30		T7	9
valid_sources[0x53]	3307	1			T3	3		T4	6		T7	12
valid_sources[0x54]	3178	1			T3	2		T4	2		T7	3
valid_sources[0x55]	3065	1			T4	10		T7	13		T8	1
valid_sources[0x56]	3520	1			T4	26		T7	9		T10	15
valid_sources[0x57]	3303	1			T3	4		T4	17		T7	7
valid_sources[0x58]	3754	1			T4	16		T7	14		T8	1
valid_sources[0x59]	3100	1			T3	1		T4	15		T7	14
valid_sources[0x5a]	3650	1			T3	1		T4	12		T7	9
valid_sources[0x5b]	3158	1			T3	2		T4	8		T7	13
valid_sources[0x5c]	4081	1			T3	1		T4	19		T7	8
valid_sources[0x5d]	3955	1			T3	2		T4	14		T7	5
valid_sources[0x5e]	3545	1			T3	1		T4	11		T7	19
valid_sources[0x5f]	3288	1			T3	3		T4	11		T7	9
valid_sources[0x60]	3121	1			T3	2		T4	16		T7	11
valid_sources[0x61]	4277	1			T3	2		T4	8		T7	8
valid_sources[0x62]	4803	1			T4	10		T7	11		T12	2
valid_sources[0x63]	4525	1			T3	1		T4	9		T7	9
valid_sources[0x64]	4804	1			T3	2		T4	18		T7	12
valid_sources[0x65]	3515	1			T3	1		T4	5		T7	5
valid_sources[0x66]	3570	1			T3	1		T4	23		T7	12
valid_sources[0x67]	3690	1			T3	3		T4	9		T7	8
valid_sources[0x68]	4028	1			T3	6		T4	12		T7	11
valid_sources[0x69]	3731	1			T4	8		T7	10		T8	2
valid_sources[0x6a]	4676	1			T3	4		T4	10		T7	12
valid_sources[0x6b]	3642	1			T3	2		T4	6		T7	12
valid_sources[0x6c]	4318	1			T3	3		T4	23		T7	14
valid_sources[0x6d]	3604	1			T3	1		T4	5		T7	12
valid_sources[0x6e]	2960	1			T4	14		T6	1		T7	7
valid_sources[0x6f]	3225	1			T4	18		T7	15		T10	15
valid_sources[0x70]	4124	1			T3	1		T4	9		T7	14
valid_sources[0x71]	3040	1			T3	1		T4	6		T7	14
valid_sources[0x72]	3341	1			T3	2		T4	26		T7	4
valid_sources[0x73]	4239	1			T3	1		T4	21		T7	14
valid_sources[0x74]	3137	1			T4	10		T7	13		T12	3
valid_sources[0x75]	3234	1			T3	2		T4	13		T7	5
valid_sources[0x76]	3293	1			T3	1		T4	6		T7	5
valid_sources[0x77]	3475	1			T3	3		T4	24		T7	9
valid_sources[0x78]	5472	1			T3	2		T4	7		T7	18
valid_sources[0x79]	4398	1			T3	2		T4	15		T7	11
valid_sources[0x7a]	3958	1			T3	1		T4	17		T7	12
valid_sources[0x7b]	3312	1			T3	1		T4	20		T7	12
valid_sources[0x7c]	3502	1			T4	7		T7	10		T8	2
valid_sources[0x7d]	5515	1			T4	16		T7	12		T10	2
valid_sources[0x7e]	3292	1			T4	19		T7	14		T8	2
valid_sources[0x7f]	3394	1			T4	3		T7	9		T10	1
valid_sources[0x80]	3681	1			T3	1		T4	13		T7	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

243671

1

T3

93

T4

679

T7

736

values[0x0]

all_enables

biggest_size

78909

1

T3

29

T4

270

T6

1

values[0x1]

all_enables

biggest_size

43031

1

T3

18

T4

132

T7

103