Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_mubi4_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_ctrl_scanmode_sync 100.00 100.00 100.00
tb.dut.u_daon_por.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_daon_por_io.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_daon_por_io_div2.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_daon_por_io_div4.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_daon_por_usb.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_daon_lc.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_lc.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_daon_lc_shadowed.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_lc_shadowed.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_daon_lc_aon.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_daon_lc_io.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_lc_io.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div2.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div2.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div4.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div4.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_daon_lc_usb.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_lc_usb.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_sys.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_daon_sys_io_div4.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_spi_device.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_spi_host0.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_spi_host1.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_usb.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_usb_aon.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_i2c0.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_i2c1.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_i2c2.u_scanmode_sync 100.00 100.00 100.00
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync 100.00 100.00 100.00
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_ctrl_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_daon_por.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_daon_por_io.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_io


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_daon_por_io_div2.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_io_div2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_daon_por_io_div4.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_daon_por_usb.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_daon_lc.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_lc.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_daon_lc_shadowed.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_lc_shadowed.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_daon_lc_aon.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_io


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_io


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io_div2.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_io_div2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io_div2.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_io_div2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io_div4.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_daon_lc_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io_div4.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_d0_lc_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_daon_lc_io_div4_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_d0_lc_io_div4_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_daon_lc_usb.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_lc_usb.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_sys.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_sys


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_daon_sys_io_div4.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_sys_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_spi_device.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_spi_device


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_spi_host0.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_spi_host0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_spi_host1.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_spi_host1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_usb.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_usb_aon.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_d0_usb_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_i2c0.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_i2c0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_i2c1.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_i2c1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_i2c2.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_i2c2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00

Line Coverage for Module : prim_mubi4_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Module : prim_mubi4_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 16665 16665 0 0
OutputsKnown_A 357419398 196181576 0 0
gen_no_flops.OutputDelay_A 357419398 196181576 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 16665 16665 0 0
T1 33 33 0 0
T2 33 33 0 0
T3 33 33 0 0
T4 33 33 0 0
T5 33 33 0 0
T6 33 33 0 0
T7 33 33 0 0
T8 33 33 0 0
T9 33 33 0 0
T10 33 33 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 357419398 196181576 0 0
T1 174981 17843 0 0
T2 182313 18074 0 0
T3 85609 52947 0 0
T4 870333 286835 0 0
T5 137964 25516 0 0
T6 42461 23317 0 0
T7 545441 270680 0 0
T8 147972 120674 0 0
T9 94141 27763 0 0
T10 293041 273226 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 357419398 196181576 0 0
T1 174981 17843 0 0
T2 182313 18074 0 0
T3 85609 52947 0 0
T4 870333 286835 0 0
T5 137964 25516 0 0
T6 42461 23317 0 0
T7 545441 270680 0 0
T8 147972 120674 0 0
T9 94141 27763 0 0
T10 293041 273226 0 0

Line Coverage for Instance : tb.dut.u_ctrl_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_ctrl_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 12220198 7007048 0 0
gen_no_flops.OutputDelay_A 12220198 7007048 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12220198 7007048 0 0
T1 5829 691 0 0
T2 5865 698 0 0
T3 2825 1843 0 0
T4 29565 12211 0 0
T5 4268 1004 0 0
T6 1373 725 0 0
T7 21505 12344 0 0
T8 5316 4674 0 0
T9 2941 947 0 0
T10 8945 8298 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12220198 7007048 0 0
T1 5829 691 0 0
T2 5865 698 0 0
T3 2825 1843 0 0
T4 29565 12211 0 0
T5 4268 1004 0 0
T6 1373 725 0 0
T7 21505 12344 0 0
T8 5316 4674 0 0
T9 2941 947 0 0
T10 8945 8298 0 0

Line Coverage for Instance : tb.dut.u_daon_por.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_daon_por.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_daon_por_io.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io_div2.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io_div4.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.u_daon_por_usb.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_daon_por_usb.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.u_daon_lc.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.u_d0_lc.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_aon.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_aon.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_io.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_io.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_usb.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_usb.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_usb.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_usb.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.u_d0_sys.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_sys.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_device.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_spi_device.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_host0.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_spi_host0.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_host1.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_spi_host1.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.u_d0_usb.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_usb.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.u_d0_usb_aon.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_usb_aon.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c0.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_i2c0.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c1.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_i2c1.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c2.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_i2c2.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 505 505 0 0
OutputsKnown_A 10787475 5911704 0 0
gen_no_flops.OutputDelay_A 10787475 5911704 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505 505 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10787475 5911704 0 0
T1 5286 536 0 0
T2 5514 543 0 0
T3 2587 1597 0 0
T4 26274 8582 0 0
T5 4178 766 0 0
T6 1284 706 0 0
T7 16373 8073 0 0
T8 4458 3625 0 0
T9 2850 838 0 0
T10 8878 8279 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%