SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_aon |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_daon_lc_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_d0_lc_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_daon_lc_io_div4_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_d0_lc_io_div4_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_sys |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_sys_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_device |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_host0 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_host1 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | u_d0_usb_aon |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c0 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c1 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 16665 | 16665 | 0 | 0 |
OutputsKnown_A | 357419398 | 196181576 | 0 | 0 |
gen_no_flops.OutputDelay_A | 357419398 | 196181576 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 16665 | 16665 | 0 | 0 |
T1 | 33 | 33 | 0 | 0 |
T2 | 33 | 33 | 0 | 0 |
T3 | 33 | 33 | 0 | 0 |
T4 | 33 | 33 | 0 | 0 |
T5 | 33 | 33 | 0 | 0 |
T6 | 33 | 33 | 0 | 0 |
T7 | 33 | 33 | 0 | 0 |
T8 | 33 | 33 | 0 | 0 |
T9 | 33 | 33 | 0 | 0 |
T10 | 33 | 33 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 357419398 | 196181576 | 0 | 0 |
T1 | 174981 | 17843 | 0 | 0 |
T2 | 182313 | 18074 | 0 | 0 |
T3 | 85609 | 52947 | 0 | 0 |
T4 | 870333 | 286835 | 0 | 0 |
T5 | 137964 | 25516 | 0 | 0 |
T6 | 42461 | 23317 | 0 | 0 |
T7 | 545441 | 270680 | 0 | 0 |
T8 | 147972 | 120674 | 0 | 0 |
T9 | 94141 | 27763 | 0 | 0 |
T10 | 293041 | 273226 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 357419398 | 196181576 | 0 | 0 |
T1 | 174981 | 17843 | 0 | 0 |
T2 | 182313 | 18074 | 0 | 0 |
T3 | 85609 | 52947 | 0 | 0 |
T4 | 870333 | 286835 | 0 | 0 |
T5 | 137964 | 25516 | 0 | 0 |
T6 | 42461 | 23317 | 0 | 0 |
T7 | 545441 | 270680 | 0 | 0 |
T8 | 147972 | 120674 | 0 | 0 |
T9 | 94141 | 27763 | 0 | 0 |
T10 | 293041 | 273226 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12220198 | 7007048 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12220198 | 7007048 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12220198 | 7007048 | 0 | 0 |
T1 | 5829 | 691 | 0 | 0 |
T2 | 5865 | 698 | 0 | 0 |
T3 | 2825 | 1843 | 0 | 0 |
T4 | 29565 | 12211 | 0 | 0 |
T5 | 4268 | 1004 | 0 | 0 |
T6 | 1373 | 725 | 0 | 0 |
T7 | 21505 | 12344 | 0 | 0 |
T8 | 5316 | 4674 | 0 | 0 |
T9 | 2941 | 947 | 0 | 0 |
T10 | 8945 | 8298 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12220198 | 7007048 | 0 | 0 |
T1 | 5829 | 691 | 0 | 0 |
T2 | 5865 | 698 | 0 | 0 |
T3 | 2825 | 1843 | 0 | 0 |
T4 | 29565 | 12211 | 0 | 0 |
T5 | 4268 | 1004 | 0 | 0 |
T6 | 1373 | 725 | 0 | 0 |
T7 | 21505 | 12344 | 0 | 0 |
T8 | 5316 | 4674 | 0 | 0 |
T9 | 2941 | 947 | 0 | 0 |
T10 | 8945 | 8298 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10787475 | 5911704 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10787475 | 5911704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10787475 | 5911704 | 0 | 0 |
T1 | 5286 | 536 | 0 | 0 |
T2 | 5514 | 543 | 0 | 0 |
T3 | 2587 | 1597 | 0 | 0 |
T4 | 26274 | 8582 | 0 | 0 |
T5 | 4178 | 766 | 0 | 0 |
T6 | 1284 | 706 | 0 | 0 |
T7 | 16373 | 8073 | 0 | 0 |
T8 | 4458 | 3625 | 0 | 0 |
T9 | 2850 | 838 | 0 | 0 |
T10 | 8878 | 8279 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |