Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T10,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T12,T61
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T12,T61
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T61,T65
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T61,T46
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T61,T22
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T10,T61
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T61,T65
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12220198	13695	0	0
gen_assertions[0].RstEnOn_A	12220198	1017	0	0
gen_assertions[0].RstNOff_A	12220198	13695	0	0
gen_assertions[0].RstNOn_A	12220198	1017	0	0
gen_assertions[1].RstEnOff_A	48880762	12441	0	0
gen_assertions[1].RstEnOn_A	48880762	970	0	0
gen_assertions[1].RstNOff_A	48880762	12441	0	0
gen_assertions[1].RstNOn_A	48880762	970	0	0
gen_assertions[2].RstEnOff_A	24441330	12475	0	0
gen_assertions[2].RstEnOn_A	24441330	970	0	0
gen_assertions[2].RstNOff_A	24441330	12475	0	0
gen_assertions[2].RstNOn_A	24441330	970	0	0
gen_assertions[3].RstEnOff_A	24441375	12551	0	0
gen_assertions[3].RstEnOn_A	24441375	1031	0	0
gen_assertions[3].RstNOff_A	24441375	12551	0	0
gen_assertions[3].RstNOn_A	24441375	1031	0	0
gen_assertions[4].RstEnOff_A	1543402	21448	0	0
gen_assertions[4].RstEnOn_A	1543402	1094	0	0
gen_assertions[4].RstNOff_A	1543402	21448	0	0
gen_assertions[4].RstNOn_A	1543402	1094	0	0
gen_assertions[5].RstEnOff_A	12220198	13929	0	0
gen_assertions[5].RstEnOn_A	12220198	1131	0	0
gen_assertions[5].RstNOff_A	12220198	13929	0	0
gen_assertions[5].RstNOn_A	12220198	1131	0	0
gen_assertions[6].RstEnOff_A	12220198	14001	0	0
gen_assertions[6].RstEnOn_A	12220198	1197	0	0
gen_assertions[6].RstNOff_A	12220198	14001	0	0
gen_assertions[6].RstNOn_A	12220198	1197	0	0
gen_assertions[7].RstEnOff_A	12220198	14056	0	0
gen_assertions[7].RstEnOn_A	12220198	1248	0	0
gen_assertions[7].RstNOff_A	12220198	14056	0	0
gen_assertions[7].RstNOn_A	12220198	1248	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12220198	13695	0	0
T3	2825	4	0	0
T4	29565	75	0	0
T5	4268	0	0	0
T6	1373	0	0	0
T7	21505	38	0	0
T8	5316	14	0	0
T9	2941	0	0	0
T10	8945	4	0	0
T11	3640	4	0	0
T12	4455	20	0	0
T14	0	43	0	0
T22	0	4	0	0
T61	0	5	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12220198	1017	0	0
T8	5316	1	0	0
T9	2941	0	0	0
T10	8945	4	0	0
T11	3640	0	0	0
T12	4455	10	0	0
T13	2378	0	0	0
T14	48705	0	0	0
T22	2677	0	0	0
T45	1891	0	0	0
T47	0	10	0	0
T61	11589	5	0	0
T65	0	9	0	0
T89	0	7	0	0
T90	0	5	0	0
T91	0	1	0	0
T92	0	4	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12220198	13695	0	0
T3	2825	4	0	0
T4	29565	75	0	0
T5	4268	0	0	0
T6	1373	0	0	0
T7	21505	38	0	0
T8	5316	14	0	0
T9	2941	0	0	0
T10	8945	4	0	0
T11	3640	4	0	0
T12	4455	20	0	0
T14	0	43	0	0
T22	0	4	0	0
T61	0	5	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12220198	1017	0	0
T8	5316	1	0	0
T9	2941	0	0	0
T10	8945	4	0	0
T11	3640	0	0	0
T12	4455	10	0	0
T13	2378	0	0	0
T14	48705	0	0	0
T22	2677	0	0	0
T45	1891	0	0	0
T47	0	10	0	0
T61	11589	5	0	0
T65	0	9	0	0
T89	0	7	0	0
T90	0	5	0	0
T91	0	1	0	0
T92	0	4	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48880762	12441	0	0
T3	11293	4	0	0
T4	118204	64	0	0
T5	17077	0	0	0
T6	5500	0	0	0
T7	86001	34	0	0
T8	21268	12	0	0
T9	11765	0	0	0
T10	35781	8	0	0
T11	14565	4	0	0
T12	17826	17	0	0
T14	0	38	0	0
T22	0	4	0	0
T61	0	6	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48880762	970	0	0
T10	35781	8	0	0
T11	14565	0	0	0
T12	17826	5	0	0
T13	9513	0	0	0
T14	194824	0	0	0
T22	10717	0	0	0
T23	16879	0	0	0
T24	10096	0	0	0
T45	7567	0	0	0
T47	0	8	0	0
T48	0	5	0	0
T61	46360	6	0	0
T65	0	7	0	0
T89	0	2	0	0
T90	0	5	0	0
T92	0	5	0	0
T93	0	1	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48880762	12441	0	0
T3	11293	4	0	0
T4	118204	64	0	0
T5	17077	0	0	0
T6	5500	0	0	0
T7	86001	34	0	0
T8	21268	12	0	0
T9	11765	0	0	0
T10	35781	8	0	0
T11	14565	4	0	0
T12	17826	17	0	0
T14	0	38	0	0
T22	0	4	0	0
T61	0	6	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48880762	970	0	0
T10	35781	8	0	0
T11	14565	0	0	0
T12	17826	5	0	0
T13	9513	0	0	0
T14	194824	0	0	0
T22	10717	0	0	0
T23	16879	0	0	0
T24	10096	0	0	0
T45	7567	0	0	0
T47	0	8	0	0
T48	0	5	0	0
T61	46360	6	0	0
T65	0	7	0	0
T89	0	2	0	0
T90	0	5	0	0
T92	0	5	0	0
T93	0	1	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24441330	12475	0	0
T3	5650	4	0	0
T4	59098	64	0	0
T5	8538	0	0	0
T6	2750	0	0	0
T7	43004	34	0	0
T8	10633	12	0	0
T9	5882	0	0	0
T10	17891	9	0	0
T11	7283	4	0	0
T12	8913	17	0	0
T14	0	38	0	0
T22	0	5	0	0
T61	0	9	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24441330	970	0	0
T10	17891	9	0	0
T11	7283	0	0	0
T12	8913	1	0	0
T13	4756	0	0	0
T14	97419	0	0	0
T22	5354	1	0	0
T23	8440	0	0	0
T24	5049	0	0	0
T45	3782	0	0	0
T47	0	10	0	0
T48	0	5	0	0
T61	23181	9	0	0
T65	0	10	0	0
T90	0	6	0	0
T92	0	5	0	0
T93	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24441330	12475	0	0
T3	5650	4	0	0
T4	59098	64	0	0
T5	8538	0	0	0
T6	2750	0	0	0
T7	43004	34	0	0
T8	10633	12	0	0
T9	5882	0	0	0
T10	17891	9	0	0
T11	7283	4	0	0
T12	8913	17	0	0
T14	0	38	0	0
T22	0	5	0	0
T61	0	9	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24441330	970	0	0
T10	17891	9	0	0
T11	7283	0	0	0
T12	8913	1	0	0
T13	4756	0	0	0
T14	97419	0	0	0
T22	5354	1	0	0
T23	8440	0	0	0
T24	5049	0	0	0
T45	3782	0	0	0
T47	0	10	0	0
T48	0	5	0	0
T61	23181	9	0	0
T65	0	10	0	0
T90	0	6	0	0
T92	0	5	0	0
T93	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24441375	12551	0	0
T3	5647	4	0	0
T4	59113	64	0	0
T5	8538	0	0	0
T6	2749	0	0	0
T7	43006	34	0	0
T8	10633	12	0	0
T9	5882	0	0	0
T10	17890	11	0	0
T11	7281	4	0	0
T12	8913	17	0	0
T14	0	38	0	0
T22	0	4	0	0
T61	0	8	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24441375	1031	0	0
T10	17890	11	0	0
T11	7281	0	0	0
T12	8913	0	0	0
T13	4755	0	0	0
T14	97417	0	0	0
T22	5357	0	0	0
T23	8437	0	0	0
T24	5047	0	0	0
T45	3783	0	0	0
T47	0	11	0	0
T48	0	6	0	0
T61	23181	8	0	0
T65	0	10	0	0
T90	0	7	0	0
T92	0	5	0	0
T94	0	1	0	0
T95	0	11	0	0
T96	0	32	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24441375	12551	0	0
T3	5647	4	0	0
T4	59113	64	0	0
T5	8538	0	0	0
T6	2749	0	0	0
T7	43006	34	0	0
T8	10633	12	0	0
T9	5882	0	0	0
T10	17890	11	0	0
T11	7281	4	0	0
T12	8913	17	0	0
T14	0	38	0	0
T22	0	4	0	0
T61	0	8	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24441375	1031	0	0
T10	17890	11	0	0
T11	7281	0	0	0
T12	8913	0	0	0
T13	4755	0	0	0
T14	97417	0	0	0
T22	5357	0	0	0
T23	8437	0	0	0
T24	5047	0	0	0
T45	3783	0	0	0
T47	0	11	0	0
T48	0	6	0	0
T61	23181	8	0	0
T65	0	10	0	0
T90	0	7	0	0
T92	0	5	0	0
T94	0	1	0	0
T95	0	11	0	0
T96	0	32	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1543402	21448	0	0
T1	730	3	0	0
T2	735	3	0	0
T3	352	6	0	0
T4	3708	76	0	0
T5	532	2	0	0
T6	170	1	0	0
T7	2759	56	0	0
T8	664	15	0	0
T9	367	2	0	0
T10	1117	12	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1543402	1094	0	0
T10	1117	11	0	0
T11	454	0	0	0
T12	555	0	0	0
T13	297	0	0	0
T14	6151	0	0	0
T22	335	0	0	0
T23	526	0	0	0
T24	313	0	0	0
T45	236	0	0	0
T46	0	1	0	0
T47	0	10	0	0
T48	0	6	0	0
T61	1447	11	0	0
T65	0	14	0	0
T90	0	7	0	0
T92	0	7	0	0
T95	0	8	0	0
T96	0	30	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1543402	21448	0	0
T1	730	3	0	0
T2	735	3	0	0
T3	352	6	0	0
T4	3708	76	0	0
T5	532	2	0	0
T6	170	1	0	0
T7	2759	56	0	0
T8	664	15	0	0
T9	367	2	0	0
T10	1117	12	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1543402	1094	0	0
T10	1117	11	0	0
T11	454	0	0	0
T12	555	0	0	0
T13	297	0	0	0
T14	6151	0	0	0
T22	335	0	0	0
T23	526	0	0	0
T24	313	0	0	0
T45	236	0	0	0
T46	0	1	0	0
T47	0	10	0	0
T48	0	6	0	0
T61	1447	11	0	0
T65	0	14	0	0
T90	0	7	0	0
T92	0	7	0	0
T95	0	8	0	0
T96	0	30	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12220198	13929	0	0
T3	2825	4	0	0
T4	29565	75	0	0
T5	4268	0	0	0
T6	1373	0	0	0
T7	21505	38	0	0
T8	5316	14	0	0
T9	2941	0	0	0
T10	8945	10	0	0
T11	3640	4	0	0
T12	4455	20	0	0
T14	0	43	0	0
T22	0	5	0	0
T61	0	12	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12220198	1131	0	0
T10	8945	10	0	0
T11	3640	0	0	0
T12	4455	0	0	0
T13	2378	0	0	0
T14	48705	0	0	0
T22	2677	1	0	0
T23	4217	0	0	0
T24	2524	0	0	0
T45	1891	1	0	0
T47	0	12	0	0
T48	0	7	0	0
T61	11589	12	0	0
T65	0	13	0	0
T90	0	8	0	0
T92	0	8	0	0
T95	0	11	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12220198	13929	0	0
T3	2825	4	0	0
T4	29565	75	0	0
T5	4268	0	0	0
T6	1373	0	0	0
T7	21505	38	0	0
T8	5316	14	0	0
T9	2941	0	0	0
T10	8945	10	0	0
T11	3640	4	0	0
T12	4455	20	0	0
T14	0	43	0	0
T22	0	5	0	0
T61	0	12	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12220198	1131	0	0
T10	8945	10	0	0
T11	3640	0	0	0
T12	4455	0	0	0
T13	2378	0	0	0
T14	48705	0	0	0
T22	2677	1	0	0
T23	4217	0	0	0
T24	2524	0	0	0
T45	1891	1	0	0
T47	0	12	0	0
T48	0	7	0	0
T61	11589	12	0	0
T65	0	13	0	0
T90	0	8	0	0
T92	0	8	0	0
T95	0	11	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12220198	14001	0	0
T3	2825	5	0	0
T4	29565	75	0	0
T5	4268	0	0	0
T6	1373	0	0	0
T7	21505	38	0	0
T8	5316	14	0	0
T9	2941	0	0	0
T10	8945	11	0	0
T11	3640	4	0	0
T12	4455	20	0	0
T14	0	43	0	0
T22	0	5	0	0
T61	0	14	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12220198	1197	0	0
T3	2825	1	0	0
T4	29565	0	0	0
T5	4268	0	0	0
T6	1373	0	0	0
T7	21505	0	0	0
T8	5316	0	0	0
T9	2941	0	0	0
T10	8945	11	0	0
T11	3640	0	0	0
T12	4455	0	0	0
T22	0	1	0	0
T45	0	1	0	0
T47	0	9	0	0
T48	0	11	0	0
T61	0	14	0	0
T65	0	14	0	0
T90	0	11	0	0
T92	0	9	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12220198	14001	0	0
T3	2825	5	0	0
T4	29565	75	0	0
T5	4268	0	0	0
T6	1373	0	0	0
T7	21505	38	0	0
T8	5316	14	0	0
T9	2941	0	0	0
T10	8945	11	0	0
T11	3640	4	0	0
T12	4455	20	0	0
T14	0	43	0	0
T22	0	5	0	0
T61	0	14	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12220198	1197	0	0
T3	2825	1	0	0
T4	29565	0	0	0
T5	4268	0	0	0
T6	1373	0	0	0
T7	21505	0	0	0
T8	5316	0	0	0
T9	2941	0	0	0
T10	8945	11	0	0
T11	3640	0	0	0
T12	4455	0	0	0
T22	0	1	0	0
T45	0	1	0	0
T47	0	9	0	0
T48	0	11	0	0
T61	0	14	0	0
T65	0	14	0	0
T90	0	11	0	0
T92	0	9	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12220198	14056	0	0
T3	2825	4	0	0
T4	29565	75	0	0
T5	4268	0	0	0
T6	1373	0	0	0
T7	21505	38	0	0
T8	5316	14	0	0
T9	2941	0	0	0
T10	8945	13	0	0
T11	3640	4	0	0
T12	4455	20	0	0
T14	0	43	0	0
T22	0	4	0	0
T61	0	12	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12220198	1248	0	0
T10	8945	13	0	0
T11	3640	0	0	0
T12	4455	0	0	0
T13	2378	0	0	0
T14	48705	0	0	0
T22	2677	0	0	0
T23	4217	0	0	0
T24	2524	0	0	0
T38	0	7	0	0
T45	1891	0	0	0
T47	0	9	0	0
T48	0	10	0	0
T61	11589	12	0	0
T65	0	16	0	0
T90	0	10	0	0
T92	0	10	0	0
T95	0	11	0	0
T96	0	33	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12220198	14056	0	0
T3	2825	4	0	0
T4	29565	75	0	0
T5	4268	0	0	0
T6	1373	0	0	0
T7	21505	38	0	0
T8	5316	14	0	0
T9	2941	0	0	0
T10	8945	13	0	0
T11	3640	4	0	0
T12	4455	20	0	0
T14	0	43	0	0
T22	0	4	0	0
T61	0	12	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12220198	1248	0	0
T10	8945	13	0	0
T11	3640	0	0	0
T12	4455	0	0	0
T13	2378	0	0	0
T14	48705	0	0	0
T22	2677	0	0	0
T23	4217	0	0	0
T24	2524	0	0	0
T38	0	7	0	0
T45	1891	0	0	0
T47	0	9	0	0
T48	0	10	0	0
T61	11589	12	0	0
T65	0	16	0	0
T90	0	10	0	0
T92	0	10	0	0
T95	0	11	0	0
T96	0	33	0	0