Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_mubi4_sender
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_daon_por.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_por_io.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_por_usb.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_aon.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_io.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc_io.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_usb.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc_usb.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_sys.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_spi_device.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_spi_host0.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_spi_host1.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_usb.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_usb_aon.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_i2c0.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_i2c1.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_i2c2.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por_io.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_io


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_io_div2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por_usb.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_aon.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_io


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_io


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_io_div2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_io_div2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_daon_lc_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_d0_lc_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_daon_lc_io_div4_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_d0_lc_io_div4_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_sys


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_sys_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_spi_device


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_spi_host0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_spi_host1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_d0_usb_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_i2c0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_i2c1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_i2c2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00

Line Coverage for Module : prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Module : prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 824943486 418414289 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 824943486 418414289 0 0
T1 393640 41709 0 0
T2 396086 42201 0 0
T3 190650 112529 0 0
T4 1995120 653837 0 0
T5 288154 59604 0 0
T6 92780 48359 0 0
T7 1451682 617650 0 0
T8 358870 262285 0 0
T9 198530 60214 0 0
T10 603798 546473 0 0

Line Coverage for Instance : tb.dut.u_daon_por.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_por.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 50919005 29217454 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 50919005 29217454 0 0
T1 24301 2898 0 0
T2 24454 2947 0 0
T3 11772 7684 0 0
T4 123163 51024 0 0
T5 17789 4192 0 0
T6 5729 3026 0 0
T7 89592 51462 0 0
T8 22153 19477 0 0
T9 12256 3953 0 0
T10 37272 34578 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_por_io.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 48880762 28047616 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 48880762 28047616 0 0
T1 23329 2781 0 0
T2 23475 2827 0 0
T3 11293 7369 0 0
T4 118204 48988 0 0
T5 17077 4024 0 0
T6 5500 2905 0 0
T7 86001 49393 0 0
T8 21268 18697 0 0
T9 11765 3793 0 0
T10 35781 33195 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 24441330 14020177 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24441330 14020177 0 0
T1 11662 1383 0 0
T2 11735 1413 0 0
T3 5650 3687 0 0
T4 59098 24480 0 0
T5 8538 2011 0 0
T6 2750 1452 0 0
T7 43004 24691 0 0
T8 10633 9349 0 0
T9 5882 1896 0 0
T10 17891 16597 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 12220198 7007048 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12220198 7007048 0 0
T1 5829 691 0 0
T2 5865 698 0 0
T3 2825 1843 0 0
T4 29565 12211 0 0
T5 4268 1004 0 0
T6 1373 725 0 0
T7 21505 12344 0 0
T8 5316 4674 0 0
T9 2941 947 0 0
T10 8945 8298 0 0

Line Coverage for Instance : tb.dut.u_daon_por_usb.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_por_usb.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 24441375 14019996 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24441375 14019996 0 0
T1 11665 1383 0 0
T2 11733 1413 0 0
T3 5647 3685 0 0
T4 59113 24491 0 0
T5 8538 2011 0 0
T6 2749 1452 0 0
T7 43006 24697 0 0
T8 10633 9349 0 0
T9 5882 1896 0 0
T10 17890 16597 0 0

Line Coverage for Instance : tb.dut.u_daon_lc.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 50919005 25622725 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 50919005 25622725 0 0
T1 24301 2817 0 0
T2 24454 2841 0 0
T3 11772 6888 0 0
T4 123163 39587 0 0
T5 17789 4176 0 0
T6 5729 3019 0 0
T7 89592 35985 0 0
T8 22153 15552 0 0
T9 12256 3940 0 0
T10 37272 34572 0 0

Line Coverage for Instance : tb.dut.u_d0_lc.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 50919005 24896890 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 50919005 24896890 0 0
T1 24301 2328 0 0
T2 24454 2349 0 0
T3 11772 6723 0 0
T4 123163 37096 0 0
T5 17789 3209 0 0
T6 5729 2953 0 0
T7 89592 34403 0 0
T8 22153 15371 0 0
T9 12256 3507 0 0
T10 37272 34505 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 50919005 25622292 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 50919005 25622292 0 0
T1 24301 2817 0 0
T2 24454 2842 0 0
T3 11772 6888 0 0
T4 123163 39537 0 0
T5 17789 4176 0 0
T6 5729 3019 0 0
T7 89592 35985 0 0
T8 22153 15552 0 0
T9 12256 3940 0 0
T10 37272 34572 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 50919005 24898623 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 50919005 24898623 0 0
T1 24301 2328 0 0
T2 24454 2349 0 0
T3 11772 6723 0 0
T4 123163 37163 0 0
T5 17789 3209 0 0
T6 5729 2953 0 0
T7 89592 34403 0 0
T8 22153 15371 0 0
T9 12256 3507 0 0
T10 37272 34505 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_aon.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_aon.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 1543402 758676 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1543402 758676 0 0
T1 730 74 0 0
T2 735 76 0 0
T3 352 201 0 0
T4 3708 1080 0 0
T5 532 123 0 0
T6 170 89 0 0
T7 2759 1087 0 0
T8 664 451 0 0
T9 367 116 0 0
T10 1117 1036 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_io.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 48880762 24597942 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 48880762 24597942 0 0
T1 23329 2746 0 0
T2 23475 2767 0 0
T3 11293 6610 0 0
T4 118204 37965 0 0
T5 17077 4009 0 0
T6 5500 2899 0 0
T7 86001 34537 0 0
T8 21268 14930 0 0
T9 11765 3781 0 0
T10 35781 33188 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 48880762 23899321 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 48880762 23899321 0 0
T1 23329 2234 0 0
T2 23475 2255 0 0
T3 11293 6450 0 0
T4 118204 35677 0 0
T5 17077 3081 0 0
T6 5500 2835 0 0
T7 86001 33017 0 0
T8 21268 14754 0 0
T9 11765 3365 0 0
T10 35781 33124 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 24441330 12288947 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24441330 12288947 0 0
T1 11662 1367 0 0
T2 11735 1381 0 0
T3 5650 3303 0 0
T4 59098 18914 0 0
T5 8538 2003 0 0
T6 2750 1449 0 0
T7 43004 17241 0 0
T8 10633 7458 0 0
T9 5882 1890 0 0
T10 17891 16594 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 24441330 11939877 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24441330 11939877 0 0
T1 11662 1111 0 0
T2 11735 1125 0 0
T3 5650 3223 0 0
T4 59098 17786 0 0
T5 8538 1539 0 0
T6 2750 1417 0 0
T7 43004 16481 0 0
T8 10633 7370 0 0
T9 5882 1682 0 0
T10 17891 16562 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 12220198 6117457 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12220198 6117457 0 0
T1 5829 665 0 0
T2 5865 672 0 0
T3 2825 1645 0 0
T4 29565 9345 0 0
T5 4268 1000 0 0
T6 1373 723 0 0
T7 21505 8555 0 0
T8 5316 3707 0 0
T9 2941 943 0 0
T10 8945 8296 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 12220198 5942861 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12220198 5942861 0 0
T1 5829 537 0 0
T2 5865 544 0 0
T3 2825 1605 0 0
T4 29565 8763 0 0
T5 4268 768 0 0
T6 1373 707 0 0
T7 21505 8175 0 0
T8 5316 3663 0 0
T9 2941 839 0 0
T10 8945 8280 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 12220198 6117457 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12220198 6117457 0 0
T1 5829 665 0 0
T2 5865 672 0 0
T3 2825 1645 0 0
T4 29565 9345 0 0
T5 4268 1000 0 0
T6 1373 723 0 0
T7 21505 8555 0 0
T8 5316 3707 0 0
T9 2941 943 0 0
T10 8945 8296 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 12220198 5942861 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12220198 5942861 0 0
T1 5829 537 0 0
T2 5865 544 0 0
T3 2825 1605 0 0
T4 29565 8763 0 0
T5 4268 768 0 0
T6 1373 707 0 0
T7 21505 8175 0 0
T8 5316 3663 0 0
T9 2941 839 0 0
T10 8945 8280 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 24441375 12288957 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24441375 12288957 0 0
T1 11665 1367 0 0
T2 11733 1381 0 0
T3 5647 3303 0 0
T4 59113 18962 0 0
T5 8538 2003 0 0
T6 2749 1449 0 0
T7 43006 17247 0 0
T8 10633 7458 0 0
T9 5882 1890 0 0
T10 17890 16594 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 24441375 11939413 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24441375 11939413 0 0
T1 11665 1111 0 0
T2 11733 1125 0 0
T3 5647 3223 0 0
T4 59113 17798 0 0
T5 8538 1539 0 0
T6 2749 1417 0 0
T7 43006 16487 0 0
T8 10633 7370 0 0
T9 5882 1682 0 0
T10 17890 16562 0 0

Line Coverage for Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 50919005 24602974 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 50919005 24602974 0 0
T1 24301 2328 0 0
T2 24454 2349 0 0
T3 11772 6647 0 0
T4 123163 35594 0 0
T5 17789 3209 0 0
T6 5729 2953 0 0
T7 89592 33467 0 0
T8 22153 14994 0 0
T9 12256 3507 0 0
T10 37272 34505 0 0

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 12220198 6046934 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12220198 6046934 0 0
T1 5829 675 0 0
T2 5865 682 0 0
T3 2825 1627 0 0
T4 29565 8957 0 0
T5 4268 1000 0 0
T6 1373 723 0 0
T7 21505 8331 0 0
T8 5316 3617 0 0
T9 2941 943 0 0
T10 8945 8296 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 12220198 5822877 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12220198 5822877 0 0
T1 5829 547 0 0
T2 5865 554 0 0
T3 2825 1605 0 0
T4 29565 8747 0 0
T5 4268 768 0 0
T6 1373 707 0 0
T7 21505 8175 0 0
T8 5316 3652 0 0
T9 2941 839 0 0
T10 8945 7779 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 48880762 23403807 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 48880762 23403807 0 0
T1 23329 2234 0 0
T2 23475 2255 0 0
T3 11293 6450 0 0
T4 118204 35677 0 0
T5 17077 3081 0 0
T6 5500 2835 0 0
T7 86001 33017 0 0
T8 21268 14754 0 0
T9 11765 3365 0 0
T10 35781 28610 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 24441330 11695462 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24441330 11695462 0 0
T1 11662 1111 0 0
T2 11735 1125 0 0
T3 5650 3223 0 0
T4 59098 17786 0 0
T5 8538 1539 0 0
T6 2750 1417 0 0
T7 43004 16481 0 0
T8 10633 7370 0 0
T9 5882 1682 0 0
T10 17891 14208 0 0

Line Coverage for Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 24441375 11701645 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24441375 11701645 0 0
T1 11665 1111 0 0
T2 11733 1125 0 0
T3 5647 3223 0 0
T4 59113 17798 0 0
T5 8538 1539 0 0
T6 2749 1417 0 0
T7 43006 16487 0 0
T8 10633 7370 0 0
T9 5882 1682 0 0
T10 17890 13980 0 0

Line Coverage for Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 1543402 721743 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1543402 721743 0 0
T1 730 58 0 0
T2 735 60 0 0
T3 352 196 0 0
T4 3708 1002 0 0
T5 532 94 0 0
T6 170 87 0 0
T7 2759 1039 0 0
T8 664 448 0 0
T9 367 103 0 0
T10 1117 879 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 12220198 5817720 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12220198 5817720 0 0
T1 5829 547 0 0
T2 5865 554 0 0
T3 2825 1605 0 0
T4 29565 8745 0 0
T5 4268 768 0 0
T6 1373 707 0 0
T7 21505 8175 0 0
T8 5316 3663 0 0
T9 2941 839 0 0
T10 8945 7428 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 12220198 5819346 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12220198 5819346 0 0
T1 5829 547 0 0
T2 5865 554 0 0
T3 2825 1585 0 0
T4 29565 8751 0 0
T5 4268 768 0 0
T6 1373 707 0 0
T7 21505 8175 0 0
T8 5316 3663 0 0
T9 2941 839 0 0
T10 8945 7299 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 12220198 5823708 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12220198 5823708 0 0
T1 5829 547 0 0
T2 5865 554 0 0
T3 2825 1605 0 0
T4 29565 8763 0 0
T5 4268 768 0 0
T6 1373 707 0 0
T7 21505 8175 0 0
T8 5316 3663 0 0
T9 2941 839 0 0
T10 8945 7184 0 0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 1543402 895049 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1543402 895049 0 0
T1 730 90 0 0
T2 735 92 0 0
T3 352 232 0 0
T4 3708 1548 0 0
T5 532 127 0 0
T6 170 91 0 0
T7 2759 1623 0 0
T8 664 585 0 0
T9 367 120 0 0
T10 1117 1038 0 0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 1543402 876434 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1543402 876434 0 0
T1 730 74 0 0
T2 735 76 0 0
T3 352 228 0 0
T4 3708 1494 0 0
T5 532 98 0 0
T6 170 89 0 0
T7 2759 1585 0 0
T8 664 583 0 0
T9 367 107 0 0
T10 1117 1036 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%