Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11575447	9396	0	0
alert_regwen_rd_A	11575447	3346	0	0
cpu_regwen_rd_A	11575447	3360	0	0
sw_rst_ctrl_n_0_rd_A	11575447	7115	0	0
sw_rst_ctrl_n_1_rd_A	11575447	6939	0	0
sw_rst_ctrl_n_2_rd_A	11575447	6871	0	0
sw_rst_ctrl_n_3_rd_A	11575447	7056	0	0
sw_rst_ctrl_n_4_rd_A	11575447	6768	0	0
sw_rst_ctrl_n_5_rd_A	11575447	6835	0	0
sw_rst_ctrl_n_6_rd_A	11575447	6946	0	0
sw_rst_ctrl_n_7_rd_A	11575447	7112	0	0
sw_rst_regwen_0_rd_A	11575447	3820	0	0
sw_rst_regwen_1_rd_A	11575447	4001	0	0
sw_rst_regwen_2_rd_A	11575447	3894	0	0
sw_rst_regwen_3_rd_A	11575447	3800	0	0
sw_rst_regwen_4_rd_A	11575447	3986	0	0
sw_rst_regwen_5_rd_A	11575447	3870	0	0
sw_rst_regwen_6_rd_A	11575447	3796	0	0
sw_rst_regwen_7_rd_A	11575447	3852	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11575447	9396	0	0
T66	8945	345	0	0
T67	9246	2	0	0
T68	6859	421	0	0
T69	4144	554	0	0
T74	2311	19	0	0
T75	4061	11	0	0
T87	12404	2	0	0
T98	2647	319	0	0
T99	4167	18	0	0
T103	2542	5	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11575447	3346	0	0
T14	42401	66	0	0
T22	2534	0	0	0
T23	3929	0	0	0
T24	2336	0	0	0
T25	53039	0	0	0
T45	1800	0	0	0
T46	2587	0	0	0
T61	11547	0	0	0
T87	0	32	0	0
T95	77149	129	0	0
T96	56554	0	0	0
T104	0	5	0	0
T105	0	3	0	0
T107	0	5	0	0
T129	0	25	0	0
T130	0	17	0	0
T131	0	29	0	0
T132	0	2	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11575447	3360	0	0
T14	42401	62	0	0
T22	2534	0	0	0
T23	3929	0	0	0
T24	2336	0	0	0
T25	53039	0	0	0
T45	1800	0	0	0
T46	2587	0	0	0
T61	11547	0	0	0
T87	0	28	0	0
T88	0	67	0	0
T95	77149	113	0	0
T96	56554	0	0	0
T104	0	3	0	0
T105	0	2	0	0
T108	0	22	0	0
T129	0	53	0	0
T130	0	33	0	0
T131	0	49	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11575447	7115	0	0
T8	4458	42	0	0
T9	2850	0	0	0
T10	8878	0	0	0
T11	3497	0	0	0
T12	2907	0	0	0
T13	2310	0	0	0
T14	42401	69	0	0
T22	2534	0	0	0
T39	0	62	0	0
T45	1800	0	0	0
T61	11547	122	0	0
T90	0	142	0	0
T94	0	14	0	0
T95	0	283	0	0
T129	0	96	0	0
T133	0	152	0	0
T134	0	22	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11575447	6939	0	0
T8	4458	52	0	0
T9	2850	0	0	0
T10	8878	0	0	0
T11	3497	0	0	0
T12	2907	0	0	0
T13	2310	0	0	0
T14	42401	61	0	0
T22	2534	0	0	0
T39	0	58	0	0
T45	1800	0	0	0
T61	11547	98	0	0
T90	0	172	0	0
T94	0	16	0	0
T95	0	253	0	0
T129	0	128	0	0
T133	0	164	0	0
T134	0	17	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11575447	6871	0	0
T8	4458	57	0	0
T9	2850	0	0	0
T10	8878	0	0	0
T11	3497	0	0	0
T12	2907	0	0	0
T13	2310	0	0	0
T14	42401	47	0	0
T22	2534	0	0	0
T39	0	75	0	0
T45	1800	0	0	0
T61	11547	141	0	0
T90	0	146	0	0
T94	0	14	0	0
T95	0	265	0	0
T129	0	128	0	0
T133	0	143	0	0
T134	0	33	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11575447	7056	0	0
T8	4458	38	0	0
T9	2850	0	0	0
T10	8878	0	0	0
T11	3497	0	0	0
T12	2907	0	0	0
T13	2310	0	0	0
T14	42401	87	0	0
T22	2534	0	0	0
T39	0	58	0	0
T45	1800	0	0	0
T61	11547	122	0	0
T90	0	143	0	0
T94	0	11	0	0
T95	0	261	0	0
T129	0	115	0	0
T133	0	137	0	0
T134	0	15	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11575447	6768	0	0
T8	4458	56	0	0
T9	2850	0	0	0
T10	8878	0	0	0
T11	3497	0	0	0
T12	2907	0	0	0
T13	2310	0	0	0
T14	42401	75	0	0
T22	2534	0	0	0
T39	0	80	0	0
T45	1800	0	0	0
T61	11547	141	0	0
T90	0	161	0	0
T94	0	9	0	0
T95	0	244	0	0
T129	0	137	0	0
T133	0	184	0	0
T134	0	37	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11575447	6835	0	0
T8	4458	42	0	0
T9	2850	0	0	0
T10	8878	0	0	0
T11	3497	0	0	0
T12	2907	0	0	0
T13	2310	0	0	0
T14	42401	61	0	0
T22	2534	0	0	0
T39	0	72	0	0
T45	1800	0	0	0
T61	11547	129	0	0
T90	0	186	0	0
T94	0	15	0	0
T95	0	249	0	0
T129	0	113	0	0
T133	0	129	0	0
T134	0	39	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11575447	6946	0	0
T8	4458	49	0	0
T9	2850	0	0	0
T10	8878	0	0	0
T11	3497	0	0	0
T12	2907	0	0	0
T13	2310	0	0	0
T14	42401	68	0	0
T22	2534	0	0	0
T39	0	54	0	0
T45	1800	0	0	0
T61	11547	115	0	0
T90	0	167	0	0
T94	0	18	0	0
T95	0	292	0	0
T129	0	104	0	0
T133	0	161	0	0
T134	0	11	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11575447	7112	0	0
T8	4458	70	0	0
T9	2850	0	0	0
T10	8878	0	0	0
T11	3497	0	0	0
T12	2907	0	0	0
T13	2310	0	0	0
T14	42401	59	0	0
T22	2534	0	0	0
T39	0	93	0	0
T45	1800	0	0	0
T61	11547	143	0	0
T90	0	159	0	0
T94	0	15	0	0
T95	0	295	0	0
T129	0	90	0	0
T133	0	151	0	0
T134	0	6	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11575447	3820	0	0
T14	42401	72	0	0
T22	2534	0	0	0
T23	3929	0	0	0
T24	2336	0	0	0
T45	1800	0	0	0
T46	2587	0	0	0
T61	11547	18	0	0
T86	5663	0	0	0
T90	10148	24	0	0
T91	1409	0	0	0
T94	0	5	0	0
T95	0	115	0	0
T129	0	54	0	0
T130	0	24	0	0
T131	0	27	0	0
T133	0	35	0	0
T135	0	7	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11575447	4001	0	0
T14	42401	48	0	0
T22	2534	0	0	0
T23	3929	0	0	0
T24	2336	0	0	0
T45	1800	0	0	0
T46	2587	0	0	0
T61	11547	15	0	0
T86	5663	0	0	0
T90	10148	29	0	0
T91	1409	0	0	0
T94	0	16	0	0
T95	0	97	0	0
T129	0	49	0	0
T130	0	23	0	0
T131	0	37	0	0
T133	0	36	0	0
T135	0	2	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11575447	3894	0	0
T14	42401	56	0	0
T22	2534	0	0	0
T23	3929	0	0	0
T24	2336	0	0	0
T45	1800	0	0	0
T46	2587	0	0	0
T61	11547	9	0	0
T86	5663	0	0	0
T90	10148	24	0	0
T91	1409	0	0	0
T94	0	10	0	0
T95	0	91	0	0
T129	0	45	0	0
T130	0	24	0	0
T131	0	31	0	0
T133	0	14	0	0
T135	0	9	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11575447	3800	0	0
T14	42401	64	0	0
T22	2534	0	0	0
T23	3929	0	0	0
T24	2336	0	0	0
T45	1800	0	0	0
T46	2587	0	0	0
T61	11547	29	0	0
T86	5663	0	0	0
T90	10148	18	0	0
T91	1409	0	0	0
T94	0	9	0	0
T95	0	138	0	0
T129	0	27	0	0
T130	0	21	0	0
T131	0	49	0	0
T133	0	21	0	0
T135	0	13	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11575447	3986	0	0
T14	42401	54	0	0
T22	2534	0	0	0
T23	3929	0	0	0
T24	2336	0	0	0
T45	1800	0	0	0
T46	2587	0	0	0
T61	11547	8	0	0
T86	5663	0	0	0
T90	10148	37	0	0
T91	1409	0	0	0
T94	0	11	0	0
T95	0	122	0	0
T129	0	53	0	0
T130	0	32	0	0
T131	0	37	0	0
T133	0	44	0	0
T135	0	10	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11575447	3870	0	0
T14	42401	57	0	0
T22	2534	0	0	0
T23	3929	0	0	0
T24	2336	0	0	0
T45	1800	0	0	0
T46	2587	0	0	0
T61	11547	27	0	0
T86	5663	0	0	0
T90	10148	33	0	0
T91	1409	0	0	0
T94	0	8	0	0
T95	0	108	0	0
T129	0	27	0	0
T130	0	17	0	0
T131	0	29	0	0
T133	0	34	0	0
T135	0	12	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11575447	3796	0	0
T14	42401	61	0	0
T22	2534	0	0	0
T23	3929	0	0	0
T24	2336	0	0	0
T45	1800	0	0	0
T46	2587	0	0	0
T61	11547	14	0	0
T86	5663	0	0	0
T90	10148	32	0	0
T91	1409	0	0	0
T94	0	11	0	0
T95	0	94	0	0
T129	0	35	0	0
T130	0	17	0	0
T131	0	27	0	0
T133	0	27	0	0
T135	0	6	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11575447	3852	0	0
T14	42401	80	0	0
T22	2534	0	0	0
T23	3929	0	0	0
T24	2336	0	0	0
T45	1800	0	0	0
T46	2587	0	0	0
T61	11547	21	0	0
T86	5663	0	0	0
T90	10148	38	0	0
T91	1409	0	0	0
T94	0	2	0	0
T95	0	126	0	0
T129	0	47	0	0
T130	0	30	0	0
T131	0	46	0	0
T133	0	26	0	0
T135	0	7	0	0