Line Coverage for Module :
pwrmgr_rstmgr_sva_if
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
ALWAYS | 33 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
Cond Coverage for Module :
pwrmgr_rstmgr_sva_if
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (((!rst_slow_ni)) || disable_sva)
--------1------- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
Assert Coverage for Module :
pwrmgr_rstmgr_sva_if
Assertion Details
gen_assertions_per_power_domains[0].LcHandshakeOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10787475 |
12839 |
0 |
0 |
T3 |
2587 |
4 |
0 |
0 |
T4 |
26274 |
75 |
0 |
0 |
T5 |
4178 |
0 |
0 |
0 |
T6 |
1284 |
0 |
0 |
0 |
T7 |
16373 |
38 |
0 |
0 |
T8 |
4458 |
14 |
0 |
0 |
T9 |
2850 |
0 |
0 |
0 |
T10 |
8878 |
0 |
0 |
0 |
T11 |
3497 |
4 |
0 |
0 |
T12 |
2907 |
20 |
0 |
0 |
T14 |
0 |
43 |
0 |
0 |
T22 |
0 |
4 |
0 |
0 |
T23 |
0 |
4 |
0 |
0 |
T24 |
0 |
4 |
0 |
0 |
gen_assertions_per_power_domains[0].LcHandshakeOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10787475 |
118523 |
0 |
0 |
T3 |
2587 |
37 |
0 |
0 |
T4 |
26274 |
709 |
0 |
0 |
T5 |
4178 |
0 |
0 |
0 |
T6 |
1284 |
0 |
0 |
0 |
T7 |
16373 |
342 |
0 |
0 |
T8 |
4458 |
126 |
0 |
0 |
T9 |
2850 |
0 |
0 |
0 |
T10 |
8878 |
0 |
0 |
0 |
T11 |
3497 |
38 |
0 |
0 |
T12 |
2907 |
180 |
0 |
0 |
T14 |
0 |
391 |
0 |
0 |
T22 |
0 |
38 |
0 |
0 |
T23 |
0 |
37 |
0 |
0 |
T24 |
0 |
38 |
0 |
0 |
gen_assertions_per_power_domains[0].SysHandshakeOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10787475 |
5951513 |
0 |
0 |
T1 |
5286 |
570 |
0 |
0 |
T2 |
5514 |
585 |
0 |
0 |
T3 |
2587 |
1611 |
0 |
0 |
T4 |
26274 |
8778 |
0 |
0 |
T5 |
4178 |
774 |
0 |
0 |
T6 |
1284 |
710 |
0 |
0 |
T7 |
16373 |
8146 |
0 |
0 |
T8 |
4458 |
3626 |
0 |
0 |
T9 |
2850 |
844 |
0 |
0 |
T10 |
8878 |
8283 |
0 |
0 |
gen_assertions_per_power_domains[0].SysHandshakeOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10787475 |
189083 |
0 |
0 |
T3 |
2587 |
55 |
0 |
0 |
T4 |
26274 |
1084 |
0 |
0 |
T5 |
4178 |
0 |
0 |
0 |
T6 |
1284 |
0 |
0 |
0 |
T7 |
16373 |
566 |
0 |
0 |
T8 |
4458 |
216 |
0 |
0 |
T9 |
2850 |
0 |
0 |
0 |
T10 |
8878 |
0 |
0 |
0 |
T11 |
3497 |
68 |
0 |
0 |
T12 |
2907 |
277 |
0 |
0 |
T14 |
0 |
616 |
0 |
0 |
T22 |
0 |
69 |
0 |
0 |
T23 |
0 |
57 |
0 |
0 |
T24 |
0 |
53 |
0 |
0 |
gen_assertions_per_power_domains[1].LcHandshakeOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10787475 |
12839 |
0 |
0 |
T3 |
2587 |
4 |
0 |
0 |
T4 |
26274 |
75 |
0 |
0 |
T5 |
4178 |
0 |
0 |
0 |
T6 |
1284 |
0 |
0 |
0 |
T7 |
16373 |
38 |
0 |
0 |
T8 |
4458 |
14 |
0 |
0 |
T9 |
2850 |
0 |
0 |
0 |
T10 |
8878 |
0 |
0 |
0 |
T11 |
3497 |
4 |
0 |
0 |
T12 |
2907 |
20 |
0 |
0 |
T14 |
0 |
43 |
0 |
0 |
T22 |
0 |
4 |
0 |
0 |
T23 |
0 |
4 |
0 |
0 |
T24 |
0 |
4 |
0 |
0 |
gen_assertions_per_power_domains[1].LcHandshakeOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10787475 |
118523 |
0 |
0 |
T3 |
2587 |
37 |
0 |
0 |
T4 |
26274 |
709 |
0 |
0 |
T5 |
4178 |
0 |
0 |
0 |
T6 |
1284 |
0 |
0 |
0 |
T7 |
16373 |
342 |
0 |
0 |
T8 |
4458 |
126 |
0 |
0 |
T9 |
2850 |
0 |
0 |
0 |
T10 |
8878 |
0 |
0 |
0 |
T11 |
3497 |
38 |
0 |
0 |
T12 |
2907 |
180 |
0 |
0 |
T14 |
0 |
391 |
0 |
0 |
T22 |
0 |
38 |
0 |
0 |
T23 |
0 |
37 |
0 |
0 |
T24 |
0 |
38 |
0 |
0 |
gen_assertions_per_power_domains[1].SysHandshakeOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10787475 |
5951513 |
0 |
0 |
T1 |
5286 |
570 |
0 |
0 |
T2 |
5514 |
585 |
0 |
0 |
T3 |
2587 |
1611 |
0 |
0 |
T4 |
26274 |
8778 |
0 |
0 |
T5 |
4178 |
774 |
0 |
0 |
T6 |
1284 |
710 |
0 |
0 |
T7 |
16373 |
8146 |
0 |
0 |
T8 |
4458 |
3626 |
0 |
0 |
T9 |
2850 |
844 |
0 |
0 |
T10 |
8878 |
8283 |
0 |
0 |
gen_assertions_per_power_domains[1].SysHandshakeOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10787475 |
189083 |
0 |
0 |
T3 |
2587 |
55 |
0 |
0 |
T4 |
26274 |
1084 |
0 |
0 |
T5 |
4178 |
0 |
0 |
0 |
T6 |
1284 |
0 |
0 |
0 |
T7 |
16373 |
566 |
0 |
0 |
T8 |
4458 |
216 |
0 |
0 |
T9 |
2850 |
0 |
0 |
0 |
T10 |
8878 |
0 |
0 |
0 |
T11 |
3497 |
68 |
0 |
0 |
T12 |
2907 |
277 |
0 |
0 |
T14 |
0 |
616 |
0 |
0 |
T22 |
0 |
69 |
0 |
0 |
T23 |
0 |
57 |
0 |
0 |
T24 |
0 |
53 |
0 |
0 |