Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T11
0	1	Covered	T7,T11,T14
1	0	Covered	T3,T7,T14

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T3,T7,T11
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	50919005	8848	0	0
CascadeEffAonToRstPorAboveRise_A	50919005	8848	0	0
CascadeEffAonToRstPorIoAboveFall_A	48880762	8848	0	0
CascadeEffAonToRstPorIoAboveRise_A	48880762	8848	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	24441330	8848	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	24441330	8848	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12220198	8848	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12220198	8848	0	0
CascadeEffAonToRstPorUcbAboveFall_A	24441375	8848	0	0
CascadeEffAonToRstPorUcbAboveRise_A	24441375	8848	0	0
CascadeLcToLcAboveFall_A	50919005	21687	0	0
CascadeLcToLcAboveRise_A	50919005	21687	0	0
CascadeLcToLcAonAboveFall_A	1543402	21687	0	0
CascadeLcToLcAonAboveRise_A	1543402	21687	0	0
CascadeLcToLcShadowedAboveFall_A	50919005	21687	0	0
CascadeLcToLcShadowedAboveRise_A	50919005	21687	0	0
CascadePorToAonAboveFall_A	1543402	7101	0	0
CascadeSysToSysAboveFall_A	50919005	21687	0	0
CascadeSysToSysAboveRise_A	50919005	21687	0	0
ScanRstToAonRise_A	1543402	216	0	0
StablePorToAonRise_A	1543402	8848	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	10787475	21687	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	10787475	21687	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	10787475	21687	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	10787475	21687	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12220198	21687	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12220198	21687	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	10787475	21687	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	10787475	21687	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	10787475	21687	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	10787475	21687	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50919005	8848	0	0
T1	24301	8	0	0
T2	24454	8	0	0
T3	11772	2	0	0
T4	123163	27	0	0
T5	17789	2	0	0
T6	5729	1	0	0
T7	89592	19	0	0
T8	22153	1	0	0
T9	12256	2	0	0
T10	37272	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50919005	8848	0	0
T1	24301	8	0	0
T2	24454	8	0	0
T3	11772	2	0	0
T4	123163	27	0	0
T5	17789	2	0	0
T6	5729	1	0	0
T7	89592	19	0	0
T8	22153	1	0	0
T9	12256	2	0	0
T10	37272	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48880762	8848	0	0
T1	23329	8	0	0
T2	23475	8	0	0
T3	11293	2	0	0
T4	118204	27	0	0
T5	17077	2	0	0
T6	5500	1	0	0
T7	86001	19	0	0
T8	21268	1	0	0
T9	11765	2	0	0
T10	35781	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48880762	8848	0	0
T1	23329	8	0	0
T2	23475	8	0	0
T3	11293	2	0	0
T4	118204	27	0	0
T5	17077	2	0	0
T6	5500	1	0	0
T7	86001	19	0	0
T8	21268	1	0	0
T9	11765	2	0	0
T10	35781	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24441330	8848	0	0
T1	11662	8	0	0
T2	11735	8	0	0
T3	5650	2	0	0
T4	59098	27	0	0
T5	8538	2	0	0
T6	2750	1	0	0
T7	43004	19	0	0
T8	10633	1	0	0
T9	5882	2	0	0
T10	17891	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24441330	8848	0	0
T1	11662	8	0	0
T2	11735	8	0	0
T3	5650	2	0	0
T4	59098	27	0	0
T5	8538	2	0	0
T6	2750	1	0	0
T7	43004	19	0	0
T8	10633	1	0	0
T9	5882	2	0	0
T10	17891	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12220198	8848	0	0
T1	5829	8	0	0
T2	5865	8	0	0
T3	2825	2	0	0
T4	29565	27	0	0
T5	4268	2	0	0
T6	1373	1	0	0
T7	21505	19	0	0
T8	5316	1	0	0
T9	2941	2	0	0
T10	8945	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12220198	8848	0	0
T1	5829	8	0	0
T2	5865	8	0	0
T3	2825	2	0	0
T4	29565	27	0	0
T5	4268	2	0	0
T6	1373	1	0	0
T7	21505	19	0	0
T8	5316	1	0	0
T9	2941	2	0	0
T10	8945	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24441375	8848	0	0
T1	11665	8	0	0
T2	11733	8	0	0
T3	5647	2	0	0
T4	59113	27	0	0
T5	8538	2	0	0
T6	2749	1	0	0
T7	43006	19	0	0
T8	10633	1	0	0
T9	5882	2	0	0
T10	17890	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24441375	8848	0	0
T1	11665	8	0	0
T2	11733	8	0	0
T3	5647	2	0	0
T4	59113	27	0	0
T5	8538	2	0	0
T6	2749	1	0	0
T7	43006	19	0	0
T8	10633	1	0	0
T9	5882	2	0	0
T10	17890	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50919005	21687	0	0
T1	24301	8	0	0
T2	24454	8	0	0
T3	11772	6	0	0
T4	123163	102	0	0
T5	17789	2	0	0
T6	5729	1	0	0
T7	89592	57	0	0
T8	22153	15	0	0
T9	12256	2	0	0
T10	37272	1	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50919005	21687	0	0
T1	24301	8	0	0
T2	24454	8	0	0
T3	11772	6	0	0
T4	123163	102	0	0
T5	17789	2	0	0
T6	5729	1	0	0
T7	89592	57	0	0
T8	22153	15	0	0
T9	12256	2	0	0
T10	37272	1	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1543402	21687	0	0
T1	730	8	0	0
T2	735	8	0	0
T3	352	6	0	0
T4	3708	102	0	0
T5	532	2	0	0
T6	170	1	0	0
T7	2759	57	0	0
T8	664	15	0	0
T9	367	2	0	0
T10	1117	1	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1543402	21687	0	0
T1	730	8	0	0
T2	735	8	0	0
T3	352	6	0	0
T4	3708	102	0	0
T5	532	2	0	0
T6	170	1	0	0
T7	2759	57	0	0
T8	664	15	0	0
T9	367	2	0	0
T10	1117	1	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50919005	21687	0	0
T1	24301	8	0	0
T2	24454	8	0	0
T3	11772	6	0	0
T4	123163	102	0	0
T5	17789	2	0	0
T6	5729	1	0	0
T7	89592	57	0	0
T8	22153	15	0	0
T9	12256	2	0	0
T10	37272	1	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50919005	21687	0	0
T1	24301	8	0	0
T2	24454	8	0	0
T3	11772	6	0	0
T4	123163	102	0	0
T5	17789	2	0	0
T6	5729	1	0	0
T7	89592	57	0	0
T8	22153	15	0	0
T9	12256	2	0	0
T10	37272	1	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1543402	7101	0	0
T1	730	8	0	0
T2	735	8	0	0
T3	352	1	0	0
T4	3708	27	0	0
T5	532	14	0	0
T6	170	1	0	0
T7	2759	7	0	0
T8	664	1	0	0
T9	367	7	0	0
T10	1117	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50919005	21687	0	0
T1	24301	8	0	0
T2	24454	8	0	0
T3	11772	6	0	0
T4	123163	102	0	0
T5	17789	2	0	0
T6	5729	1	0	0
T7	89592	57	0	0
T8	22153	15	0	0
T9	12256	2	0	0
T10	37272	1	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50919005	21687	0	0
T1	24301	8	0	0
T2	24454	8	0	0
T3	11772	6	0	0
T4	123163	102	0	0
T5	17789	2	0	0
T6	5729	1	0	0
T7	89592	57	0	0
T8	22153	15	0	0
T9	12256	2	0	0
T10	37272	1	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1543402	216	0	0
T14	6151	3	0	0
T22	335	0	0	0
T23	526	0	0	0
T24	313	0	0	0
T45	236	0	0	0
T46	359	1	0	0
T47	10220	3	0	0
T48	983	0	0	0
T53	0	1	0	0
T56	0	1	0	0
T58	0	3	0	0
T61	1447	0	0	0
T92	397	0	0	0
T95	0	1	0	0
T96	0	2	0	0
T97	0	4	0	0
T110	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1543402	8848	0	0
T1	730	8	0	0
T2	735	8	0	0
T3	352	2	0	0
T4	3708	27	0	0
T5	532	2	0	0
T6	170	1	0	0
T7	2759	19	0	0
T8	664	1	0	0
T9	367	2	0	0
T10	1117	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10787475	21687	0	0
T1	5286	8	0	0
T2	5514	8	0	0
T3	2587	6	0	0
T4	26274	102	0	0
T5	4178	2	0	0
T6	1284	1	0	0
T7	16373	57	0	0
T8	4458	15	0	0
T9	2850	2	0	0
T10	8878	1	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10787475	21687	0	0
T1	5286	8	0	0
T2	5514	8	0	0
T3	2587	6	0	0
T4	26274	102	0	0
T5	4178	2	0	0
T6	1284	1	0	0
T7	16373	57	0	0
T8	4458	15	0	0
T9	2850	2	0	0
T10	8878	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10787475	21687	0	0
T1	5286	8	0	0
T2	5514	8	0	0
T3	2587	6	0	0
T4	26274	102	0	0
T5	4178	2	0	0
T6	1284	1	0	0
T7	16373	57	0	0
T8	4458	15	0	0
T9	2850	2	0	0
T10	8878	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10787475	21687	0	0
T1	5286	8	0	0
T2	5514	8	0	0
T3	2587	6	0	0
T4	26274	102	0	0
T5	4178	2	0	0
T6	1284	1	0	0
T7	16373	57	0	0
T8	4458	15	0	0
T9	2850	2	0	0
T10	8878	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12220198	21687	0	0
T1	5829	8	0	0
T2	5865	8	0	0
T3	2825	6	0	0
T4	29565	102	0	0
T5	4268	2	0	0
T6	1373	1	0	0
T7	21505	57	0	0
T8	5316	15	0	0
T9	2941	2	0	0
T10	8945	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12220198	21687	0	0
T1	5829	8	0	0
T2	5865	8	0	0
T3	2825	6	0	0
T4	29565	102	0	0
T5	4268	2	0	0
T6	1373	1	0	0
T7	21505	57	0	0
T8	5316	15	0	0
T9	2941	2	0	0
T10	8945	1	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10787475	21687	0	0
T1	5286	8	0	0
T2	5514	8	0	0
T3	2587	6	0	0
T4	26274	102	0	0
T5	4178	2	0	0
T6	1284	1	0	0
T7	16373	57	0	0
T8	4458	15	0	0
T9	2850	2	0	0
T10	8878	1	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10787475	21687	0	0
T1	5286	8	0	0
T2	5514	8	0	0
T3	2587	6	0	0
T4	26274	102	0	0
T5	4178	2	0	0
T6	1284	1	0	0
T7	16373	57	0	0
T8	4458	15	0	0
T9	2850	2	0	0
T10	8878	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10787475	21687	0	0
T1	5286	8	0	0
T2	5514	8	0	0
T3	2587	6	0	0
T4	26274	102	0	0
T5	4178	2	0	0
T6	1284	1	0	0
T7	16373	57	0	0
T8	4458	15	0	0
T9	2850	2	0	0
T10	8878	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10787475	21687	0	0
T1	5286	8	0	0
T2	5514	8	0	0
T3	2587	6	0	0
T4	26274	102	0	0
T5	4178	2	0	0
T6	1284	1	0	0
T7	16373	57	0	0
T8	4458	15	0	0
T9	2850	2	0	0
T10	8878	1	0	0