Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1600 |
1 |
|
|
T6 |
32 |
|
T39 |
32 |
|
T40 |
32 |
auto[1] |
4389 |
1 |
|
|
T6 |
31 |
|
T7 |
3 |
|
T8 |
3 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1600 |
1 |
|
|
T6 |
32 |
|
T39 |
32 |
|
T40 |
32 |
auto[1] |
4389 |
1 |
|
|
T6 |
31 |
|
T7 |
3 |
|
T8 |
3 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1754 |
1 |
|
|
T6 |
16 |
|
T7 |
1 |
|
T8 |
1 |
auto[1] |
4235 |
1 |
|
|
T6 |
47 |
|
T7 |
2 |
|
T8 |
2 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1754 |
1 |
|
|
T6 |
16 |
|
T7 |
1 |
|
T8 |
1 |
auto[1] |
4235 |
1 |
|
|
T6 |
47 |
|
T7 |
2 |
|
T8 |
2 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
400 |
1 |
|
|
T6 |
8 |
|
T39 |
8 |
|
T40 |
8 |
auto[0] |
auto[1] |
1200 |
1 |
|
|
T6 |
24 |
|
T39 |
24 |
|
T40 |
24 |
auto[1] |
auto[0] |
1354 |
1 |
|
|
T6 |
8 |
|
T7 |
1 |
|
T8 |
1 |
auto[1] |
auto[1] |
3035 |
1 |
|
|
T6 |
23 |
|
T7 |
2 |
|
T8 |
2 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1469 |
1 |
|
|
T6 |
28 |
|
T39 |
28 |
|
T40 |
28 |
auto[1] |
4275 |
1 |
|
|
T6 |
35 |
|
T7 |
3 |
|
T8 |
3 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1469 |
1 |
|
|
T6 |
28 |
|
T39 |
28 |
|
T40 |
28 |
auto[1] |
4275 |
1 |
|
|
T6 |
35 |
|
T7 |
3 |
|
T8 |
3 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1646 |
1 |
|
|
T6 |
21 |
|
T12 |
9 |
|
T39 |
15 |
auto[1] |
4098 |
1 |
|
|
T6 |
42 |
|
T7 |
3 |
|
T8 |
3 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1646 |
1 |
|
|
T6 |
21 |
|
T12 |
9 |
|
T39 |
15 |
auto[1] |
4098 |
1 |
|
|
T6 |
42 |
|
T7 |
3 |
|
T8 |
3 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
384 |
1 |
|
|
T6 |
7 |
|
T39 |
7 |
|
T40 |
7 |
auto[0] |
auto[1] |
1085 |
1 |
|
|
T6 |
21 |
|
T39 |
21 |
|
T40 |
21 |
auto[1] |
auto[0] |
1262 |
1 |
|
|
T6 |
14 |
|
T12 |
9 |
|
T39 |
8 |
auto[1] |
auto[1] |
3013 |
1 |
|
|
T6 |
21 |
|
T7 |
3 |
|
T8 |
3 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1275 |
1 |
|
|
T6 |
24 |
|
T39 |
24 |
|
T40 |
24 |
auto[1] |
4385 |
1 |
|
|
T6 |
39 |
|
T7 |
3 |
|
T8 |
3 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1275 |
1 |
|
|
T6 |
24 |
|
T39 |
24 |
|
T40 |
24 |
auto[1] |
4385 |
1 |
|
|
T6 |
39 |
|
T7 |
3 |
|
T8 |
3 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1615 |
1 |
|
|
T6 |
22 |
|
T12 |
4 |
|
T39 |
16 |
auto[1] |
4045 |
1 |
|
|
T6 |
41 |
|
T7 |
3 |
|
T8 |
3 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1615 |
1 |
|
|
T6 |
22 |
|
T12 |
4 |
|
T39 |
16 |
auto[1] |
4045 |
1 |
|
|
T6 |
41 |
|
T7 |
3 |
|
T8 |
3 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
337 |
1 |
|
|
T6 |
6 |
|
T39 |
6 |
|
T40 |
6 |
auto[0] |
auto[1] |
938 |
1 |
|
|
T6 |
18 |
|
T39 |
18 |
|
T40 |
18 |
auto[1] |
auto[0] |
1278 |
1 |
|
|
T6 |
16 |
|
T12 |
4 |
|
T39 |
10 |
auto[1] |
auto[1] |
3107 |
1 |
|
|
T6 |
23 |
|
T7 |
3 |
|
T8 |
3 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1078 |
1 |
|
|
T6 |
20 |
|
T8 |
3 |
|
T39 |
20 |
auto[1] |
4570 |
1 |
|
|
T6 |
43 |
|
T7 |
3 |
|
T12 |
25 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1078 |
1 |
|
|
T6 |
20 |
|
T8 |
3 |
|
T39 |
20 |
auto[1] |
4570 |
1 |
|
|
T6 |
43 |
|
T7 |
3 |
|
T12 |
25 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1549 |
1 |
|
|
T6 |
18 |
|
T7 |
1 |
|
T8 |
2 |
auto[1] |
4099 |
1 |
|
|
T6 |
45 |
|
T7 |
2 |
|
T8 |
1 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1549 |
1 |
|
|
T6 |
18 |
|
T7 |
1 |
|
T8 |
2 |
auto[1] |
4099 |
1 |
|
|
T6 |
45 |
|
T7 |
2 |
|
T8 |
1 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
290 |
1 |
|
|
T6 |
5 |
|
T8 |
2 |
|
T39 |
5 |
auto[0] |
auto[1] |
788 |
1 |
|
|
T6 |
15 |
|
T8 |
1 |
|
T39 |
15 |
auto[1] |
auto[0] |
1259 |
1 |
|
|
T6 |
13 |
|
T7 |
1 |
|
T12 |
6 |
auto[1] |
auto[1] |
3311 |
1 |
|
|
T6 |
30 |
|
T7 |
2 |
|
T12 |
19 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
875 |
1 |
|
|
T6 |
16 |
|
T7 |
3 |
|
T39 |
16 |
auto[1] |
4773 |
1 |
|
|
T6 |
47 |
|
T8 |
3 |
|
T12 |
25 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
875 |
1 |
|
|
T6 |
16 |
|
T7 |
3 |
|
T39 |
16 |
auto[1] |
4773 |
1 |
|
|
T6 |
47 |
|
T8 |
3 |
|
T12 |
25 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1557 |
1 |
|
|
T6 |
19 |
|
T7 |
2 |
|
T8 |
1 |
auto[1] |
4091 |
1 |
|
|
T6 |
44 |
|
T7 |
1 |
|
T8 |
2 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1557 |
1 |
|
|
T6 |
19 |
|
T7 |
2 |
|
T8 |
1 |
auto[1] |
4091 |
1 |
|
|
T6 |
44 |
|
T7 |
1 |
|
T8 |
2 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
236 |
1 |
|
|
T6 |
4 |
|
T7 |
2 |
|
T39 |
4 |
auto[0] |
auto[1] |
639 |
1 |
|
|
T6 |
12 |
|
T7 |
1 |
|
T39 |
12 |
auto[1] |
auto[0] |
1321 |
1 |
|
|
T6 |
15 |
|
T8 |
1 |
|
T12 |
7 |
auto[1] |
auto[1] |
3452 |
1 |
|
|
T6 |
32 |
|
T8 |
2 |
|
T12 |
18 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
654 |
1 |
|
|
T6 |
12 |
|
T39 |
12 |
|
T40 |
12 |
auto[1] |
4994 |
1 |
|
|
T6 |
51 |
|
T7 |
3 |
|
T8 |
3 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
654 |
1 |
|
|
T6 |
12 |
|
T39 |
12 |
|
T40 |
12 |
auto[1] |
4994 |
1 |
|
|
T6 |
51 |
|
T7 |
3 |
|
T8 |
3 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1597 |
1 |
|
|
T6 |
18 |
|
T8 |
1 |
|
T12 |
12 |
auto[1] |
4051 |
1 |
|
|
T6 |
45 |
|
T7 |
3 |
|
T8 |
2 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1597 |
1 |
|
|
T6 |
18 |
|
T8 |
1 |
|
T12 |
12 |
auto[1] |
4051 |
1 |
|
|
T6 |
45 |
|
T7 |
3 |
|
T8 |
2 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
175 |
1 |
|
|
T6 |
3 |
|
T39 |
3 |
|
T40 |
3 |
auto[0] |
auto[1] |
479 |
1 |
|
|
T6 |
9 |
|
T39 |
9 |
|
T40 |
9 |
auto[1] |
auto[0] |
1422 |
1 |
|
|
T6 |
15 |
|
T8 |
1 |
|
T12 |
12 |
auto[1] |
auto[1] |
3572 |
1 |
|
|
T6 |
36 |
|
T7 |
3 |
|
T8 |
2 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
475 |
1 |
|
|
T6 |
8 |
|
T7 |
3 |
|
T8 |
3 |
auto[1] |
5173 |
1 |
|
|
T6 |
55 |
|
T12 |
25 |
|
T39 |
47 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
475 |
1 |
|
|
T6 |
8 |
|
T7 |
3 |
|
T8 |
3 |
auto[1] |
5173 |
1 |
|
|
T6 |
55 |
|
T12 |
25 |
|
T39 |
47 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1588 |
1 |
|
|
T6 |
18 |
|
T7 |
2 |
|
T8 |
1 |
auto[1] |
4060 |
1 |
|
|
T6 |
45 |
|
T7 |
1 |
|
T8 |
2 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1588 |
1 |
|
|
T6 |
18 |
|
T7 |
2 |
|
T8 |
1 |
auto[1] |
4060 |
1 |
|
|
T6 |
45 |
|
T7 |
1 |
|
T8 |
2 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
138 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T8 |
1 |
auto[0] |
auto[1] |
337 |
1 |
|
|
T6 |
6 |
|
T7 |
1 |
|
T8 |
2 |
auto[1] |
auto[0] |
1450 |
1 |
|
|
T6 |
16 |
|
T12 |
10 |
|
T39 |
15 |
auto[1] |
auto[1] |
3723 |
1 |
|
|
T6 |
39 |
|
T12 |
15 |
|
T39 |
32 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
257 |
1 |
|
|
T6 |
4 |
|
T8 |
3 |
|
T39 |
4 |
auto[1] |
5391 |
1 |
|
|
T6 |
59 |
|
T7 |
3 |
|
T12 |
25 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
257 |
1 |
|
|
T6 |
4 |
|
T8 |
3 |
|
T39 |
4 |
auto[1] |
5391 |
1 |
|
|
T6 |
59 |
|
T7 |
3 |
|
T12 |
25 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1569 |
1 |
|
|
T6 |
17 |
|
T8 |
2 |
|
T12 |
7 |
auto[1] |
4079 |
1 |
|
|
T6 |
46 |
|
T7 |
3 |
|
T8 |
1 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1569 |
1 |
|
|
T6 |
17 |
|
T8 |
2 |
|
T12 |
7 |
auto[1] |
4079 |
1 |
|
|
T6 |
46 |
|
T7 |
3 |
|
T8 |
1 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
83 |
1 |
|
|
T6 |
1 |
|
T8 |
2 |
|
T39 |
1 |
auto[0] |
auto[1] |
174 |
1 |
|
|
T6 |
3 |
|
T8 |
1 |
|
T39 |
3 |
auto[1] |
auto[0] |
1486 |
1 |
|
|
T6 |
16 |
|
T12 |
7 |
|
T39 |
14 |
auto[1] |
auto[1] |
3905 |
1 |
|
|
T6 |
43 |
|
T7 |
3 |
|
T12 |
18 |