Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	587594	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

353758

1

T1

1151

T3

79

T4

1085

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	501499	1			T1	1500		T2	1		T3	99
values[0x0]	219571	1			T1	869		T3	47		T4	876
values[0x1]	220282	1			T1	831		T3	66		T4	824

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	493193	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

448159

1

T1

1446

T2

1

T3

99

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3969	1			T4	11		T8	5		T9	1
valid_sources[0x01]	4121	1			T3	3		T4	16		T7	3
valid_sources[0x02]	3451	1			T4	15		T7	4		T8	1
valid_sources[0x03]	3156	1			T3	6		T4	10		T7	1
valid_sources[0x04]	3694	1			T4	13		T6	27		T7	1
valid_sources[0x05]	3237	1			T4	11		T7	4		T8	1
valid_sources[0x06]	3266	1			T4	16		T7	2		T12	15
valid_sources[0x07]	3014	1			T4	10		T6	4		T8	5
valid_sources[0x08]	3074	1			T4	14		T9	3		T12	20
valid_sources[0x09]	3354	1			T4	11		T9	1		T12	38
valid_sources[0x0a]	3109	1			T3	1		T4	9		T8	1
valid_sources[0x0b]	3884	1			T4	10		T7	1		T8	2
valid_sources[0x0c]	3467	1			T4	10		T6	5		T7	2
valid_sources[0x0d]	3479	1			T4	8		T6	5		T8	9
valid_sources[0x0e]	3817	1			T3	5		T4	10		T9	1
valid_sources[0x0f]	3105	1			T3	2		T4	12		T6	11
valid_sources[0x10]	4483	1			T4	15		T6	18		T7	1
valid_sources[0x11]	3671	1			T4	13		T6	5		T7	1
valid_sources[0x12]	3378	1			T3	1		T4	13		T6	8
valid_sources[0x13]	3723	1			T4	10		T6	8		T7	3
valid_sources[0x14]	3383	1			T4	14		T6	13		T7	1
valid_sources[0x15]	3787	1			T4	13		T6	11		T9	1
valid_sources[0x16]	6539	1			T4	12		T7	2		T8	3
valid_sources[0x17]	3383	1			T4	12		T7	2		T8	3
valid_sources[0x18]	3176	1			T4	10		T12	17		T20	11
valid_sources[0x19]	3247	1			T4	13		T7	2		T9	2
valid_sources[0x1a]	3294	1			T4	14		T7	1		T8	1
valid_sources[0x1b]	4254	1			T3	2		T4	16		T6	1
valid_sources[0x1c]	3555	1			T4	16		T8	4		T12	29
valid_sources[0x1d]	4204	1			T4	19		T7	1		T9	1
valid_sources[0x1e]	3218	1			T4	17		T6	1		T7	1
valid_sources[0x1f]	3480	1			T4	13		T6	6		T7	1
valid_sources[0x20]	4837	1			T3	1		T4	21		T7	1
valid_sources[0x21]	3335	1			T4	14		T6	9		T7	2
valid_sources[0x22]	2991	1			T3	2		T4	9		T7	1
valid_sources[0x23]	3798	1			T4	13		T6	2		T8	5
valid_sources[0x24]	3140	1			T3	2		T4	6		T6	16
valid_sources[0x25]	3304	1			T3	1		T4	14		T7	2
valid_sources[0x26]	3902	1			T3	3		T4	11		T9	1
valid_sources[0x27]	4850	1			T4	11		T6	3		T7	1
valid_sources[0x28]	3268	1			T4	13		T6	7		T7	1
valid_sources[0x29]	3495	1			T4	11		T6	4		T7	2
valid_sources[0x2a]	3171	1			T4	11		T6	9		T7	1
valid_sources[0x2b]	3991	1			T3	3		T4	13		T6	3
valid_sources[0x2c]	3069	1			T4	15		T6	8		T7	2
valid_sources[0x2d]	3318	1			T3	1		T4	13		T8	1
valid_sources[0x2e]	4142	1			T4	14		T6	4		T7	1
valid_sources[0x2f]	3143	1			T4	10		T6	11		T7	1
valid_sources[0x30]	3411	1			T4	14		T6	3		T7	5
valid_sources[0x31]	3242	1			T4	10		T6	8		T7	4
valid_sources[0x32]	4904	1			T4	16		T6	1		T7	2
valid_sources[0x33]	3068	1			T4	23		T6	16		T7	1
valid_sources[0x34]	3604	1			T4	15		T7	1		T12	39
valid_sources[0x35]	3483	1			T4	18		T8	1		T12	26
valid_sources[0x36]	3237	1			T4	9		T8	1		T12	30
valid_sources[0x37]	3061	1			T3	3		T4	15		T7	2
valid_sources[0x38]	3830	1			T4	10		T6	15		T7	1
valid_sources[0x39]	3722	1			T4	7		T6	2		T7	1
valid_sources[0x3a]	3222	1			T3	7		T4	8		T7	3
valid_sources[0x3b]	3808	1			T4	7		T7	1		T8	3
valid_sources[0x3c]	3785	1			T4	15		T7	4		T8	1
valid_sources[0x3d]	4798	1			T3	1		T4	11		T9	1
valid_sources[0x3e]	3908	1			T4	11		T6	9		T8	1
valid_sources[0x3f]	3502	1			T4	15		T7	2		T8	1
valid_sources[0x40]	3276	1			T4	10		T6	3		T7	2
valid_sources[0x41]	3413	1			T4	10		T6	4		T7	1
valid_sources[0x42]	3381	1			T4	18		T6	4		T7	6
valid_sources[0x43]	3512	1			T3	1		T4	15		T7	1
valid_sources[0x44]	3038	1			T3	2		T4	11		T7	1
valid_sources[0x45]	3157	1			T4	12		T6	10		T7	1
valid_sources[0x46]	3184	1			T4	15		T8	6		T12	12
valid_sources[0x47]	3048	1			T4	12		T7	2		T8	1
valid_sources[0x48]	3901	1			T4	16		T6	6		T7	2
valid_sources[0x49]	3416	1			T4	14		T7	5		T8	6
valid_sources[0x4a]	6725	1			T3	3		T4	11		T8	2
valid_sources[0x4b]	2874	1			T3	2		T4	9		T7	3
valid_sources[0x4c]	3073	1			T4	14		T6	15		T9	1
valid_sources[0x4d]	4036	1			T4	11		T6	2		T7	1
valid_sources[0x4e]	3140	1			T4	13		T6	1		T7	3
valid_sources[0x4f]	3420	1			T4	18		T8	7		T12	26
valid_sources[0x50]	3427	1			T3	2		T4	13		T6	3
valid_sources[0x51]	3615	1			T3	1		T4	13		T6	2
valid_sources[0x52]	3981	1			T4	16		T6	18		T8	1
valid_sources[0x53]	3809	1			T4	13		T7	3		T8	2
valid_sources[0x54]	3952	1			T3	1		T4	11		T7	2
valid_sources[0x55]	4390	1			T4	9		T6	17		T12	20
valid_sources[0x56]	3738	1			T4	9		T6	10		T7	3
valid_sources[0x57]	3466	1			T3	5		T4	12		T7	1
valid_sources[0x58]	3886	1			T4	13		T7	1		T8	1
valid_sources[0x59]	3805	1			T3	5		T4	7		T7	4
valid_sources[0x5a]	3009	1			T4	14		T7	2		T9	2
valid_sources[0x5b]	3712	1			T3	1		T4	8		T8	4
valid_sources[0x5c]	4334	1			T3	2		T4	13		T6	11
valid_sources[0x5d]	3597	1			T3	2		T4	15		T6	18
valid_sources[0x5e]	3733	1			T4	14		T6	6		T7	1
valid_sources[0x5f]	3148	1			T3	4		T4	16		T6	23
valid_sources[0x60]	4448	1			T3	1		T4	11		T7	1
valid_sources[0x61]	3313	1			T4	12		T6	8		T8	2
valid_sources[0x62]	3215	1			T4	11		T7	7		T8	3
valid_sources[0x63]	3765	1			T4	14		T6	14		T7	1
valid_sources[0x64]	3870	1			T3	1		T4	13		T7	2
valid_sources[0x65]	4412	1			T3	1		T4	5		T6	12
valid_sources[0x66]	3414	1			T4	9		T6	13		T7	1
valid_sources[0x67]	3855	1			T4	8		T12	39		T20	16
valid_sources[0x68]	3220	1			T4	14		T6	7		T7	3
valid_sources[0x69]	3883	1			T4	10		T7	2		T12	40
valid_sources[0x6a]	4028	1			T3	4		T4	13		T7	1
valid_sources[0x6b]	3466	1			T3	1		T4	14		T6	5
valid_sources[0x6c]	5024	1			T3	3		T4	9		T6	4
valid_sources[0x6d]	3310	1			T4	8		T7	3		T8	1
valid_sources[0x6e]	5806	1			T3	2		T4	9		T7	2
valid_sources[0x6f]	6215	1			T4	14		T7	4		T8	1
valid_sources[0x70]	3465	1			T4	16		T7	3		T12	20
valid_sources[0x71]	3031	1			T3	1		T4	20		T7	2
valid_sources[0x72]	3549	1			T4	10		T8	1		T9	1
valid_sources[0x73]	6644	1			T3	3		T4	10		T7	3
valid_sources[0x74]	3456	1			T4	16		T12	33		T20	25
valid_sources[0x75]	3405	1			T4	14		T6	9		T7	1
valid_sources[0x76]	3649	1			T4	10		T7	5		T8	3
valid_sources[0x77]	3791	1			T4	13		T7	2		T8	1
valid_sources[0x78]	3363	1			T4	17		T6	30		T7	3
valid_sources[0x79]	3806	1			T3	1		T4	14		T8	3
valid_sources[0x7a]	3417	1			T4	4		T7	3		T8	1
valid_sources[0x7b]	3386	1			T4	15		T6	37		T7	2
valid_sources[0x7c]	4177	1			T3	4		T4	21		T7	2
valid_sources[0x7d]	3585	1			T4	14		T6	2		T12	26
valid_sources[0x7e]	3224	1			T4	13		T6	6		T7	1
valid_sources[0x7f]	3069	1			T4	17		T12	30		T20	11
valid_sources[0x80]	2813	1			T4	11		T6	8		T7	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

235495

1

T1

691

T3

49

T4

683

values[0x0]

all_enables

biggest_size

76821

1

T1

313

T3

16

T4

272

values[0x1]

all_enables

biggest_size

41442

1

T1

147

T3

14

T4

130