SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
92.86 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rstmgr_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 956766 | 0 | T1 | 3200 | T2 | 1 | T3 | 212 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 956549 | 1 | T1 | 3200 | T2 | 1 | T3 | 212 | ||||
values[1] | 29 | 1 | T60 | 1 | T89 | 2 | T82 | 1 | ||||
values[2] | 3 | 1 | T89 | 1 | T75 | 1 | T123 | 1 | ||||
values[3] | 119 | 1 | T60 | 7 | T88 | 8 | T89 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 956554 | 1 | T1 | 3200 | T2 | 1 | T3 | 212 | ||||
values[1] | 26 | 1 | T60 | 3 | T89 | 2 | T82 | 2 | ||||
values[2] | 7 | 1 | T88 | 1 | T82 | 1 | T76 | 2 | ||||
values[3] | 85 | 1 | T60 | 4 | T88 | 3 | T89 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 956446 | 1 | T1 | 3200 | T2 | 1 | T3 | 212 | ||||
auto[TlIntgErrCmd] | 108 | 1 | T60 | 6 | T88 | 5 | T89 | 9 | ||||
auto[TlIntgErrData] | 103 | 1 | T60 | 8 | T88 | 2 | T89 | 5 | ||||
auto[TlIntgErrBoth] | 109 | 1 | T60 | 6 | T88 | 3 | T89 | 6 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |