SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_aon |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_daon_lc_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_d0_lc_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_daon_lc_io_div4_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_d0_lc_io_div4_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_sys |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_sys_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_device |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_host0 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_host1 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | u_d0_usb_aon |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c0 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c1 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 16665 | 16665 | 0 | 0 |
OutputsKnown_A | 371949998 | 214401383 | 0 | 0 |
gen_no_flops.OutputDelay_A | 371949998 | 214401383 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 16665 | 16665 | 0 | 0 |
T1 | 33 | 33 | 0 | 0 |
T2 | 33 | 33 | 0 | 0 |
T3 | 33 | 33 | 0 | 0 |
T4 | 33 | 33 | 0 | 0 |
T5 | 33 | 33 | 0 | 0 |
T6 | 33 | 33 | 0 | 0 |
T7 | 33 | 33 | 0 | 0 |
T8 | 33 | 33 | 0 | 0 |
T9 | 33 | 33 | 0 | 0 |
T10 | 33 | 33 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 371949998 | 214401383 | 0 | 0 |
T1 | 864856 | 287502 | 0 | 0 |
T2 | 99138 | 30050 | 0 | 0 |
T3 | 119024 | 85839 | 0 | 0 |
T4 | 1778940 | 1193732 | 0 | 0 |
T5 | 117289 | 19636 | 0 | 0 |
T6 | 440403 | 419086 | 0 | 0 |
T7 | 151429 | 118569 | 0 | 0 |
T8 | 143482 | 110011 | 0 | 0 |
T9 | 79274 | 47322 | 0 | 0 |
T10 | 12743331 | 1311424 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 371949998 | 214401383 | 0 | 0 |
T1 | 864856 | 287502 | 0 | 0 |
T2 | 99138 | 30050 | 0 | 0 |
T3 | 119024 | 85839 | 0 | 0 |
T4 | 1778940 | 1193732 | 0 | 0 |
T5 | 117289 | 19636 | 0 | 0 |
T6 | 440403 | 419086 | 0 | 0 |
T7 | 151429 | 118569 | 0 | 0 |
T8 | 143482 | 110011 | 0 | 0 |
T9 | 79274 | 47322 | 0 | 0 |
T10 | 12743331 | 1311424 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12593550 | 7536135 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12593550 | 7536135 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12593550 | 7536135 | 0 | 0 |
T1 | 29176 | 11822 | 0 | 0 |
T2 | 3138 | 962 | 0 | 0 |
T3 | 3792 | 2799 | 0 | 0 |
T4 | 56572 | 39204 | 0 | 0 |
T5 | 3689 | 756 | 0 | 0 |
T6 | 13363 | 12718 | 0 | 0 |
T7 | 4773 | 3785 | 0 | 0 |
T8 | 4538 | 3579 | 0 | 0 |
T9 | 2730 | 1722 | 0 | 0 |
T10 | 396867 | 49184 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12593550 | 7536135 | 0 | 0 |
T1 | 29176 | 11822 | 0 | 0 |
T2 | 3138 | 962 | 0 | 0 |
T3 | 3792 | 2799 | 0 | 0 |
T4 | 56572 | 39204 | 0 | 0 |
T5 | 3689 | 756 | 0 | 0 |
T6 | 13363 | 12718 | 0 | 0 |
T7 | 4773 | 3785 | 0 | 0 |
T8 | 4538 | 3579 | 0 | 0 |
T9 | 2730 | 1722 | 0 | 0 |
T10 | 396867 | 49184 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 11229889 | 6464539 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11229889 | 6464539 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11229889 | 6464539 | 0 | 0 |
T1 | 26115 | 8615 | 0 | 0 |
T2 | 3000 | 909 | 0 | 0 |
T3 | 3601 | 2595 | 0 | 0 |
T4 | 53824 | 36079 | 0 | 0 |
T5 | 3550 | 590 | 0 | 0 |
T6 | 13345 | 12699 | 0 | 0 |
T7 | 4583 | 3587 | 0 | 0 |
T8 | 4342 | 3326 | 0 | 0 |
T9 | 2392 | 1425 | 0 | 0 |
T10 | 385827 | 39445 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |