Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T39
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T39
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T39
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T39
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12593550	13494	0	0
gen_assertions[0].RstEnOn_A	12593550	1050	0	0
gen_assertions[0].RstNOff_A	12593550	13494	0	0
gen_assertions[0].RstNOn_A	12593550	1050	0	0
gen_assertions[1].RstEnOff_A	50374123	12248	0	0
gen_assertions[1].RstEnOn_A	50374123	985	0	0
gen_assertions[1].RstNOff_A	50374123	12248	0	0
gen_assertions[1].RstNOn_A	50374123	985	0	0
gen_assertions[2].RstEnOff_A	25187975	12293	0	0
gen_assertions[2].RstEnOn_A	25187975	993	0	0
gen_assertions[2].RstNOff_A	25187975	12293	0	0
gen_assertions[2].RstNOn_A	25187975	993	0	0
gen_assertions[3].RstEnOff_A	25187702	12303	0	0
gen_assertions[3].RstEnOn_A	25187702	1000	0	0
gen_assertions[3].RstNOff_A	25187702	12303	0	0
gen_assertions[3].RstNOn_A	25187702	1000	0	0
gen_assertions[4].RstEnOff_A	1589507	20954	0	0
gen_assertions[4].RstEnOn_A	1589507	1040	0	0
gen_assertions[4].RstNOff_A	1589507	20954	0	0
gen_assertions[4].RstNOn_A	1589507	1040	0	0
gen_assertions[5].RstEnOff_A	12593550	13723	0	0
gen_assertions[5].RstEnOn_A	12593550	1138	0	0
gen_assertions[5].RstNOff_A	12593550	13723	0	0
gen_assertions[5].RstNOn_A	12593550	1138	0	0
gen_assertions[6].RstEnOff_A	12593550	13754	0	0
gen_assertions[6].RstEnOn_A	12593550	1161	0	0
gen_assertions[6].RstNOff_A	12593550	13754	0	0
gen_assertions[6].RstNOn_A	12593550	1161	0	0
gen_assertions[7].RstEnOff_A	12593550	13786	0	0
gen_assertions[7].RstEnOn_A	12593550	1193	0	0
gen_assertions[7].RstNOff_A	12593550	13786	0	0
gen_assertions[7].RstNOn_A	12593550	1193	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593550	13494	0	0
T1	29176	75	0	0
T2	3138	0	0	0
T3	3792	4	0	0
T4	56572	75	0	0
T5	3689	0	0	0
T6	13363	6	0	0
T7	4773	5	0	0
T8	4538	5	0	0
T9	2730	4	0	0
T10	396867	0	0	0
T12	0	82	0	0
T20	0	75	0	0
T21	0	39	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593550	1050	0	0
T6	13363	6	0	0
T7	4773	1	0	0
T8	4538	1	0	0
T9	2730	0	0	0
T10	396867	0	0	0
T11	2442	0	0	0
T12	90359	8	0	0
T20	52106	0	0	0
T21	22571	0	0	0
T23	5831	0	0	0
T39	0	5	0	0
T40	0	4	0	0
T62	0	2	0	0
T63	0	4	0	0
T64	0	1	0	0
T65	0	4	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593550	13494	0	0
T1	29176	75	0	0
T2	3138	0	0	0
T3	3792	4	0	0
T4	56572	75	0	0
T5	3689	0	0	0
T6	13363	6	0	0
T7	4773	5	0	0
T8	4538	5	0	0
T9	2730	4	0	0
T10	396867	0	0	0
T12	0	82	0	0
T20	0	75	0	0
T21	0	39	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593550	1050	0	0
T6	13363	6	0	0
T7	4773	1	0	0
T8	4538	1	0	0
T9	2730	0	0	0
T10	396867	0	0	0
T11	2442	0	0	0
T12	90359	8	0	0
T20	52106	0	0	0
T21	22571	0	0	0
T23	5831	0	0	0
T39	0	5	0	0
T40	0	4	0	0
T62	0	2	0	0
T63	0	4	0	0
T64	0	1	0	0
T65	0	4	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50374123	12248	0	0
T1	116682	72	0	0
T2	12557	0	0	0
T3	15180	4	0	0
T4	226269	66	0	0
T5	14758	0	0	0
T6	53455	10	0	0
T7	19097	4	0	0
T8	18148	4	0	0
T9	10923	4	0	0
T10	158733	0	0	0
T12	0	69	0	0
T20	0	66	0	0
T21	0	37	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50374123	985	0	0
T6	53455	10	0	0
T7	19097	0	0	0
T8	18148	0	0	0
T9	10923	0	0	0
T10	158733	0	0	0
T11	9772	0	0	0
T12	361432	6	0	0
T20	208441	0	0	0
T21	90285	0	0	0
T23	23318	0	0	0
T39	0	7	0	0
T40	0	4	0	0
T63	0	4	0	0
T64	0	1	0	0
T65	0	6	0	0
T66	0	7	0	0
T67	0	3	0	0
T68	0	6	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50374123	12248	0	0
T1	116682	72	0	0
T2	12557	0	0	0
T3	15180	4	0	0
T4	226269	66	0	0
T5	14758	0	0	0
T6	53455	10	0	0
T7	19097	4	0	0
T8	18148	4	0	0
T9	10923	4	0	0
T10	158733	0	0	0
T12	0	69	0	0
T20	0	66	0	0
T21	0	37	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50374123	985	0	0
T6	53455	10	0	0
T7	19097	0	0	0
T8	18148	0	0	0
T9	10923	0	0	0
T10	158733	0	0	0
T11	9772	0	0	0
T12	361432	6	0	0
T20	208441	0	0	0
T21	90285	0	0	0
T23	23318	0	0	0
T39	0	7	0	0
T40	0	4	0	0
T63	0	4	0	0
T64	0	1	0	0
T65	0	6	0	0
T66	0	7	0	0
T67	0	3	0	0
T68	0	6	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25187975	12293	0	0
T1	58371	72	0	0
T2	6277	0	0	0
T3	7590	4	0	0
T4	113158	66	0	0
T5	7380	0	0	0
T6	26728	12	0	0
T7	9548	4	0	0
T8	9078	4	0	0
T9	5461	4	0	0
T10	793672	0	0	0
T12	0	66	0	0
T20	0	66	0	0
T21	0	37	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25187975	993	0	0
T6	26728	12	0	0
T7	9548	0	0	0
T8	9078	0	0	0
T9	5461	0	0	0
T10	793672	0	0	0
T11	4886	0	0	0
T12	180737	4	0	0
T20	104227	0	0	0
T21	45137	0	0	0
T23	11665	0	0	0
T39	0	9	0	0
T40	0	7	0	0
T63	0	3	0	0
T65	0	8	0	0
T66	0	7	0	0
T67	0	1	0	0
T68	0	5	0	0
T69	0	17	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25187975	12293	0	0
T1	58371	72	0	0
T2	6277	0	0	0
T3	7590	4	0	0
T4	113158	66	0	0
T5	7380	0	0	0
T6	26728	12	0	0
T7	9548	4	0	0
T8	9078	4	0	0
T9	5461	4	0	0
T10	793672	0	0	0
T12	0	66	0	0
T20	0	66	0	0
T21	0	37	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25187975	993	0	0
T6	26728	12	0	0
T7	9548	0	0	0
T8	9078	0	0	0
T9	5461	0	0	0
T10	793672	0	0	0
T11	4886	0	0	0
T12	180737	4	0	0
T20	104227	0	0	0
T21	45137	0	0	0
T23	11665	0	0	0
T39	0	9	0	0
T40	0	7	0	0
T63	0	3	0	0
T65	0	8	0	0
T66	0	7	0	0
T67	0	1	0	0
T68	0	5	0	0
T69	0	17	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25187702	12303	0	0
T1	58339	72	0	0
T2	6278	0	0	0
T3	7586	4	0	0
T4	113166	66	0	0
T5	7379	0	0	0
T6	26728	11	0	0
T7	9550	5	0	0
T8	9075	4	0	0
T9	5461	4	0	0
T10	793692	0	0	0
T12	0	68	0	0
T20	0	66	0	0
T21	0	37	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25187702	1000	0	0
T6	26728	11	0	0
T7	9550	1	0	0
T8	9075	0	0	0
T9	5461	0	0	0
T10	793692	0	0	0
T11	4887	0	0	0
T12	180721	6	0	0
T20	104220	0	0	0
T21	45148	0	0	0
T23	11665	0	0	0
T39	0	7	0	0
T40	0	8	0	0
T63	0	4	0	0
T65	0	8	0	0
T66	0	8	0	0
T68	0	4	0	0
T70	0	1	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25187702	12303	0	0
T1	58339	72	0	0
T2	6278	0	0	0
T3	7586	4	0	0
T4	113166	66	0	0
T5	7379	0	0	0
T6	26728	11	0	0
T7	9550	5	0	0
T8	9075	4	0	0
T9	5461	4	0	0
T10	793692	0	0	0
T12	0	68	0	0
T20	0	66	0	0
T21	0	37	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25187702	1000	0	0
T6	26728	11	0	0
T7	9550	1	0	0
T8	9075	0	0	0
T9	5461	0	0	0
T10	793692	0	0	0
T11	4887	0	0	0
T12	180721	6	0	0
T20	104220	0	0	0
T21	45148	0	0	0
T23	11665	0	0	0
T39	0	7	0	0
T40	0	8	0	0
T63	0	4	0	0
T65	0	8	0	0
T66	0	8	0	0
T68	0	4	0	0
T70	0	1	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1589507	20954	0	0
T1	3663	77	0	0
T2	391	2	0	0
T3	472	6	0	0
T4	7086	101	0	0
T5	459	2	0	0
T6	1669	14	0	0
T7	595	6	0	0
T8	566	7	0	0
T9	340	5	0	0
T10	49850	541	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1589507	1040	0	0
T6	1669	13	0	0
T7	595	0	0	0
T8	566	1	0	0
T9	340	0	0	0
T10	49850	0	0	0
T11	303	0	0	0
T12	11438	7	0	0
T20	6527	0	0	0
T21	2879	0	0	0
T23	730	0	0	0
T39	0	10	0	0
T40	0	9	0	0
T63	0	4	0	0
T65	0	10	0	0
T66	0	10	0	0
T68	0	5	0	0
T69	0	20	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1589507	20954	0	0
T1	3663	77	0	0
T2	391	2	0	0
T3	472	6	0	0
T4	7086	101	0	0
T5	459	2	0	0
T6	1669	14	0	0
T7	595	6	0	0
T8	566	7	0	0
T9	340	5	0	0
T10	49850	541	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1589507	1040	0	0
T6	1669	13	0	0
T7	595	0	0	0
T8	566	1	0	0
T9	340	0	0	0
T10	49850	0	0	0
T11	303	0	0	0
T12	11438	7	0	0
T20	6527	0	0	0
T21	2879	0	0	0
T23	730	0	0	0
T39	0	10	0	0
T40	0	9	0	0
T63	0	4	0	0
T65	0	10	0	0
T66	0	10	0	0
T68	0	5	0	0
T69	0	20	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593550	13723	0	0
T1	29176	75	0	0
T2	3138	0	0	0
T3	3792	4	0	0
T4	56572	75	0	0
T5	3689	0	0	0
T6	13363	13	0	0
T7	4773	4	0	0
T8	4538	5	0	0
T9	2730	4	0	0
T10	396867	0	0	0
T12	0	82	0	0
T20	0	75	0	0
T21	0	39	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593550	1138	0	0
T6	13363	13	0	0
T7	4773	0	0	0
T8	4538	1	0	0
T9	2730	0	0	0
T10	396867	0	0	0
T11	2442	0	0	0
T12	90359	8	0	0
T20	52106	0	0	0
T21	22571	0	0	0
T23	5831	0	0	0
T39	0	10	0	0
T40	0	10	0	0
T63	0	4	0	0
T65	0	14	0	0
T66	0	11	0	0
T68	0	2	0	0
T69	0	22	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593550	13723	0	0
T1	29176	75	0	0
T2	3138	0	0	0
T3	3792	4	0	0
T4	56572	75	0	0
T5	3689	0	0	0
T6	13363	13	0	0
T7	4773	4	0	0
T8	4538	5	0	0
T9	2730	4	0	0
T10	396867	0	0	0
T12	0	82	0	0
T20	0	75	0	0
T21	0	39	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593550	1138	0	0
T6	13363	13	0	0
T7	4773	0	0	0
T8	4538	1	0	0
T9	2730	0	0	0
T10	396867	0	0	0
T11	2442	0	0	0
T12	90359	8	0	0
T20	52106	0	0	0
T21	22571	0	0	0
T23	5831	0	0	0
T39	0	10	0	0
T40	0	10	0	0
T63	0	4	0	0
T65	0	14	0	0
T66	0	11	0	0
T68	0	2	0	0
T69	0	22	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593550	13754	0	0
T1	29176	75	0	0
T2	3138	0	0	0
T3	3792	4	0	0
T4	56572	75	0	0
T5	3689	0	0	0
T6	13363	14	0	0
T7	4773	4	0	0
T8	4538	4	0	0
T9	2730	4	0	0
T10	396867	0	0	0
T12	0	81	0	0
T20	0	75	0	0
T21	0	39	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593550	1161	0	0
T6	13363	14	0	0
T7	4773	0	0	0
T8	4538	0	0	0
T9	2730	0	0	0
T10	396867	0	0	0
T11	2442	0	0	0
T12	90359	6	0	0
T20	52106	0	0	0
T21	22571	0	0	0
T23	5831	0	0	0
T39	0	13	0	0
T40	0	12	0	0
T63	0	5	0	0
T65	0	13	0	0
T66	0	13	0	0
T68	0	5	0	0
T69	0	22	0	0
T71	0	6	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593550	13754	0	0
T1	29176	75	0	0
T2	3138	0	0	0
T3	3792	4	0	0
T4	56572	75	0	0
T5	3689	0	0	0
T6	13363	14	0	0
T7	4773	4	0	0
T8	4538	4	0	0
T9	2730	4	0	0
T10	396867	0	0	0
T12	0	81	0	0
T20	0	75	0	0
T21	0	39	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593550	1161	0	0
T6	13363	14	0	0
T7	4773	0	0	0
T8	4538	0	0	0
T9	2730	0	0	0
T10	396867	0	0	0
T11	2442	0	0	0
T12	90359	6	0	0
T20	52106	0	0	0
T21	22571	0	0	0
T23	5831	0	0	0
T39	0	13	0	0
T40	0	12	0	0
T63	0	5	0	0
T65	0	13	0	0
T66	0	13	0	0
T68	0	5	0	0
T69	0	22	0	0
T71	0	6	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593550	13786	0	0
T1	29176	75	0	0
T2	3138	0	0	0
T3	3792	4	0	0
T4	56572	75	0	0
T5	3689	0	0	0
T6	13363	14	0	0
T7	4773	4	0	0
T8	4538	4	0	0
T9	2730	4	0	0
T10	396867	0	0	0
T12	0	79	0	0
T20	0	75	0	0
T21	0	39	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593550	1193	0	0
T6	13363	14	0	0
T7	4773	0	0	0
T8	4538	0	0	0
T9	2730	0	0	0
T10	396867	0	0	0
T11	2442	0	0	0
T12	90359	4	0	0
T20	52106	0	0	0
T21	22571	0	0	0
T23	5831	0	0	0
T39	0	12	0	0
T40	0	10	0	0
T63	0	3	0	0
T65	0	14	0	0
T66	0	13	0	0
T68	0	5	0	0
T69	0	20	0	0
T71	0	8	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593550	13786	0	0
T1	29176	75	0	0
T2	3138	0	0	0
T3	3792	4	0	0
T4	56572	75	0	0
T5	3689	0	0	0
T6	13363	14	0	0
T7	4773	4	0	0
T8	4538	4	0	0
T9	2730	4	0	0
T10	396867	0	0	0
T12	0	79	0	0
T20	0	75	0	0
T21	0	39	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593550	1193	0	0
T6	13363	14	0	0
T7	4773	0	0	0
T8	4538	0	0	0
T9	2730	0	0	0
T10	396867	0	0	0
T11	2442	0	0	0
T12	90359	4	0	0
T20	52106	0	0	0
T21	22571	0	0	0
T23	5831	0	0	0
T39	0	12	0	0
T40	0	10	0	0
T63	0	3	0	0
T65	0	14	0	0
T66	0	13	0	0
T68	0	5	0	0
T69	0	20	0	0
T71	0	8	0	0