SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_aon |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_daon_lc_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_d0_lc_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_daon_lc_io_div4_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_d0_lc_io_div4_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_sys |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_sys_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_device |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_host0 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_host1 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | u_d0_usb_aon |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c0 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c1 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 850142650 | 455139335 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 850142650 | 455139335 | 0 | 0 |
T1 | 1969406 | 649147 | 0 | 0 |
T2 | 211866 | 63167 | 0 | 0 |
T3 | 256128 | 179573 | 0 | 0 |
T4 | 3818858 | 2501726 | 0 | 0 |
T5 | 249038 | 45385 | 0 | 0 |
T6 | 902060 | 832103 | 0 | 0 |
T7 | 322260 | 246244 | 0 | 0 |
T8 | 306284 | 229357 | 0 | 0 |
T9 | 184332 | 101865 | 0 | 0 |
T10 | 12144528 | 3000197 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 52474987 | 31423338 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 52474987 | 31423338 | 0 | 0 |
T1 | 121571 | 49290 | 0 | 0 |
T2 | 13079 | 4013 | 0 | 0 |
T3 | 15816 | 11672 | 0 | 0 |
T4 | 235737 | 163434 | 0 | 0 |
T5 | 15374 | 3157 | 0 | 0 |
T6 | 55685 | 52997 | 0 | 0 |
T7 | 19895 | 15775 | 0 | 0 |
T8 | 18906 | 14912 | 0 | 0 |
T9 | 11382 | 7184 | 0 | 0 |
T10 | 165345 | 207163 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 50374123 | 30164704 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 50374123 | 30164704 | 0 | 0 |
T1 | 116682 | 47333 | 0 | 0 |
T2 | 12557 | 3852 | 0 | 0 |
T3 | 15180 | 11202 | 0 | 0 |
T4 | 226269 | 156926 | 0 | 0 |
T5 | 14758 | 3031 | 0 | 0 |
T6 | 53455 | 50875 | 0 | 0 |
T7 | 19097 | 15141 | 0 | 0 |
T8 | 18148 | 14314 | 0 | 0 |
T9 | 10923 | 6893 | 0 | 0 |
T10 | 158733 | 198836 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 25187975 | 15079003 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 25187975 | 15079003 | 0 | 0 |
T1 | 58371 | 23658 | 0 | 0 |
T2 | 6277 | 1925 | 0 | 0 |
T3 | 7590 | 5602 | 0 | 0 |
T4 | 113158 | 78431 | 0 | 0 |
T5 | 7380 | 1515 | 0 | 0 |
T6 | 26728 | 25438 | 0 | 0 |
T7 | 9548 | 7570 | 0 | 0 |
T8 | 9078 | 7161 | 0 | 0 |
T9 | 5461 | 3446 | 0 | 0 |
T10 | 793672 | 99153 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 12593550 | 7536135 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12593550 | 7536135 | 0 | 0 |
T1 | 29176 | 11822 | 0 | 0 |
T2 | 3138 | 962 | 0 | 0 |
T3 | 3792 | 2799 | 0 | 0 |
T4 | 56572 | 39204 | 0 | 0 |
T5 | 3689 | 756 | 0 | 0 |
T6 | 13363 | 12718 | 0 | 0 |
T7 | 4773 | 3785 | 0 | 0 |
T8 | 4538 | 3579 | 0 | 0 |
T9 | 2730 | 1722 | 0 | 0 |
T10 | 396867 | 49184 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 25187702 | 15078632 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 25187702 | 15078632 | 0 | 0 |
T1 | 58339 | 23652 | 0 | 0 |
T2 | 6278 | 1925 | 0 | 0 |
T3 | 7586 | 5599 | 0 | 0 |
T4 | 113166 | 78471 | 0 | 0 |
T5 | 7379 | 1515 | 0 | 0 |
T6 | 26728 | 25438 | 0 | 0 |
T7 | 9550 | 7571 | 0 | 0 |
T8 | 9075 | 7158 | 0 | 0 |
T9 | 5461 | 3445 | 0 | 0 |
T10 | 793692 | 99153 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 52474987 | 27903768 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 52474987 | 27903768 | 0 | 0 |
T1 | 121571 | 39681 | 0 | 0 |
T2 | 13079 | 4002 | 0 | 0 |
T3 | 15816 | 11070 | 0 | 0 |
T4 | 235737 | 154071 | 0 | 0 |
T5 | 15374 | 3144 | 0 | 0 |
T6 | 55685 | 52990 | 0 | 0 |
T7 | 19895 | 15205 | 0 | 0 |
T8 | 18906 | 14109 | 0 | 0 |
T9 | 11382 | 6194 | 0 | 0 |
T10 | 165345 | 203780 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 52474987 | 27198335 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 52474987 | 27198335 | 0 | 0 |
T1 | 121571 | 37187 | 0 | 0 |
T2 | 13079 | 3802 | 0 | 0 |
T3 | 15816 | 10903 | 0 | 0 |
T4 | 235737 | 151634 | 0 | 0 |
T5 | 15374 | 2477 | 0 | 0 |
T6 | 55685 | 52924 | 0 | 0 |
T7 | 19895 | 15037 | 0 | 0 |
T8 | 18906 | 13942 | 0 | 0 |
T9 | 11382 | 6029 | 0 | 0 |
T10 | 165345 | 167703 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 52474987 | 27903624 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 52474987 | 27903624 | 0 | 0 |
T1 | 121571 | 39640 | 0 | 0 |
T2 | 13079 | 4002 | 0 | 0 |
T3 | 15816 | 11070 | 0 | 0 |
T4 | 235737 | 154133 | 0 | 0 |
T5 | 15374 | 3144 | 0 | 0 |
T6 | 55685 | 52990 | 0 | 0 |
T7 | 19895 | 15205 | 0 | 0 |
T8 | 18906 | 14109 | 0 | 0 |
T9 | 11382 | 6194 | 0 | 0 |
T10 | 165345 | 203780 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 52474987 | 27199696 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 52474987 | 27199696 | 0 | 0 |
T1 | 121571 | 37258 | 0 | 0 |
T2 | 13079 | 3802 | 0 | 0 |
T3 | 15816 | 10903 | 0 | 0 |
T4 | 235737 | 151709 | 0 | 0 |
T5 | 15374 | 2477 | 0 | 0 |
T6 | 55685 | 52924 | 0 | 0 |
T7 | 19895 | 15037 | 0 | 0 |
T8 | 18906 | 13942 | 0 | 0 |
T9 | 11382 | 6029 | 0 | 0 |
T10 | 165345 | 167703 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 1589507 | 827174 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1589507 | 827174 | 0 | 0 |
T1 | 3663 | 1082 | 0 | 0 |
T2 | 391 | 118 | 0 | 0 |
T3 | 472 | 324 | 0 | 0 |
T4 | 7086 | 4520 | 0 | 0 |
T5 | 459 | 92 | 0 | 0 |
T6 | 1669 | 1588 | 0 | 0 |
T7 | 595 | 449 | 0 | 0 |
T8 | 566 | 418 | 0 | 0 |
T9 | 340 | 180 | 0 | 0 |
T10 | 49850 | 5404 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 50374123 | 26787720 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 50374123 | 26787720 | 0 | 0 |
T1 | 116682 | 38082 | 0 | 0 |
T2 | 12557 | 3842 | 0 | 0 |
T3 | 15180 | 10624 | 0 | 0 |
T4 | 226269 | 147874 | 0 | 0 |
T5 | 14758 | 3018 | 0 | 0 |
T6 | 53455 | 50868 | 0 | 0 |
T7 | 19097 | 14593 | 0 | 0 |
T8 | 18148 | 13542 | 0 | 0 |
T9 | 10923 | 5944 | 0 | 0 |
T10 | 158733 | 195589 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 50374123 | 26108454 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 50374123 | 26108454 | 0 | 0 |
T1 | 116682 | 35755 | 0 | 0 |
T2 | 12557 | 3650 | 0 | 0 |
T3 | 15180 | 10464 | 0 | 0 |
T4 | 226269 | 145614 | 0 | 0 |
T5 | 14758 | 2378 | 0 | 0 |
T6 | 53455 | 50804 | 0 | 0 |
T7 | 19097 | 14433 | 0 | 0 |
T8 | 18148 | 13382 | 0 | 0 |
T9 | 10923 | 5784 | 0 | 0 |
T10 | 158733 | 160966 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 25187975 | 13384163 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 25187975 | 13384163 | 0 | 0 |
T1 | 58371 | 19004 | 0 | 0 |
T2 | 6277 | 1920 | 0 | 0 |
T3 | 7590 | 5310 | 0 | 0 |
T4 | 113158 | 73895 | 0 | 0 |
T5 | 7380 | 1509 | 0 | 0 |
T6 | 26728 | 25435 | 0 | 0 |
T7 | 9548 | 7294 | 0 | 0 |
T8 | 9078 | 6773 | 0 | 0 |
T9 | 5461 | 2970 | 0 | 0 |
T10 | 793672 | 97528 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 25187975 | 13044312 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 25187975 | 13044312 | 0 | 0 |
T1 | 58371 | 17840 | 0 | 0 |
T2 | 6277 | 1824 | 0 | 0 |
T3 | 7590 | 5230 | 0 | 0 |
T4 | 113158 | 72739 | 0 | 0 |
T5 | 7380 | 1189 | 0 | 0 |
T6 | 26728 | 25403 | 0 | 0 |
T7 | 9548 | 7214 | 0 | 0 |
T8 | 9078 | 6693 | 0 | 0 |
T9 | 5461 | 2890 | 0 | 0 |
T10 | 793672 | 80216 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 12593550 | 6665126 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12593550 | 6665126 | 0 | 0 |
T1 | 29176 | 9352 | 0 | 0 |
T2 | 3138 | 958 | 0 | 0 |
T3 | 3792 | 2646 | 0 | 0 |
T4 | 56572 | 36817 | 0 | 0 |
T5 | 3689 | 752 | 0 | 0 |
T6 | 13363 | 12716 | 0 | 0 |
T7 | 4773 | 3639 | 0 | 0 |
T8 | 4538 | 3378 | 0 | 0 |
T9 | 2730 | 1477 | 0 | 0 |
T10 | 396867 | 48102 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 12593550 | 6495329 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12593550 | 6495329 | 0 | 0 |
T1 | 29176 | 8770 | 0 | 0 |
T2 | 3138 | 910 | 0 | 0 |
T3 | 3792 | 2606 | 0 | 0 |
T4 | 56572 | 36235 | 0 | 0 |
T5 | 3689 | 592 | 0 | 0 |
T6 | 13363 | 12700 | 0 | 0 |
T7 | 4773 | 3599 | 0 | 0 |
T8 | 4538 | 3338 | 0 | 0 |
T9 | 2730 | 1437 | 0 | 0 |
T10 | 396867 | 39446 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 12593550 | 6665126 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12593550 | 6665126 | 0 | 0 |
T1 | 29176 | 9352 | 0 | 0 |
T2 | 3138 | 958 | 0 | 0 |
T3 | 3792 | 2646 | 0 | 0 |
T4 | 56572 | 36817 | 0 | 0 |
T5 | 3689 | 752 | 0 | 0 |
T6 | 13363 | 12716 | 0 | 0 |
T7 | 4773 | 3639 | 0 | 0 |
T8 | 4538 | 3378 | 0 | 0 |
T9 | 2730 | 1477 | 0 | 0 |
T10 | 396867 | 48102 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 12593550 | 6495329 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12593550 | 6495329 | 0 | 0 |
T1 | 29176 | 8770 | 0 | 0 |
T2 | 3138 | 910 | 0 | 0 |
T3 | 3792 | 2606 | 0 | 0 |
T4 | 56572 | 36235 | 0 | 0 |
T5 | 3689 | 592 | 0 | 0 |
T6 | 13363 | 12700 | 0 | 0 |
T7 | 4773 | 3599 | 0 | 0 |
T8 | 4538 | 3338 | 0 | 0 |
T9 | 2730 | 1437 | 0 | 0 |
T10 | 396867 | 39446 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 25187702 | 13384058 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 25187702 | 13384058 | 0 | 0 |
T1 | 58339 | 18958 | 0 | 0 |
T2 | 6278 | 1920 | 0 | 0 |
T3 | 7586 | 5307 | 0 | 0 |
T4 | 113166 | 73912 | 0 | 0 |
T5 | 7379 | 1509 | 0 | 0 |
T6 | 26728 | 25435 | 0 | 0 |
T7 | 9550 | 7295 | 0 | 0 |
T8 | 9075 | 6770 | 0 | 0 |
T9 | 5461 | 2969 | 0 | 0 |
T10 | 793692 | 97528 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 25187702 | 13044397 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 25187702 | 13044397 | 0 | 0 |
T1 | 58339 | 17828 | 0 | 0 |
T2 | 6278 | 1824 | 0 | 0 |
T3 | 7586 | 5227 | 0 | 0 |
T4 | 113166 | 72750 | 0 | 0 |
T5 | 7379 | 1189 | 0 | 0 |
T6 | 26728 | 25403 | 0 | 0 |
T7 | 9550 | 7215 | 0 | 0 |
T8 | 9075 | 6690 | 0 | 0 |
T9 | 5461 | 2889 | 0 | 0 |
T10 | 793692 | 80216 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 52474987 | 26908282 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 52474987 | 26908282 | 0 | 0 |
T1 | 121571 | 35501 | 0 | 0 |
T2 | 13079 | 3802 | 0 | 0 |
T3 | 15816 | 10783 | 0 | 0 |
T4 | 235737 | 149751 | 0 | 0 |
T5 | 15374 | 2477 | 0 | 0 |
T6 | 55685 | 52924 | 0 | 0 |
T7 | 19895 | 14941 | 0 | 0 |
T8 | 18906 | 13830 | 0 | 0 |
T9 | 11382 | 5911 | 0 | 0 |
T10 | 165345 | 167703 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 12593550 | 6595617 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12593550 | 6595617 | 0 | 0 |
T1 | 29176 | 8931 | 0 | 0 |
T2 | 3138 | 958 | 0 | 0 |
T3 | 3792 | 2617 | 0 | 0 |
T4 | 56572 | 36348 | 0 | 0 |
T5 | 3689 | 752 | 0 | 0 |
T6 | 13363 | 12716 | 0 | 0 |
T7 | 4773 | 3616 | 0 | 0 |
T8 | 4538 | 3351 | 0 | 0 |
T9 | 2730 | 1449 | 0 | 0 |
T10 | 396867 | 48102 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 12593550 | 6351164 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12593550 | 6351164 | 0 | 0 |
T1 | 29176 | 8770 | 0 | 0 |
T2 | 3138 | 910 | 0 | 0 |
T3 | 3792 | 2606 | 0 | 0 |
T4 | 56572 | 36223 | 0 | 0 |
T5 | 3689 | 592 | 0 | 0 |
T6 | 13363 | 11369 | 0 | 0 |
T7 | 4773 | 3504 | 0 | 0 |
T8 | 4538 | 3243 | 0 | 0 |
T9 | 2730 | 1437 | 0 | 0 |
T10 | 396867 | 39446 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 50374123 | 25562598 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 50374123 | 25562598 | 0 | 0 |
T1 | 116682 | 35755 | 0 | 0 |
T2 | 12557 | 3650 | 0 | 0 |
T3 | 15180 | 10464 | 0 | 0 |
T4 | 226269 | 145554 | 0 | 0 |
T5 | 14758 | 2378 | 0 | 0 |
T6 | 53455 | 41443 | 0 | 0 |
T7 | 19097 | 14433 | 0 | 0 |
T8 | 18148 | 13382 | 0 | 0 |
T9 | 10923 | 5784 | 0 | 0 |
T10 | 158733 | 160966 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 25187975 | 12762035 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 25187975 | 12762035 | 0 | 0 |
T1 | 58371 | 17818 | 0 | 0 |
T2 | 6277 | 1824 | 0 | 0 |
T3 | 7590 | 5230 | 0 | 0 |
T4 | 113158 | 72743 | 0 | 0 |
T5 | 7380 | 1189 | 0 | 0 |
T6 | 26728 | 20425 | 0 | 0 |
T7 | 9548 | 7214 | 0 | 0 |
T8 | 9078 | 6693 | 0 | 0 |
T9 | 5461 | 2890 | 0 | 0 |
T10 | 793672 | 80216 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 25187702 | 12781502 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 25187702 | 12781502 | 0 | 0 |
T1 | 58339 | 17828 | 0 | 0 |
T2 | 6278 | 1824 | 0 | 0 |
T3 | 7586 | 5227 | 0 | 0 |
T4 | 113166 | 72776 | 0 | 0 |
T5 | 7379 | 1189 | 0 | 0 |
T6 | 26728 | 21615 | 0 | 0 |
T7 | 9550 | 7056 | 0 | 0 |
T8 | 9075 | 6690 | 0 | 0 |
T9 | 5461 | 2889 | 0 | 0 |
T10 | 793692 | 80216 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 1589507 | 789705 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1589507 | 789705 | 0 | 0 |
T1 | 3663 | 1011 | 0 | 0 |
T2 | 391 | 112 | 0 | 0 |
T3 | 472 | 320 | 0 | 0 |
T4 | 7086 | 4442 | 0 | 0 |
T5 | 459 | 72 | 0 | 0 |
T6 | 1669 | 1310 | 0 | 0 |
T7 | 595 | 444 | 0 | 0 |
T8 | 566 | 405 | 0 | 0 |
T9 | 340 | 174 | 0 | 0 |
T10 | 49850 | 4322 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 12593550 | 6358542 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12593550 | 6358542 | 0 | 0 |
T1 | 29176 | 8758 | 0 | 0 |
T2 | 3138 | 910 | 0 | 0 |
T3 | 3792 | 2606 | 0 | 0 |
T4 | 56572 | 36221 | 0 | 0 |
T5 | 3689 | 592 | 0 | 0 |
T6 | 13363 | 10555 | 0 | 0 |
T7 | 4773 | 3599 | 0 | 0 |
T8 | 4538 | 3267 | 0 | 0 |
T9 | 2730 | 1437 | 0 | 0 |
T10 | 396867 | 39446 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 12593550 | 6368134 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12593550 | 6368134 | 0 | 0 |
T1 | 29176 | 8760 | 0 | 0 |
T2 | 3138 | 910 | 0 | 0 |
T3 | 3792 | 2606 | 0 | 0 |
T4 | 56572 | 36220 | 0 | 0 |
T5 | 3689 | 592 | 0 | 0 |
T6 | 13363 | 10716 | 0 | 0 |
T7 | 4773 | 3599 | 0 | 0 |
T8 | 4538 | 3338 | 0 | 0 |
T9 | 2730 | 1437 | 0 | 0 |
T10 | 396867 | 39446 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 12593550 | 6370324 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12593550 | 6370324 | 0 | 0 |
T1 | 29176 | 8757 | 0 | 0 |
T2 | 3138 | 910 | 0 | 0 |
T3 | 3792 | 2606 | 0 | 0 |
T4 | 56572 | 36235 | 0 | 0 |
T5 | 3689 | 592 | 0 | 0 |
T6 | 13363 | 10790 | 0 | 0 |
T7 | 4773 | 3599 | 0 | 0 |
T8 | 4538 | 3338 | 0 | 0 |
T9 | 2730 | 1437 | 0 | 0 |
T10 | 396867 | 39446 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 1589507 | 960540 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1589507 | 960540 | 0 | 0 |
T1 | 3663 | 1499 | 0 | 0 |
T2 | 391 | 122 | 0 | 0 |
T3 | 472 | 351 | 0 | 0 |
T4 | 7086 | 4923 | 0 | 0 |
T5 | 459 | 96 | 0 | 0 |
T6 | 1669 | 1590 | 0 | 0 |
T7 | 595 | 474 | 0 | 0 |
T8 | 566 | 449 | 0 | 0 |
T9 | 340 | 217 | 0 | 0 |
T10 | 49850 | 6486 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 1589507 | 942469 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1589507 | 942469 | 0 | 0 |
T1 | 3663 | 1445 | 0 | 0 |
T2 | 391 | 116 | 0 | 0 |
T3 | 472 | 347 | 0 | 0 |
T4 | 7086 | 4869 | 0 | 0 |
T5 | 459 | 76 | 0 | 0 |
T6 | 1669 | 1588 | 0 | 0 |
T7 | 595 | 470 | 0 | 0 |
T8 | 566 | 445 | 0 | 0 |
T9 | 340 | 213 | 0 | 0 |
T10 | 49850 | 5404 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |