Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12008071	8236	0	0
alert_regwen_rd_A	12008071	3391	0	0
cpu_regwen_rd_A	12008071	3160	0	0
sw_rst_ctrl_n_0_rd_A	12008071	7993	0	0
sw_rst_ctrl_n_1_rd_A	12008071	8100	0	0
sw_rst_ctrl_n_2_rd_A	12008071	8181	0	0
sw_rst_ctrl_n_3_rd_A	12008071	8077	0	0
sw_rst_ctrl_n_4_rd_A	12008071	7919	0	0
sw_rst_ctrl_n_5_rd_A	12008071	8219	0	0
sw_rst_ctrl_n_6_rd_A	12008071	7702	0	0
sw_rst_ctrl_n_7_rd_A	12008071	7936	0	0
sw_rst_regwen_0_rd_A	12008071	3810	0	0
sw_rst_regwen_1_rd_A	12008071	3709	0	0
sw_rst_regwen_2_rd_A	12008071	3800	0	0
sw_rst_regwen_3_rd_A	12008071	3959	0	0
sw_rst_regwen_4_rd_A	12008071	3969	0	0
sw_rst_regwen_5_rd_A	12008071	3832	0	0
sw_rst_regwen_6_rd_A	12008071	3792	0	0
sw_rst_regwen_7_rd_A	12008071	3896	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12008071	8236	0	0
T41	4159	14	0	0
T43	3944	132	0	0
T45	3437	548	0	0
T46	9950	591	0	0
T52	3692	3	0	0
T60	20473	2	0	0
T74	0	254	0	0
T85	1663	0	0	0
T86	1977	0	0	0
T87	2778	0	0	0
T88	0	2	0	0
T89	0	4	0	0
T119	3866	42	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12008071	3391	0	0
T24	53167	0	0	0
T40	3512	0	0	0
T41	0	15	0	0
T42	0	19	0	0
T56	31519	49	0	0
T57	27671	0	0	0
T58	5699	0	0	0
T59	41703	76	0	0
T61	5084	0	0	0
T62	3207	0	0	0
T63	64309	0	0	0
T71	0	169	0	0
T91	0	53	0	0
T93	0	59	0	0
T94	0	73	0	0
T101	0	40	0	0
T120	0	41	0	0
T121	5476	0	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12008071	3160	0	0
T24	53167	0	0	0
T40	3512	0	0	0
T41	0	16	0	0
T42	0	60	0	0
T56	31519	57	0	0
T57	27671	0	0	0
T58	5699	0	0	0
T59	41703	66	0	0
T61	5084	0	0	0
T62	3207	0	0	0
T63	64309	0	0	0
T71	0	166	0	0
T91	0	32	0	0
T93	0	39	0	0
T94	0	80	0	0
T101	0	43	0	0
T120	0	43	0	0
T121	5476	0	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12008071	7993	0	0
T6	13345	203	0	0
T7	4583	0	0	0
T8	4342	0	0	0
T9	2392	0	0	0
T10	385827	0	0	0
T11	2256	0	0	0
T12	79192	0	0	0
T20	48679	0	0	0
T21	17051	0	0	0
T23	5285	0	0	0
T56	0	54	0	0
T59	0	74	0	0
T65	0	116	0	0
T70	0	18	0	0
T71	0	204	0	0
T91	0	45	0	0
T93	0	53	0	0
T94	0	79	0	0
T120	0	56	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12008071	8100	0	0
T6	13345	200	0	0
T7	4583	0	0	0
T8	4342	0	0	0
T9	2392	0	0	0
T10	385827	0	0	0
T11	2256	0	0	0
T12	79192	0	0	0
T20	48679	0	0	0
T21	17051	0	0	0
T23	5285	0	0	0
T56	0	50	0	0
T59	0	66	0	0
T65	0	71	0	0
T70	0	16	0	0
T71	0	246	0	0
T91	0	39	0	0
T93	0	65	0	0
T94	0	75	0	0
T120	0	56	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12008071	8181	0	0
T6	13345	226	0	0
T7	4583	0	0	0
T8	4342	0	0	0
T9	2392	0	0	0
T10	385827	0	0	0
T11	2256	0	0	0
T12	79192	0	0	0
T20	48679	0	0	0
T21	17051	0	0	0
T23	5285	0	0	0
T56	0	57	0	0
T59	0	46	0	0
T65	0	145	0	0
T70	0	13	0	0
T71	0	249	0	0
T91	0	54	0	0
T93	0	46	0	0
T94	0	69	0	0
T120	0	75	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12008071	8077	0	0
T6	13345	198	0	0
T7	4583	0	0	0
T8	4342	0	0	0
T9	2392	0	0	0
T10	385827	0	0	0
T11	2256	0	0	0
T12	79192	0	0	0
T20	48679	0	0	0
T21	17051	0	0	0
T23	5285	0	0	0
T56	0	57	0	0
T59	0	79	0	0
T65	0	83	0	0
T70	0	16	0	0
T71	0	232	0	0
T91	0	31	0	0
T93	0	68	0	0
T94	0	64	0	0
T120	0	68	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12008071	7919	0	0
T6	13345	208	0	0
T7	4583	0	0	0
T8	4342	0	0	0
T9	2392	0	0	0
T10	385827	0	0	0
T11	2256	0	0	0
T12	79192	0	0	0
T20	48679	0	0	0
T21	17051	0	0	0
T23	5285	0	0	0
T56	0	64	0	0
T59	0	71	0	0
T65	0	120	0	0
T70	0	14	0	0
T71	0	214	0	0
T91	0	38	0	0
T93	0	64	0	0
T94	0	44	0	0
T120	0	40	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12008071	8219	0	0
T6	13345	218	0	0
T7	4583	0	0	0
T8	4342	0	0	0
T9	2392	0	0	0
T10	385827	0	0	0
T11	2256	0	0	0
T12	79192	0	0	0
T20	48679	0	0	0
T21	17051	0	0	0
T23	5285	0	0	0
T56	0	35	0	0
T59	0	65	0	0
T65	0	153	0	0
T70	0	11	0	0
T71	0	193	0	0
T91	0	39	0	0
T93	0	51	0	0
T94	0	54	0	0
T120	0	40	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12008071	7702	0	0
T6	13345	235	0	0
T7	4583	0	0	0
T8	4342	0	0	0
T9	2392	0	0	0
T10	385827	0	0	0
T11	2256	0	0	0
T12	79192	0	0	0
T20	48679	0	0	0
T21	17051	0	0	0
T23	5285	0	0	0
T56	0	68	0	0
T59	0	58	0	0
T65	0	106	0	0
T70	0	17	0	0
T71	0	194	0	0
T91	0	26	0	0
T93	0	57	0	0
T94	0	58	0	0
T120	0	39	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12008071	7936	0	0
T6	13345	219	0	0
T7	4583	0	0	0
T8	4342	0	0	0
T9	2392	0	0	0
T10	385827	0	0	0
T11	2256	0	0	0
T12	79192	0	0	0
T20	48679	0	0	0
T21	17051	0	0	0
T23	5285	0	0	0
T56	0	48	0	0
T59	0	79	0	0
T65	0	97	0	0
T70	0	11	0	0
T71	0	208	0	0
T91	0	36	0	0
T93	0	71	0	0
T94	0	51	0	0
T120	0	45	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12008071	3810	0	0
T6	13345	34	0	0
T7	4583	0	0	0
T8	4342	0	0	0
T9	2392	0	0	0
T10	385827	0	0	0
T11	2256	0	0	0
T12	79192	0	0	0
T20	48679	0	0	0
T21	17051	0	0	0
T23	5285	0	0	0
T56	0	44	0	0
T59	0	90	0	0
T65	0	18	0	0
T70	0	5	0	0
T71	0	119	0	0
T91	0	53	0	0
T93	0	58	0	0
T94	0	81	0	0
T120	0	46	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12008071	3709	0	0
T6	13345	19	0	0
T7	4583	0	0	0
T8	4342	0	0	0
T9	2392	0	0	0
T10	385827	0	0	0
T11	2256	0	0	0
T12	79192	0	0	0
T20	48679	0	0	0
T21	17051	0	0	0
T23	5285	0	0	0
T56	0	44	0	0
T59	0	66	0	0
T65	0	17	0	0
T70	0	11	0	0
T71	0	106	0	0
T91	0	39	0	0
T93	0	52	0	0
T94	0	67	0	0
T120	0	49	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12008071	3800	0	0
T6	13345	29	0	0
T7	4583	0	0	0
T8	4342	0	0	0
T9	2392	0	0	0
T10	385827	0	0	0
T11	2256	0	0	0
T12	79192	0	0	0
T20	48679	0	0	0
T21	17051	0	0	0
T23	5285	0	0	0
T56	0	36	0	0
T59	0	89	0	0
T65	0	6	0	0
T70	0	2	0	0
T71	0	121	0	0
T91	0	42	0	0
T93	0	54	0	0
T94	0	83	0	0
T120	0	54	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12008071	3959	0	0
T6	13345	18	0	0
T7	4583	0	0	0
T8	4342	0	0	0
T9	2392	0	0	0
T10	385827	0	0	0
T11	2256	0	0	0
T12	79192	0	0	0
T20	48679	0	0	0
T21	17051	0	0	0
T23	5285	0	0	0
T56	0	52	0	0
T59	0	87	0	0
T65	0	27	0	0
T70	0	9	0	0
T71	0	115	0	0
T91	0	32	0	0
T93	0	59	0	0
T94	0	64	0	0
T120	0	46	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12008071	3969	0	0
T6	13345	39	0	0
T7	4583	0	0	0
T8	4342	0	0	0
T9	2392	0	0	0
T10	385827	0	0	0
T11	2256	0	0	0
T12	79192	0	0	0
T20	48679	0	0	0
T21	17051	0	0	0
T23	5285	0	0	0
T56	0	46	0	0
T59	0	89	0	0
T65	0	17	0	0
T70	0	5	0	0
T71	0	122	0	0
T91	0	50	0	0
T93	0	34	0	0
T94	0	67	0	0
T120	0	51	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12008071	3832	0	0
T6	13345	39	0	0
T7	4583	0	0	0
T8	4342	0	0	0
T9	2392	0	0	0
T10	385827	0	0	0
T11	2256	0	0	0
T12	79192	0	0	0
T20	48679	0	0	0
T21	17051	0	0	0
T23	5285	0	0	0
T56	0	66	0	0
T59	0	53	0	0
T65	0	26	0	0
T70	0	12	0	0
T71	0	115	0	0
T91	0	32	0	0
T93	0	62	0	0
T94	0	47	0	0
T120	0	34	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12008071	3792	0	0
T6	13345	27	0	0
T7	4583	0	0	0
T8	4342	0	0	0
T9	2392	0	0	0
T10	385827	0	0	0
T11	2256	0	0	0
T12	79192	0	0	0
T20	48679	0	0	0
T21	17051	0	0	0
T23	5285	0	0	0
T56	0	41	0	0
T59	0	69	0	0
T65	0	18	0	0
T70	0	5	0	0
T71	0	164	0	0
T91	0	43	0	0
T93	0	45	0	0
T94	0	57	0	0
T120	0	75	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12008071	3896	0	0
T6	13345	35	0	0
T7	4583	0	0	0
T8	4342	0	0	0
T9	2392	0	0	0
T10	385827	0	0	0
T11	2256	0	0	0
T12	79192	0	0	0
T20	48679	0	0	0
T21	17051	0	0	0
T23	5285	0	0	0
T56	0	38	0	0
T59	0	76	0	0
T65	0	15	0	0
T70	0	4	0	0
T71	0	108	0	0
T91	0	32	0	0
T93	0	38	0	0
T94	0	58	0	0
T120	0	41	0	0