Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11229889	12616	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11229889	116311	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11229889	6503697	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11229889	185901	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11229889	12616	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11229889	116311	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11229889	6503697	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11229889	185901	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229889	12616	0	0
T1	26115	75	0	0
T2	3000	0	0	0
T3	3601	4	0	0
T4	53824	75	0	0
T5	3550	0	0	0
T6	13345	0	0	0
T7	4583	4	0	0
T8	4342	4	0	0
T9	2392	4	0	0
T10	385827	0	0	0
T12	0	75	0	0
T20	0	75	0	0
T21	0	39	0	0
T22	0	18	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229889	116311	0	0
T1	26115	712	0	0
T2	3000	0	0	0
T3	3601	38	0	0
T4	53824	716	0	0
T5	3550	0	0	0
T6	13345	0	0	0
T7	4583	37	0	0
T8	4342	37	0	0
T9	2392	38	0	0
T10	385827	0	0	0
T12	0	677	0	0
T20	0	706	0	0
T21	0	355	0	0
T22	0	162	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229889	6503697	0	0
T1	26115	8743	0	0
T2	3000	915	0	0
T3	3601	2600	0	0
T4	53824	36182	0	0
T5	3550	598	0	0
T6	13345	12703	0	0
T7	4583	3593	0	0
T8	4342	3330	0	0
T9	2392	1427	0	0
T10	385827	41441	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229889	185901	0	0
T1	26115	1119	0	0
T2	3000	0	0	0
T3	3601	67	0	0
T4	53824	1171	0	0
T5	3550	0	0	0
T6	13345	0	0	0
T7	4583	60	0	0
T8	4342	64	0	0
T9	2392	66	0	0
T10	385827	0	0	0
T12	0	1068	0	0
T20	0	1093	0	0
T21	0	573	0	0
T22	0	247	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229889	12616	0	0
T1	26115	75	0	0
T2	3000	0	0	0
T3	3601	4	0	0
T4	53824	75	0	0
T5	3550	0	0	0
T6	13345	0	0	0
T7	4583	4	0	0
T8	4342	4	0	0
T9	2392	4	0	0
T10	385827	0	0	0
T12	0	75	0	0
T20	0	75	0	0
T21	0	39	0	0
T22	0	18	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229889	116311	0	0
T1	26115	712	0	0
T2	3000	0	0	0
T3	3601	38	0	0
T4	53824	716	0	0
T5	3550	0	0	0
T6	13345	0	0	0
T7	4583	37	0	0
T8	4342	37	0	0
T9	2392	38	0	0
T10	385827	0	0	0
T12	0	677	0	0
T20	0	706	0	0
T21	0	355	0	0
T22	0	162	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229889	6503697	0	0
T1	26115	8743	0	0
T2	3000	915	0	0
T3	3601	2600	0	0
T4	53824	36182	0	0
T5	3550	598	0	0
T6	13345	12703	0	0
T7	4583	3593	0	0
T8	4342	3330	0	0
T9	2392	1427	0	0
T10	385827	41441	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229889	185901	0	0
T1	26115	1119	0	0
T2	3000	0	0	0
T3	3601	67	0	0
T4	53824	1171	0	0
T5	3550	0	0	0
T6	13345	0	0	0
T7	4583	60	0	0
T8	4342	64	0	0
T9	2392	66	0	0
T10	385827	0	0	0
T12	0	1068	0	0
T20	0	1093	0	0
T21	0	573	0	0
T22	0	247	0	0