Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Covered	T8,T9,T12
1	0	Covered	T7,T12,T21

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	52474987	8586	0	0
CascadeEffAonToRstPorAboveRise_A	52474987	8586	0	0
CascadeEffAonToRstPorIoAboveFall_A	50374123	8586	0	0
CascadeEffAonToRstPorIoAboveRise_A	50374123	8586	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25187975	8586	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25187975	8586	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12593550	8586	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12593550	8586	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25187702	8586	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25187702	8586	0	0
CascadeLcToLcAboveFall_A	52474987	21202	0	0
CascadeLcToLcAboveRise_A	52474987	21202	0	0
CascadeLcToLcAonAboveFall_A	1589507	21202	0	0
CascadeLcToLcAonAboveRise_A	1589507	21202	0	0
CascadeLcToLcShadowedAboveFall_A	52474987	21202	0	0
CascadeLcToLcShadowedAboveRise_A	52474987	21202	0	0
CascadePorToAonAboveFall_A	1589507	6875	0	0
CascadeSysToSysAboveFall_A	52474987	21202	0	0
CascadeSysToSysAboveRise_A	52474987	21202	0	0
ScanRstToAonRise_A	1589507	197	0	0
StablePorToAonRise_A	1589507	8586	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11229889	21202	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11229889	21202	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11229889	21202	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11229889	21202	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12593550	21202	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12593550	21202	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11229889	21202	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11229889	21202	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11229889	21202	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11229889	21202	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52474987	8586	0	0
T1	121571	27	0	0
T2	13079	2	0	0
T3	15816	2	0	0
T4	235737	27	0	0
T5	15374	2	0	0
T6	55685	1	0	0
T7	19895	2	0	0
T8	18906	2	0	0
T9	11382	2	0	0
T10	165345	541	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52474987	8586	0	0
T1	121571	27	0	0
T2	13079	2	0	0
T3	15816	2	0	0
T4	235737	27	0	0
T5	15374	2	0	0
T6	55685	1	0	0
T7	19895	2	0	0
T8	18906	2	0	0
T9	11382	2	0	0
T10	165345	541	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50374123	8586	0	0
T1	116682	27	0	0
T2	12557	2	0	0
T3	15180	2	0	0
T4	226269	27	0	0
T5	14758	2	0	0
T6	53455	1	0	0
T7	19097	2	0	0
T8	18148	2	0	0
T9	10923	2	0	0
T10	158733	541	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50374123	8586	0	0
T1	116682	27	0	0
T2	12557	2	0	0
T3	15180	2	0	0
T4	226269	27	0	0
T5	14758	2	0	0
T6	53455	1	0	0
T7	19097	2	0	0
T8	18148	2	0	0
T9	10923	2	0	0
T10	158733	541	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25187975	8586	0	0
T1	58371	27	0	0
T2	6277	2	0	0
T3	7590	2	0	0
T4	113158	27	0	0
T5	7380	2	0	0
T6	26728	1	0	0
T7	9548	2	0	0
T8	9078	2	0	0
T9	5461	2	0	0
T10	793672	541	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25187975	8586	0	0
T1	58371	27	0	0
T2	6277	2	0	0
T3	7590	2	0	0
T4	113158	27	0	0
T5	7380	2	0	0
T6	26728	1	0	0
T7	9548	2	0	0
T8	9078	2	0	0
T9	5461	2	0	0
T10	793672	541	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593550	8586	0	0
T1	29176	27	0	0
T2	3138	2	0	0
T3	3792	2	0	0
T4	56572	27	0	0
T5	3689	2	0	0
T6	13363	1	0	0
T7	4773	2	0	0
T8	4538	2	0	0
T9	2730	2	0	0
T10	396867	541	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593550	8586	0	0
T1	29176	27	0	0
T2	3138	2	0	0
T3	3792	2	0	0
T4	56572	27	0	0
T5	3689	2	0	0
T6	13363	1	0	0
T7	4773	2	0	0
T8	4538	2	0	0
T9	2730	2	0	0
T10	396867	541	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25187702	8586	0	0
T1	58339	27	0	0
T2	6278	2	0	0
T3	7586	2	0	0
T4	113166	27	0	0
T5	7379	2	0	0
T6	26728	1	0	0
T7	9550	2	0	0
T8	9075	2	0	0
T9	5461	2	0	0
T10	793692	541	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25187702	8586	0	0
T1	58339	27	0	0
T2	6278	2	0	0
T3	7586	2	0	0
T4	113166	27	0	0
T5	7379	2	0	0
T6	26728	1	0	0
T7	9550	2	0	0
T8	9075	2	0	0
T9	5461	2	0	0
T10	793692	541	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52474987	21202	0	0
T1	121571	102	0	0
T2	13079	2	0	0
T3	15816	6	0	0
T4	235737	102	0	0
T5	15374	2	0	0
T6	55685	1	0	0
T7	19895	6	0	0
T8	18906	6	0	0
T9	11382	6	0	0
T10	165345	541	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52474987	21202	0	0
T1	121571	102	0	0
T2	13079	2	0	0
T3	15816	6	0	0
T4	235737	102	0	0
T5	15374	2	0	0
T6	55685	1	0	0
T7	19895	6	0	0
T8	18906	6	0	0
T9	11382	6	0	0
T10	165345	541	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1589507	21202	0	0
T1	3663	102	0	0
T2	391	2	0	0
T3	472	6	0	0
T4	7086	102	0	0
T5	459	2	0	0
T6	1669	1	0	0
T7	595	6	0	0
T8	566	6	0	0
T9	340	6	0	0
T10	49850	541	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1589507	21202	0	0
T1	3663	102	0	0
T2	391	2	0	0
T3	472	6	0	0
T4	7086	102	0	0
T5	459	2	0	0
T6	1669	1	0	0
T7	595	6	0	0
T8	566	6	0	0
T9	340	6	0	0
T10	49850	541	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52474987	21202	0	0
T1	121571	102	0	0
T2	13079	2	0	0
T3	15816	6	0	0
T4	235737	102	0	0
T5	15374	2	0	0
T6	55685	1	0	0
T7	19895	6	0	0
T8	18906	6	0	0
T9	11382	6	0	0
T10	165345	541	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52474987	21202	0	0
T1	121571	102	0	0
T2	13079	2	0	0
T3	15816	6	0	0
T4	235737	102	0	0
T5	15374	2	0	0
T6	55685	1	0	0
T7	19895	6	0	0
T8	18906	6	0	0
T9	11382	6	0	0
T10	165345	541	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1589507	6875	0	0
T1	3663	27	0	0
T2	391	9	0	0
T3	472	1	0	0
T4	7086	27	0	0
T5	459	13	0	0
T6	1669	1	0	0
T7	595	1	0	0
T8	566	1	0	0
T9	340	1	0	0
T10	49850	541	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52474987	21202	0	0
T1	121571	102	0	0
T2	13079	2	0	0
T3	15816	6	0	0
T4	235737	102	0	0
T5	15374	2	0	0
T6	55685	1	0	0
T7	19895	6	0	0
T8	18906	6	0	0
T9	11382	6	0	0
T10	165345	541	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52474987	21202	0	0
T1	121571	102	0	0
T2	13079	2	0	0
T3	15816	6	0	0
T4	235737	102	0	0
T5	15374	2	0	0
T6	55685	1	0	0
T7	19895	6	0	0
T8	18906	6	0	0
T9	11382	6	0	0
T10	165345	541	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1589507	197	0	0
T8	566	1	0	0
T9	340	0	0	0
T10	49850	0	0	0
T11	303	0	0	0
T12	11438	3	0	0
T20	6527	0	0	0
T21	2879	3	0	0
T23	730	0	0	0
T49	194	0	0	0
T53	731	0	0	0
T57	0	2	0	0
T63	0	3	0	0
T69	0	2	0	0
T91	0	1	0	0
T92	0	1	0	0
T94	0	1	0	0
T122	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1589507	8586	0	0
T1	3663	27	0	0
T2	391	2	0	0
T3	472	2	0	0
T4	7086	27	0	0
T5	459	2	0	0
T6	1669	1	0	0
T7	595	2	0	0
T8	566	2	0	0
T9	340	2	0	0
T10	49850	541	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229889	21202	0	0
T1	26115	102	0	0
T2	3000	2	0	0
T3	3601	6	0	0
T4	53824	102	0	0
T5	3550	2	0	0
T6	13345	1	0	0
T7	4583	6	0	0
T8	4342	6	0	0
T9	2392	6	0	0
T10	385827	541	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229889	21202	0	0
T1	26115	102	0	0
T2	3000	2	0	0
T3	3601	6	0	0
T4	53824	102	0	0
T5	3550	2	0	0
T6	13345	1	0	0
T7	4583	6	0	0
T8	4342	6	0	0
T9	2392	6	0	0
T10	385827	541	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229889	21202	0	0
T1	26115	102	0	0
T2	3000	2	0	0
T3	3601	6	0	0
T4	53824	102	0	0
T5	3550	2	0	0
T6	13345	1	0	0
T7	4583	6	0	0
T8	4342	6	0	0
T9	2392	6	0	0
T10	385827	541	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229889	21202	0	0
T1	26115	102	0	0
T2	3000	2	0	0
T3	3601	6	0	0
T4	53824	102	0	0
T5	3550	2	0	0
T6	13345	1	0	0
T7	4583	6	0	0
T8	4342	6	0	0
T9	2392	6	0	0
T10	385827	541	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593550	21202	0	0
T1	29176	102	0	0
T2	3138	2	0	0
T3	3792	6	0	0
T4	56572	102	0	0
T5	3689	2	0	0
T6	13363	1	0	0
T7	4773	6	0	0
T8	4538	6	0	0
T9	2730	6	0	0
T10	396867	541	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593550	21202	0	0
T1	29176	102	0	0
T2	3138	2	0	0
T3	3792	6	0	0
T4	56572	102	0	0
T5	3689	2	0	0
T6	13363	1	0	0
T7	4773	6	0	0
T8	4538	6	0	0
T9	2730	6	0	0
T10	396867	541	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229889	21202	0	0
T1	26115	102	0	0
T2	3000	2	0	0
T3	3601	6	0	0
T4	53824	102	0	0
T5	3550	2	0	0
T6	13345	1	0	0
T7	4583	6	0	0
T8	4342	6	0	0
T9	2392	6	0	0
T10	385827	541	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229889	21202	0	0
T1	26115	102	0	0
T2	3000	2	0	0
T3	3601	6	0	0
T4	53824	102	0	0
T5	3550	2	0	0
T6	13345	1	0	0
T7	4583	6	0	0
T8	4342	6	0	0
T9	2392	6	0	0
T10	385827	541	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229889	21202	0	0
T1	26115	102	0	0
T2	3000	2	0	0
T3	3601	6	0	0
T4	53824	102	0	0
T5	3550	2	0	0
T6	13345	1	0	0
T7	4583	6	0	0
T8	4342	6	0	0
T9	2392	6	0	0
T10	385827	541	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229889	21202	0	0
T1	26115	102	0	0
T2	3000	2	0	0
T3	3601	6	0	0
T4	53824	102	0	0
T5	3550	2	0	0
T6	13345	1	0	0
T7	4583	6	0	0
T8	4342	6	0	0
T9	2392	6	0	0
T10	385827	541	0	0