Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1184 |
1 |
|
|
T5 |
32 |
|
T7 |
32 |
|
T30 |
32 |
auto[1] |
3267 |
1 |
|
|
T3 |
3 |
|
T4 |
92 |
|
T5 |
17 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1184 |
1 |
|
|
T5 |
32 |
|
T7 |
32 |
|
T30 |
32 |
auto[1] |
3267 |
1 |
|
|
T3 |
3 |
|
T4 |
92 |
|
T5 |
17 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1266 |
1 |
|
|
T4 |
28 |
|
T5 |
14 |
|
T7 |
12 |
auto[1] |
3185 |
1 |
|
|
T3 |
3 |
|
T4 |
64 |
|
T5 |
35 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1266 |
1 |
|
|
T4 |
28 |
|
T5 |
14 |
|
T7 |
12 |
auto[1] |
3185 |
1 |
|
|
T3 |
3 |
|
T4 |
64 |
|
T5 |
35 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
296 |
1 |
|
|
T5 |
8 |
|
T7 |
8 |
|
T30 |
8 |
auto[0] |
auto[1] |
888 |
1 |
|
|
T5 |
24 |
|
T7 |
24 |
|
T30 |
24 |
auto[1] |
auto[0] |
970 |
1 |
|
|
T4 |
28 |
|
T5 |
6 |
|
T7 |
4 |
auto[1] |
auto[1] |
2297 |
1 |
|
|
T3 |
3 |
|
T4 |
64 |
|
T5 |
11 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1099 |
1 |
|
|
T5 |
28 |
|
T6 |
3 |
|
T7 |
28 |
auto[1] |
3162 |
1 |
|
|
T3 |
3 |
|
T4 |
92 |
|
T5 |
21 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1099 |
1 |
|
|
T5 |
28 |
|
T6 |
3 |
|
T7 |
28 |
auto[1] |
3162 |
1 |
|
|
T3 |
3 |
|
T4 |
92 |
|
T5 |
21 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1194 |
1 |
|
|
T4 |
28 |
|
T5 |
16 |
|
T6 |
2 |
auto[1] |
3067 |
1 |
|
|
T3 |
3 |
|
T4 |
64 |
|
T5 |
33 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1194 |
1 |
|
|
T4 |
28 |
|
T5 |
16 |
|
T6 |
2 |
auto[1] |
3067 |
1 |
|
|
T3 |
3 |
|
T4 |
64 |
|
T5 |
33 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
293 |
1 |
|
|
T5 |
7 |
|
T6 |
2 |
|
T7 |
7 |
auto[0] |
auto[1] |
806 |
1 |
|
|
T5 |
21 |
|
T6 |
1 |
|
T7 |
21 |
auto[1] |
auto[0] |
901 |
1 |
|
|
T4 |
28 |
|
T5 |
9 |
|
T7 |
9 |
auto[1] |
auto[1] |
2261 |
1 |
|
|
T3 |
3 |
|
T4 |
64 |
|
T5 |
12 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
966 |
1 |
|
|
T5 |
24 |
|
T7 |
24 |
|
T18 |
3 |
auto[1] |
3205 |
1 |
|
|
T3 |
3 |
|
T4 |
92 |
|
T5 |
25 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
966 |
1 |
|
|
T5 |
24 |
|
T7 |
24 |
|
T18 |
3 |
auto[1] |
3205 |
1 |
|
|
T3 |
3 |
|
T4 |
92 |
|
T5 |
25 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1152 |
1 |
|
|
T3 |
1 |
|
T4 |
26 |
|
T5 |
14 |
auto[1] |
3019 |
1 |
|
|
T3 |
2 |
|
T4 |
66 |
|
T5 |
35 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1152 |
1 |
|
|
T3 |
1 |
|
T4 |
26 |
|
T5 |
14 |
auto[1] |
3019 |
1 |
|
|
T3 |
2 |
|
T4 |
66 |
|
T5 |
35 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
263 |
1 |
|
|
T5 |
6 |
|
T7 |
6 |
|
T18 |
1 |
auto[0] |
auto[1] |
703 |
1 |
|
|
T5 |
18 |
|
T7 |
18 |
|
T18 |
2 |
auto[1] |
auto[0] |
889 |
1 |
|
|
T3 |
1 |
|
T4 |
26 |
|
T5 |
8 |
auto[1] |
auto[1] |
2316 |
1 |
|
|
T3 |
2 |
|
T4 |
66 |
|
T5 |
17 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
809 |
1 |
|
|
T3 |
3 |
|
T5 |
20 |
|
T7 |
20 |
auto[1] |
3344 |
1 |
|
|
T4 |
92 |
|
T5 |
29 |
|
T6 |
3 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
809 |
1 |
|
|
T3 |
3 |
|
T5 |
20 |
|
T7 |
20 |
auto[1] |
3344 |
1 |
|
|
T4 |
92 |
|
T5 |
29 |
|
T6 |
3 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1155 |
1 |
|
|
T3 |
1 |
|
T4 |
31 |
|
T5 |
13 |
auto[1] |
2998 |
1 |
|
|
T3 |
2 |
|
T4 |
61 |
|
T5 |
36 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1155 |
1 |
|
|
T3 |
1 |
|
T4 |
31 |
|
T5 |
13 |
auto[1] |
2998 |
1 |
|
|
T3 |
2 |
|
T4 |
61 |
|
T5 |
36 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
214 |
1 |
|
|
T3 |
1 |
|
T5 |
5 |
|
T7 |
5 |
auto[0] |
auto[1] |
595 |
1 |
|
|
T3 |
2 |
|
T5 |
15 |
|
T7 |
15 |
auto[1] |
auto[0] |
941 |
1 |
|
|
T4 |
31 |
|
T5 |
8 |
|
T6 |
1 |
auto[1] |
auto[1] |
2403 |
1 |
|
|
T4 |
61 |
|
T5 |
21 |
|
T6 |
2 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
652 |
1 |
|
|
T3 |
3 |
|
T5 |
16 |
|
T7 |
16 |
auto[1] |
3501 |
1 |
|
|
T4 |
92 |
|
T5 |
33 |
|
T6 |
3 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
652 |
1 |
|
|
T3 |
3 |
|
T5 |
16 |
|
T7 |
16 |
auto[1] |
3501 |
1 |
|
|
T4 |
92 |
|
T5 |
33 |
|
T6 |
3 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1127 |
1 |
|
|
T3 |
1 |
|
T4 |
31 |
|
T5 |
12 |
auto[1] |
3026 |
1 |
|
|
T3 |
2 |
|
T4 |
61 |
|
T5 |
37 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1127 |
1 |
|
|
T3 |
1 |
|
T4 |
31 |
|
T5 |
12 |
auto[1] |
3026 |
1 |
|
|
T3 |
2 |
|
T4 |
61 |
|
T5 |
37 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
175 |
1 |
|
|
T3 |
1 |
|
T5 |
4 |
|
T7 |
4 |
auto[0] |
auto[1] |
477 |
1 |
|
|
T3 |
2 |
|
T5 |
12 |
|
T7 |
12 |
auto[1] |
auto[0] |
952 |
1 |
|
|
T4 |
31 |
|
T5 |
8 |
|
T7 |
14 |
auto[1] |
auto[1] |
2549 |
1 |
|
|
T4 |
61 |
|
T5 |
25 |
|
T6 |
3 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
516 |
1 |
|
|
T3 |
3 |
|
T5 |
12 |
|
T6 |
3 |
auto[1] |
3637 |
1 |
|
|
T4 |
92 |
|
T5 |
37 |
|
T7 |
43 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
516 |
1 |
|
|
T3 |
3 |
|
T5 |
12 |
|
T6 |
3 |
auto[1] |
3637 |
1 |
|
|
T4 |
92 |
|
T5 |
37 |
|
T7 |
43 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1113 |
1 |
|
|
T3 |
2 |
|
T4 |
23 |
|
T5 |
15 |
auto[1] |
3040 |
1 |
|
|
T3 |
1 |
|
T4 |
69 |
|
T5 |
34 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1113 |
1 |
|
|
T3 |
2 |
|
T4 |
23 |
|
T5 |
15 |
auto[1] |
3040 |
1 |
|
|
T3 |
1 |
|
T4 |
69 |
|
T5 |
34 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
147 |
1 |
|
|
T3 |
2 |
|
T5 |
3 |
|
T6 |
1 |
auto[0] |
auto[1] |
369 |
1 |
|
|
T3 |
1 |
|
T5 |
9 |
|
T6 |
2 |
auto[1] |
auto[0] |
966 |
1 |
|
|
T4 |
23 |
|
T5 |
12 |
|
T7 |
9 |
auto[1] |
auto[1] |
2671 |
1 |
|
|
T4 |
69 |
|
T5 |
25 |
|
T7 |
34 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
362 |
1 |
|
|
T5 |
8 |
|
T7 |
8 |
|
T18 |
3 |
auto[1] |
3791 |
1 |
|
|
T3 |
3 |
|
T4 |
92 |
|
T5 |
41 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
362 |
1 |
|
|
T5 |
8 |
|
T7 |
8 |
|
T18 |
3 |
auto[1] |
3791 |
1 |
|
|
T3 |
3 |
|
T4 |
92 |
|
T5 |
41 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1184 |
1 |
|
|
T3 |
1 |
|
T4 |
32 |
|
T5 |
14 |
auto[1] |
2969 |
1 |
|
|
T3 |
2 |
|
T4 |
60 |
|
T5 |
35 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1184 |
1 |
|
|
T3 |
1 |
|
T4 |
32 |
|
T5 |
14 |
auto[1] |
2969 |
1 |
|
|
T3 |
2 |
|
T4 |
60 |
|
T5 |
35 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
109 |
1 |
|
|
T5 |
2 |
|
T7 |
2 |
|
T18 |
2 |
auto[0] |
auto[1] |
253 |
1 |
|
|
T5 |
6 |
|
T7 |
6 |
|
T18 |
1 |
auto[1] |
auto[0] |
1075 |
1 |
|
|
T3 |
1 |
|
T4 |
32 |
|
T5 |
12 |
auto[1] |
auto[1] |
2716 |
1 |
|
|
T3 |
2 |
|
T4 |
60 |
|
T5 |
29 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
202 |
1 |
|
|
T5 |
4 |
|
T7 |
4 |
|
T18 |
3 |
auto[1] |
3951 |
1 |
|
|
T3 |
3 |
|
T4 |
92 |
|
T5 |
45 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
202 |
1 |
|
|
T5 |
4 |
|
T7 |
4 |
|
T18 |
3 |
auto[1] |
3951 |
1 |
|
|
T3 |
3 |
|
T4 |
92 |
|
T5 |
45 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1154 |
1 |
|
|
T3 |
1 |
|
T4 |
28 |
|
T5 |
12 |
auto[1] |
2999 |
1 |
|
|
T3 |
2 |
|
T4 |
64 |
|
T5 |
37 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1154 |
1 |
|
|
T3 |
1 |
|
T4 |
28 |
|
T5 |
12 |
auto[1] |
2999 |
1 |
|
|
T3 |
2 |
|
T4 |
64 |
|
T5 |
37 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
62 |
1 |
|
|
T5 |
1 |
|
T7 |
1 |
|
T18 |
2 |
auto[0] |
auto[1] |
140 |
1 |
|
|
T5 |
3 |
|
T7 |
3 |
|
T18 |
1 |
auto[1] |
auto[0] |
1092 |
1 |
|
|
T3 |
1 |
|
T4 |
28 |
|
T5 |
11 |
auto[1] |
auto[1] |
2859 |
1 |
|
|
T3 |
2 |
|
T4 |
64 |
|
T5 |
34 |