Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	470363	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

284595

1

T3

144

T4

7108

T5

345

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	401367	1			T3	186		T4	10380		T5	475
values[0x0]	176458	1			T3	86		T4	4466		T5	215
values[0x1]	177133	1			T3	107		T4	4357		T5	214

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	394594	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

360364

1

T3

190

T4

9052

T5

414

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2385	1			T4	53		T5	3		T7	7
valid_sources[0x01]	2431	1			T6	1		T7	6		T9	1
valid_sources[0x02]	2592	1			T3	1		T4	60		T5	2
valid_sources[0x03]	3617	1			T3	4		T4	60		T5	1
valid_sources[0x04]	3094	1			T4	63		T7	3		T9	1
valid_sources[0x05]	2736	1			T4	115		T6	1		T7	4
valid_sources[0x06]	3063	1			T4	82		T5	7		T7	4
valid_sources[0x07]	2988	1			T3	3		T4	53		T5	7
valid_sources[0x08]	3683	1			T3	3		T4	7		T5	1
valid_sources[0x09]	2660	1			T4	188		T5	5		T6	4
valid_sources[0x0a]	3248	1			T3	1		T4	121		T5	7
valid_sources[0x0b]	2547	1			T3	3		T4	82		T5	9
valid_sources[0x0c]	2738	1			T4	65		T5	2		T6	1
valid_sources[0x0d]	2609	1			T4	105		T5	2		T6	3
valid_sources[0x0e]	2657	1			T3	1		T4	40		T5	4
valid_sources[0x0f]	3753	1			T3	1		T4	74		T6	1
valid_sources[0x10]	2481	1			T3	2		T4	60		T5	4
valid_sources[0x11]	2639	1			T3	7		T4	128		T5	3
valid_sources[0x12]	3361	1			T3	1		T4	65		T6	1
valid_sources[0x13]	3652	1			T3	2		T4	111		T5	2
valid_sources[0x14]	3746	1			T3	3		T4	62		T5	3
valid_sources[0x15]	2323	1			T4	53		T5	1		T93	2
valid_sources[0x16]	3080	1			T3	2		T4	168		T5	4
valid_sources[0x17]	2598	1			T4	172		T5	2		T7	10
valid_sources[0x18]	2477	1			T3	2		T4	68		T5	8
valid_sources[0x19]	2767	1			T3	1		T4	103		T5	3
valid_sources[0x1a]	2663	1			T3	2		T4	243		T5	2
valid_sources[0x1b]	2844	1			T3	1		T4	114		T5	1
valid_sources[0x1c]	3321	1			T3	2		T4	93		T5	3
valid_sources[0x1d]	4056	1			T4	42		T5	3		T6	2
valid_sources[0x1e]	2774	1			T4	38		T5	4		T6	1
valid_sources[0x1f]	2955	1			T3	2		T4	87		T5	5
valid_sources[0x20]	2578	1			T4	42		T5	3		T6	4
valid_sources[0x21]	2476	1			T3	1		T4	44		T5	1
valid_sources[0x22]	4039	1			T3	3		T4	22		T6	1
valid_sources[0x23]	2938	1			T3	1		T4	96		T5	14
valid_sources[0x24]	2751	1			T3	1		T4	92		T7	3
valid_sources[0x25]	3181	1			T3	1		T4	164		T9	4
valid_sources[0x26]	2828	1			T4	19		T5	3		T6	2
valid_sources[0x27]	2823	1			T3	1		T4	39		T7	3
valid_sources[0x28]	2860	1			T3	1		T4	78		T5	1
valid_sources[0x29]	2684	1			T3	4		T4	97		T5	8
valid_sources[0x2a]	2906	1			T3	2		T4	323		T5	2
valid_sources[0x2b]	2666	1			T3	3		T4	70		T5	6
valid_sources[0x2c]	2888	1			T4	73		T5	3		T6	1
valid_sources[0x2d]	3161	1			T3	3		T4	86		T5	4
valid_sources[0x2e]	4329	1			T3	1		T4	27		T5	6
valid_sources[0x2f]	2785	1			T3	2		T4	59		T5	5
valid_sources[0x30]	2349	1			T3	2		T4	44		T5	5
valid_sources[0x31]	2638	1			T3	1		T4	17		T5	8
valid_sources[0x32]	2571	1			T3	3		T4	164		T5	2
valid_sources[0x33]	2338	1			T4	182		T5	2		T6	2
valid_sources[0x34]	3846	1			T4	87		T5	2		T6	4
valid_sources[0x35]	2849	1			T3	3		T4	20		T6	3
valid_sources[0x36]	2556	1			T4	27		T5	6		T6	1
valid_sources[0x37]	2833	1			T4	192		T5	9		T6	1
valid_sources[0x38]	2757	1			T3	2		T4	37		T5	1
valid_sources[0x39]	2419	1			T4	82		T5	4		T6	2
valid_sources[0x3a]	2485	1			T3	4		T4	110		T6	2
valid_sources[0x3b]	2771	1			T4	9		T5	2		T6	3
valid_sources[0x3c]	2858	1			T4	115		T5	2		T6	3
valid_sources[0x3d]	2386	1			T3	1		T4	78		T5	4
valid_sources[0x3e]	5346	1			T4	58		T5	5		T6	3
valid_sources[0x3f]	2994	1			T3	3		T4	80		T5	1
valid_sources[0x40]	3171	1			T3	3		T4	64		T6	1
valid_sources[0x41]	2320	1			T3	2		T4	15		T5	5
valid_sources[0x42]	2469	1			T3	1		T4	63		T5	2
valid_sources[0x43]	2906	1			T3	2		T4	121		T5	4
valid_sources[0x44]	3099	1			T3	1		T4	45		T5	1
valid_sources[0x45]	2643	1			T3	3		T4	86		T5	8
valid_sources[0x46]	2825	1			T4	118		T5	2		T6	2
valid_sources[0x47]	2567	1			T3	2		T4	103		T5	10
valid_sources[0x48]	2666	1			T4	264		T5	2		T6	1
valid_sources[0x49]	3776	1			T3	1		T4	22		T5	3
valid_sources[0x4a]	2918	1			T3	2		T4	65		T5	1
valid_sources[0x4b]	2994	1			T4	120		T5	4		T6	2
valid_sources[0x4c]	6010	1			T3	2		T4	42		T5	2
valid_sources[0x4d]	2989	1			T4	113		T5	2		T6	3
valid_sources[0x4e]	2462	1			T3	1		T4	113		T5	5
valid_sources[0x4f]	2387	1			T4	34		T5	4		T6	4
valid_sources[0x50]	2544	1			T3	2		T4	113		T5	4
valid_sources[0x51]	2101	1			T4	28		T5	1		T6	2
valid_sources[0x52]	2438	1			T3	1		T4	96		T5	11
valid_sources[0x53]	2576	1			T4	43		T5	4		T6	3
valid_sources[0x54]	2853	1			T4	108		T5	6		T7	3
valid_sources[0x55]	3189	1			T3	2		T4	39		T5	1
valid_sources[0x56]	2496	1			T3	3		T4	69		T5	5
valid_sources[0x57]	5581	1			T3	4		T4	13		T5	7
valid_sources[0x58]	2549	1			T3	2		T4	77		T7	2
valid_sources[0x59]	2622	1			T3	3		T4	7		T5	4
valid_sources[0x5a]	2909	1			T3	2		T4	13		T5	8
valid_sources[0x5b]	3261	1			T3	1		T4	123		T6	2
valid_sources[0x5c]	2972	1			T3	3		T4	9		T5	3
valid_sources[0x5d]	3679	1			T3	3		T4	76		T5	5
valid_sources[0x5e]	2081	1			T3	2		T4	90		T5	5
valid_sources[0x5f]	3231	1			T3	5		T4	65		T5	6
valid_sources[0x60]	2827	1			T3	2		T4	21		T5	6
valid_sources[0x61]	2924	1			T3	4		T4	119		T5	3
valid_sources[0x62]	2887	1			T4	16		T5	1		T6	3
valid_sources[0x63]	3050	1			T3	4		T4	76		T5	3
valid_sources[0x64]	3061	1			T4	74		T5	3		T7	7
valid_sources[0x65]	2641	1			T3	1		T4	45		T6	3
valid_sources[0x66]	2799	1			T3	2		T4	58		T5	1
valid_sources[0x67]	2827	1			T6	4		T7	6		T9	1
valid_sources[0x68]	2596	1			T3	2		T4	50		T7	4
valid_sources[0x69]	3080	1			T3	6		T4	65		T5	2
valid_sources[0x6a]	2850	1			T3	3		T4	47		T5	10
valid_sources[0x6b]	2294	1			T3	2		T4	11		T6	3
valid_sources[0x6c]	2452	1			T3	2		T4	111		T5	20
valid_sources[0x6d]	2655	1			T3	5		T4	73		T5	1
valid_sources[0x6e]	2570	1			T3	2		T4	11		T5	4
valid_sources[0x6f]	2126	1			T3	3		T4	22		T5	2
valid_sources[0x70]	2616	1			T4	78		T5	5		T9	1
valid_sources[0x71]	2443	1			T3	4		T4	39		T5	5
valid_sources[0x72]	2648	1			T4	18		T5	8		T6	3
valid_sources[0x73]	2895	1			T3	1		T4	127		T5	2
valid_sources[0x74]	2814	1			T4	87		T5	5		T7	1
valid_sources[0x75]	2478	1			T3	3		T4	115		T5	6
valid_sources[0x76]	2858	1			T3	1		T4	39		T5	7
valid_sources[0x77]	2574	1			T4	59		T5	1		T6	5
valid_sources[0x78]	3772	1			T3	1		T4	46		T5	1
valid_sources[0x79]	2724	1			T4	151		T5	1		T6	2
valid_sources[0x7a]	2758	1			T3	1		T4	56		T5	5
valid_sources[0x7b]	2353	1			T4	149		T5	5		T6	1
valid_sources[0x7c]	4091	1			T3	2		T4	31		T5	4
valid_sources[0x7d]	3141	1			T3	1		T4	57		T5	3
valid_sources[0x7e]	2682	1			T3	1		T4	96		T5	5
valid_sources[0x7f]	3528	1			T3	4		T4	42		T6	3
valid_sources[0x80]	2296	1			T3	3		T4	64		T5	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

188355

1

T3

93

T4

4886

T5

245

values[0x0]

all_enables

biggest_size

62425

1

T3

28

T4

1496

T5

65

values[0x1]

all_enables

biggest_size

33815

1

T3

23

T4

726

T5

35