Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_mubi4_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_ctrl_scanmode_sync 100.00 100.00 100.00
tb.dut.u_daon_por.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_daon_por_io.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_daon_por_io_div2.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_daon_por_io_div4.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_daon_por_usb.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_daon_lc.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_lc.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_daon_lc_shadowed.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_lc_shadowed.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_daon_lc_aon.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_daon_lc_io.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_lc_io.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div2.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div2.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div4.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div4.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_daon_lc_usb.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_lc_usb.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_sys.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_daon_sys_io_div4.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_spi_device.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_spi_host0.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_spi_host1.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_usb.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_usb_aon.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_i2c0.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_i2c1.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_d0_i2c2.u_scanmode_sync 100.00 100.00 100.00
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync 100.00 100.00 100.00
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_ctrl_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_daon_por.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_daon_por_io.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_io


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_daon_por_io_div2.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_io_div2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_daon_por_io_div4.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_daon_por_usb.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_daon_lc.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_lc.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_daon_lc_shadowed.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_lc_shadowed.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_daon_lc_aon.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_io


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_io


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io_div2.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_io_div2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io_div2.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_io_div2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io_div4.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_daon_lc_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io_div4.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_d0_lc_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_daon_lc_io_div4_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_d0_lc_io_div4_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_daon_lc_usb.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_lc_usb.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_sys.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_sys


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_daon_sys_io_div4.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_sys_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_spi_device.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_spi_device


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_spi_host0.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_spi_host0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_spi_host1.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_spi_host1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_usb.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_usb_aon.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_d0_usb_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_i2c0.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_i2c0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_i2c1.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_i2c1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_d0_i2c2.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_i2c2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00

Line Coverage for Module : prim_mubi4_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Module : prim_mubi4_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 13431 13431 0 0
OutputsKnown_A 284144115 165582261 0 0
gen_no_flops.OutputDelay_A 284144115 165582261 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13431 13431 0 0
T1 33 33 0 0
T2 33 33 0 0
T3 33 33 0 0
T4 33 33 0 0
T5 33 33 0 0
T6 33 33 0 0
T7 33 33 0 0
T11 33 33 0 0
T12 33 33 0 0
T16 33 33 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 284144115 165582261 0 0
T1 180598 17645 0 0
T2 180568 17678 0 0
T3 191031 158950 0 0
T4 3768756 1996871 0 0
T5 100075 78724 0 0
T6 191819 158896 0 0
T7 275476 256462 0 0
T11 1090889 794494 0 0
T12 1231498 790069 0 0
T16 54568 33085 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 284144115 165582261 0 0
T1 180598 17645 0 0
T2 180568 17678 0 0
T3 191031 158950 0 0
T4 3768756 1996871 0 0
T5 100075 78724 0 0
T6 191819 158896 0 0
T7 275476 256462 0 0
T11 1090889 794494 0 0
T12 1231498 790069 0 0
T16 54568 33085 0 0

Line Coverage for Instance : tb.dut.u_ctrl_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_ctrl_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 9688787 5835541 0 0
gen_no_flops.OutputDelay_A 9688787 5835541 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9688787 5835541 0 0
T1 5814 685 0 0
T2 5816 686 0 0
T3 6071 5062 0 0
T4 144692 85479 0 0
T5 3051 2404 0 0
T6 6091 5104 0 0
T7 8436 7790 0 0
T11 37385 27454 0 0
T12 42858 27349 0 0
T16 1672 1021 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9688787 5835541 0 0
T1 5814 685 0 0
T2 5816 686 0 0
T3 6071 5062 0 0
T4 144692 85479 0 0
T5 3051 2404 0 0
T6 6091 5104 0 0
T7 8436 7790 0 0
T11 37385 27454 0 0
T12 42858 27349 0 0
T16 1672 1021 0 0

Line Coverage for Instance : tb.dut.u_daon_por.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_daon_por.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_daon_por_io.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io_div2.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io_div4.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.u_daon_por_usb.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_daon_por_usb.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.u_daon_lc.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.u_d0_lc.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_aon.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_aon.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_io.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_io.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_usb.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_usb.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_usb.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_usb.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.u_d0_sys.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_sys.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_device.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_spi_device.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_host0.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_spi_host0.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_host1.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_spi_host1.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.u_d0_usb.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_usb.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.u_d0_usb_aon.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_usb_aon.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c0.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_i2c0.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c1.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_i2c1.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c2.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_d0_i2c2.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 407 407 0 0
OutputsKnown_A 8576729 4992085 0 0
gen_no_flops.OutputDelay_A 8576729 4992085 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 407 407 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8576729 4992085 0 0
T1 5462 530 0 0
T2 5461 531 0 0
T3 5780 4809 0 0
T4 113252 59731 0 0
T5 3032 2385 0 0
T6 5804 4806 0 0
T7 8345 7771 0 0
T11 32922 23970 0 0
T12 37145 23835 0 0
T16 1653 1002 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%