Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
978464 |
952416 |
0 |
0 |
selKnown1 |
128896 |
102848 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
978464 |
952416 |
0 |
0 |
T1 |
534 |
470 |
0 |
0 |
T2 |
534 |
470 |
0 |
0 |
T3 |
350 |
286 |
0 |
0 |
T4 |
21451 |
21387 |
0 |
0 |
T5 |
127 |
63 |
0 |
0 |
T6 |
350 |
286 |
0 |
0 |
T7 |
131 |
67 |
0 |
0 |
T11 |
3627 |
3563 |
0 |
0 |
T12 |
3439 |
3375 |
0 |
0 |
T13 |
0 |
97 |
0 |
0 |
T14 |
0 |
5152 |
0 |
0 |
T15 |
0 |
87 |
0 |
0 |
T16 |
64 |
0 |
0 |
0 |
T27 |
0 |
26 |
0 |
0 |
T29 |
0 |
45 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
128896 |
102848 |
0 |
0 |
T3 |
128 |
64 |
0 |
0 |
T4 |
3008 |
2944 |
0 |
0 |
T5 |
64 |
0 |
0 |
0 |
T6 |
128 |
64 |
0 |
0 |
T7 |
64 |
0 |
0 |
0 |
T11 |
640 |
576 |
0 |
0 |
T12 |
832 |
768 |
0 |
0 |
T13 |
64 |
0 |
0 |
0 |
T14 |
1344 |
1280 |
0 |
0 |
T16 |
64 |
0 |
0 |
0 |
T17 |
0 |
64 |
0 |
0 |
T18 |
0 |
64 |
0 |
0 |
T28 |
0 |
64 |
0 |
0 |
T29 |
0 |
2688 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16621 |
16214 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16621 |
16214 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16621 |
16214 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16621 |
16214 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16621 |
16214 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16621 |
16214 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16621 |
16214 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16621 |
16214 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
6490 |
6083 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6490 |
6083 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
110 |
109 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
19 |
18 |
0 |
0 |
T12 |
29 |
28 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
42 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16659 |
16252 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16659 |
16252 |
0 |
0 |
T1 |
9 |
8 |
0 |
0 |
T2 |
9 |
8 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
6490 |
6083 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6490 |
6083 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
110 |
109 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
19 |
18 |
0 |
0 |
T12 |
29 |
28 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
42 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16659 |
16252 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16659 |
16252 |
0 |
0 |
T1 |
9 |
8 |
0 |
0 |
T2 |
9 |
8 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
6490 |
6083 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6490 |
6083 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
110 |
109 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
19 |
18 |
0 |
0 |
T12 |
29 |
28 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
42 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16659 |
16252 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16659 |
16252 |
0 |
0 |
T1 |
9 |
8 |
0 |
0 |
T2 |
9 |
8 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
6490 |
6083 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6490 |
6083 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
110 |
109 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
19 |
18 |
0 |
0 |
T12 |
29 |
28 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
42 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16659 |
16252 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16659 |
16252 |
0 |
0 |
T1 |
9 |
8 |
0 |
0 |
T2 |
9 |
8 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
6490 |
6083 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6490 |
6083 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
110 |
109 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
19 |
18 |
0 |
0 |
T12 |
29 |
28 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
42 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16659 |
16252 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16659 |
16252 |
0 |
0 |
T1 |
9 |
8 |
0 |
0 |
T2 |
9 |
8 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16621 |
16214 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16621 |
16214 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16659 |
16252 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16659 |
16252 |
0 |
0 |
T1 |
9 |
8 |
0 |
0 |
T2 |
9 |
8 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16621 |
16214 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16621 |
16214 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16659 |
16252 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16659 |
16252 |
0 |
0 |
T1 |
9 |
8 |
0 |
0 |
T2 |
9 |
8 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16621 |
16214 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16621 |
16214 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16659 |
16252 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16659 |
16252 |
0 |
0 |
T1 |
9 |
8 |
0 |
0 |
T2 |
9 |
8 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16621 |
16214 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16621 |
16214 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16659 |
16252 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16659 |
16252 |
0 |
0 |
T1 |
9 |
8 |
0 |
0 |
T2 |
9 |
8 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16621 |
16214 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16621 |
16214 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16566 |
16159 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16566 |
16159 |
0 |
0 |
T1 |
7 |
6 |
0 |
0 |
T2 |
7 |
6 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
369 |
368 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16621 |
16214 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16621 |
16214 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16659 |
16252 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16659 |
16252 |
0 |
0 |
T1 |
9 |
8 |
0 |
0 |
T2 |
9 |
8 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16621 |
16214 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16621 |
16214 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16659 |
16252 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16659 |
16252 |
0 |
0 |
T1 |
9 |
8 |
0 |
0 |
T2 |
9 |
8 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16621 |
16214 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16621 |
16214 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16659 |
16252 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16659 |
16252 |
0 |
0 |
T1 |
9 |
8 |
0 |
0 |
T2 |
9 |
8 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16621 |
16214 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16621 |
16214 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16659 |
16252 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16659 |
16252 |
0 |
0 |
T1 |
9 |
8 |
0 |
0 |
T2 |
9 |
8 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16621 |
16214 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16621 |
16214 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16621 |
16214 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16621 |
16214 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16621 |
16214 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16621 |
16214 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16621 |
16214 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16621 |
16214 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16621 |
16214 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16621 |
16214 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16659 |
16252 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16659 |
16252 |
0 |
0 |
T1 |
9 |
8 |
0 |
0 |
T2 |
9 |
8 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16621 |
16214 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16621 |
16214 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16659 |
16252 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16659 |
16252 |
0 |
0 |
T1 |
9 |
8 |
0 |
0 |
T2 |
9 |
8 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16621 |
16214 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16621 |
16214 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16659 |
16252 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16659 |
16252 |
0 |
0 |
T1 |
9 |
8 |
0 |
0 |
T2 |
9 |
8 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16621 |
16214 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16621 |
16214 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16659 |
16252 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16659 |
16252 |
0 |
0 |
T1 |
9 |
8 |
0 |
0 |
T2 |
9 |
8 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
17219 |
16812 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17219 |
16812 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
387 |
386 |
0 |
0 |
T5 |
5 |
4 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
5 |
4 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16659 |
16252 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16659 |
16252 |
0 |
0 |
T1 |
9 |
8 |
0 |
0 |
T2 |
9 |
8 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
17255 |
16848 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17255 |
16848 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
390 |
389 |
0 |
0 |
T5 |
7 |
6 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
8 |
7 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16659 |
16252 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16659 |
16252 |
0 |
0 |
T1 |
9 |
8 |
0 |
0 |
T2 |
9 |
8 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
17275 |
16868 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17275 |
16868 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
7 |
6 |
0 |
0 |
T4 |
389 |
388 |
0 |
0 |
T5 |
8 |
7 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
8 |
7 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16659 |
16252 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16659 |
16252 |
0 |
0 |
T1 |
9 |
8 |
0 |
0 |
T2 |
9 |
8 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
17342 |
16935 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17342 |
16935 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
393 |
392 |
0 |
0 |
T5 |
8 |
7 |
0 |
0 |
T6 |
7 |
6 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16659 |
16252 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16659 |
16252 |
0 |
0 |
T1 |
9 |
8 |
0 |
0 |
T2 |
9 |
8 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
17347 |
16940 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17347 |
16940 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
391 |
390 |
0 |
0 |
T5 |
8 |
7 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
11 |
10 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16566 |
16159 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16566 |
16159 |
0 |
0 |
T1 |
7 |
6 |
0 |
0 |
T2 |
7 |
6 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
369 |
368 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
17388 |
16981 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17388 |
16981 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
387 |
386 |
0 |
0 |
T5 |
12 |
11 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16659 |
16252 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16659 |
16252 |
0 |
0 |
T1 |
9 |
8 |
0 |
0 |
T2 |
9 |
8 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
17458 |
17051 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17458 |
17051 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
7 |
6 |
0 |
0 |
T4 |
393 |
392 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
7 |
6 |
0 |
0 |
T7 |
10 |
9 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16659 |
16252 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16659 |
16252 |
0 |
0 |
T1 |
9 |
8 |
0 |
0 |
T2 |
9 |
8 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
17474 |
17067 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17474 |
17067 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
7 |
6 |
0 |
0 |
T4 |
389 |
388 |
0 |
0 |
T5 |
12 |
11 |
0 |
0 |
T6 |
7 |
6 |
0 |
0 |
T7 |
15 |
14 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
16659 |
16252 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16659 |
16252 |
0 |
0 |
T1 |
9 |
8 |
0 |
0 |
T2 |
9 |
8 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
370 |
369 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
63 |
62 |
0 |
0 |
T12 |
58 |
57 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
102 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
5362 |
4955 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5362 |
4955 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
64 |
63 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
17 |
16 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
T14 |
0 |
22 |
0 |
0 |
T15 |
0 |
18 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T27 |
0 |
26 |
0 |
0 |
T29 |
0 |
45 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
6925 |
6518 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6925 |
6518 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
110 |
109 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
19 |
18 |
0 |
0 |
T12 |
29 |
28 |
0 |
0 |
T13 |
0 |
17 |
0 |
0 |
T14 |
0 |
42 |
0 |
0 |
T15 |
0 |
15 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
6490 |
6083 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6490 |
6083 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
110 |
109 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
19 |
18 |
0 |
0 |
T12 |
29 |
28 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
42 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T4,T6,T11 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
6490 |
6083 |
0 |
0 |
selKnown1 |
2014 |
1607 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6490 |
6083 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
110 |
109 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
19 |
18 |
0 |
0 |
T12 |
29 |
28 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
42 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2014 |
1607 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
47 |
46 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T11 |
10 |
9 |
0 |
0 |
T12 |
13 |
12 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
21 |
20 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |