Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	9688787	10729	0	0
gen_assertions[0].RstEnOn_A	9688787	751	0	0
gen_assertions[0].RstNOff_A	9688787	10729	0	0
gen_assertions[0].RstNOn_A	9688787	751	0	0
gen_assertions[1].RstEnOff_A	38754767	9758	0	0
gen_assertions[1].RstEnOn_A	38754767	709	0	0
gen_assertions[1].RstNOff_A	38754767	9758	0	0
gen_assertions[1].RstNOn_A	38754767	709	0	0
gen_assertions[2].RstEnOff_A	19377970	9778	0	0
gen_assertions[2].RstEnOn_A	19377970	686	0	0
gen_assertions[2].RstNOff_A	19377970	9778	0	0
gen_assertions[2].RstNOn_A	19377970	686	0	0
gen_assertions[3].RstEnOff_A	19377952	9845	0	0
gen_assertions[3].RstEnOn_A	19377952	748	0	0
gen_assertions[3].RstNOff_A	19377952	9845	0	0
gen_assertions[3].RstNOn_A	19377952	748	0	0
gen_assertions[4].RstEnOff_A	1223397	16152	0	0
gen_assertions[4].RstEnOn_A	1223397	775	0	0
gen_assertions[4].RstNOff_A	1223397	16152	0	0
gen_assertions[4].RstNOn_A	1223397	775	0	0
gen_assertions[5].RstEnOff_A	9688787	10898	0	0
gen_assertions[5].RstEnOn_A	9688787	791	0	0
gen_assertions[5].RstNOff_A	9688787	10898	0	0
gen_assertions[5].RstNOn_A	9688787	791	0	0
gen_assertions[6].RstEnOff_A	9688787	10968	0	0
gen_assertions[6].RstEnOn_A	9688787	867	0	0
gen_assertions[6].RstNOff_A	9688787	10968	0	0
gen_assertions[6].RstNOn_A	9688787	867	0	0
gen_assertions[7].RstEnOff_A	9688787	10984	0	0
gen_assertions[7].RstEnOn_A	9688787	878	0	0
gen_assertions[7].RstNOff_A	9688787	10984	0	0
gen_assertions[7].RstNOn_A	9688787	878	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9688787	10729	0	0
T3	6071	4	0	0
T4	144692	277	0	0
T5	3051	4	0	0
T6	6091	4	0	0
T7	8436	4	0	0
T11	37385	44	0	0
T12	42858	29	0	0
T13	4819	0	0	0
T14	78349	73	0	0
T16	1672	0	0	0
T17	0	4	0	0
T18	0	4	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9688787	751	0	0
T4	144692	19	0	0
T5	3051	4	0	0
T6	6091	0	0	0
T7	8436	4	0	0
T14	78349	15	0	0
T15	5358	0	0	0
T17	2466	0	0	0
T18	5567	0	0	0
T27	29279	0	0	0
T28	3701	0	0	0
T29	0	9	0	0
T30	0	5	0	0
T41	0	5	0	0
T43	0	2	0	0
T81	0	3	0	0
T82	0	6	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9688787	10729	0	0
T3	6071	4	0	0
T4	144692	277	0	0
T5	3051	4	0	0
T6	6091	4	0	0
T7	8436	4	0	0
T11	37385	44	0	0
T12	42858	29	0	0
T13	4819	0	0	0
T14	78349	73	0	0
T16	1672	0	0	0
T17	0	4	0	0
T18	0	4	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9688787	751	0	0
T4	144692	19	0	0
T5	3051	4	0	0
T6	6091	0	0	0
T7	8436	4	0	0
T14	78349	15	0	0
T15	5358	0	0	0
T17	2466	0	0	0
T18	5567	0	0	0
T27	29279	0	0	0
T28	3701	0	0	0
T29	0	9	0	0
T30	0	5	0	0
T41	0	5	0	0
T43	0	2	0	0
T81	0	3	0	0
T82	0	6	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38754767	9758	0	0
T3	24280	3	0	0
T4	578772	255	0	0
T5	12205	6	0	0
T6	24369	4	0	0
T7	33746	7	0	0
T11	149499	38	0	0
T12	171461	28	0	0
T13	19283	0	0	0
T14	313364	66	0	0
T16	6691	0	0	0
T17	0	4	0	0
T18	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38754767	709	0	0
T4	578772	23	0	0
T5	12205	6	0	0
T6	24369	0	0	0
T7	33746	7	0	0
T14	313364	13	0	0
T15	21431	0	0	0
T17	9873	0	0	0
T18	22280	0	0	0
T27	117108	0	0	0
T28	14802	0	0	0
T29	0	9	0	0
T30	0	4	0	0
T41	0	8	0	0
T81	0	4	0	0
T82	0	6	0	0
T83	0	12	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38754767	9758	0	0
T3	24280	3	0	0
T4	578772	255	0	0
T5	12205	6	0	0
T6	24369	4	0	0
T7	33746	7	0	0
T11	149499	38	0	0
T12	171461	28	0	0
T13	19283	0	0	0
T14	313364	66	0	0
T16	6691	0	0	0
T17	0	4	0	0
T18	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38754767	709	0	0
T4	578772	23	0	0
T5	12205	6	0	0
T6	24369	0	0	0
T7	33746	7	0	0
T14	313364	13	0	0
T15	21431	0	0	0
T17	9873	0	0	0
T18	22280	0	0	0
T27	117108	0	0	0
T28	14802	0	0	0
T29	0	9	0	0
T30	0	4	0	0
T41	0	8	0	0
T81	0	4	0	0
T82	0	6	0	0
T83	0	12	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377970	9778	0	0
T3	12142	4	0	0
T4	289375	254	0	0
T5	6101	7	0	0
T6	12182	4	0	0
T7	16874	7	0	0
T11	74770	38	0	0
T12	85716	28	0	0
T13	9641	0	0	0
T14	156694	65	0	0
T16	3344	0	0	0
T17	0	4	0	0
T18	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377970	686	0	0
T3	12142	1	0	0
T4	289375	20	0	0
T5	6101	7	0	0
T6	12182	0	0	0
T7	16874	7	0	0
T14	156694	12	0	0
T15	10715	0	0	0
T17	4934	0	0	0
T18	11139	0	0	0
T27	58535	0	0	0
T29	0	10	0	0
T30	0	8	0	0
T41	0	7	0	0
T81	0	4	0	0
T82	0	9	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377970	9778	0	0
T3	12142	4	0	0
T4	289375	254	0	0
T5	6101	7	0	0
T6	12182	4	0	0
T7	16874	7	0	0
T11	74770	38	0	0
T12	85716	28	0	0
T13	9641	0	0	0
T14	156694	65	0	0
T16	3344	0	0	0
T17	0	4	0	0
T18	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377970	686	0	0
T3	12142	1	0	0
T4	289375	20	0	0
T5	6101	7	0	0
T6	12182	0	0	0
T7	16874	7	0	0
T14	156694	12	0	0
T15	10715	0	0	0
T17	4934	0	0	0
T18	11139	0	0	0
T27	58535	0	0	0
T29	0	10	0	0
T30	0	8	0	0
T41	0	7	0	0
T81	0	4	0	0
T82	0	9	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377952	9845	0	0
T3	12142	3	0	0
T4	289353	258	0	0
T5	6102	7	0	0
T6	12182	5	0	0
T7	16874	8	0	0
T11	74756	38	0	0
T12	85715	28	0	0
T13	9641	0	0	0
T14	156683	66	0	0
T16	3344	0	0	0
T17	0	4	0	0
T18	0	4	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377952	748	0	0
T4	289353	27	0	0
T5	6102	7	0	0
T6	12182	1	0	0
T7	16874	8	0	0
T14	156683	14	0	0
T15	10716	0	0	0
T17	4936	0	0	0
T18	11139	0	0	0
T27	58550	0	0	0
T28	7402	0	0	0
T29	0	10	0	0
T30	0	8	0	0
T41	0	5	0	0
T81	0	5	0	0
T82	0	10	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377952	9845	0	0
T3	12142	3	0	0
T4	289353	258	0	0
T5	6102	7	0	0
T6	12182	5	0	0
T7	16874	8	0	0
T11	74756	38	0	0
T12	85715	28	0	0
T13	9641	0	0	0
T14	156683	66	0	0
T16	3344	0	0	0
T17	0	4	0	0
T18	0	4	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377952	748	0	0
T4	289353	27	0	0
T5	6102	7	0	0
T6	12182	1	0	0
T7	16874	8	0	0
T14	156683	14	0	0
T15	10716	0	0	0
T17	4936	0	0	0
T18	11139	0	0	0
T27	58550	0	0	0
T28	7402	0	0	0
T29	0	10	0	0
T30	0	8	0	0
T41	0	5	0	0
T81	0	5	0	0
T82	0	10	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1223397	16152	0	0
T1	729	2	0	0
T2	729	3	0	0
T3	757	6	0	0
T4	18500	383	0	0
T5	380	8	0	0
T6	760	6	0	0
T7	1053	11	0	0
T11	4786	63	0	0
T12	5415	58	0	0
T16	207	1	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1223397	775	0	0
T4	18500	25	0	0
T5	380	7	0	0
T6	760	0	0	0
T7	1053	10	0	0
T14	9857	13	0	0
T15	669	0	0	0
T17	307	0	0	0
T18	696	0	0	0
T27	3673	0	0	0
T28	461	0	0	0
T29	0	8	0	0
T30	0	9	0	0
T41	0	7	0	0
T81	0	6	0	0
T82	0	9	0	0
T83	0	12	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1223397	16152	0	0
T1	729	2	0	0
T2	729	3	0	0
T3	757	6	0	0
T4	18500	383	0	0
T5	380	8	0	0
T6	760	6	0	0
T7	1053	11	0	0
T11	4786	63	0	0
T12	5415	58	0	0
T16	207	1	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1223397	775	0	0
T4	18500	25	0	0
T5	380	7	0	0
T6	760	0	0	0
T7	1053	10	0	0
T14	9857	13	0	0
T15	669	0	0	0
T17	307	0	0	0
T18	696	0	0	0
T27	3673	0	0	0
T28	461	0	0	0
T29	0	8	0	0
T30	0	9	0	0
T41	0	7	0	0
T81	0	6	0	0
T82	0	9	0	0
T83	0	12	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9688787	10898	0	0
T3	6071	4	0	0
T4	144692	277	0	0
T5	3051	11	0	0
T6	6091	4	0	0
T7	8436	8	0	0
T11	37385	44	0	0
T12	42858	29	0	0
T13	4819	0	0	0
T14	78349	74	0	0
T16	1672	0	0	0
T17	0	4	0	0
T18	0	5	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9688787	791	0	0
T4	144692	18	0	0
T5	3051	11	0	0
T6	6091	0	0	0
T7	8436	8	0	0
T14	78349	16	0	0
T15	5358	0	0	0
T17	2466	0	0	0
T18	5567	1	0	0
T27	29279	0	0	0
T28	3701	0	0	0
T29	0	10	0	0
T30	0	9	0	0
T41	0	7	0	0
T81	0	6	0	0
T82	0	13	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9688787	10898	0	0
T3	6071	4	0	0
T4	144692	277	0	0
T5	3051	11	0	0
T6	6091	4	0	0
T7	8436	8	0	0
T11	37385	44	0	0
T12	42858	29	0	0
T13	4819	0	0	0
T14	78349	74	0	0
T16	1672	0	0	0
T17	0	4	0	0
T18	0	5	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9688787	791	0	0
T4	144692	18	0	0
T5	3051	11	0	0
T6	6091	0	0	0
T7	8436	8	0	0
T14	78349	16	0	0
T15	5358	0	0	0
T17	2466	0	0	0
T18	5567	1	0	0
T27	29279	0	0	0
T28	3701	0	0	0
T29	0	10	0	0
T30	0	9	0	0
T41	0	7	0	0
T81	0	6	0	0
T82	0	13	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9688787	10968	0	0
T3	6071	5	0	0
T4	144692	283	0	0
T5	3051	10	0	0
T6	6091	5	0	0
T7	8436	9	0	0
T11	37385	44	0	0
T12	42858	29	0	0
T13	4819	0	0	0
T14	78349	74	0	0
T16	1672	0	0	0
T17	0	4	0	0
T18	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9688787	867	0	0
T3	6071	1	0	0
T4	144692	25	0	0
T5	3051	10	0	0
T6	6091	1	0	0
T7	8436	9	0	0
T14	78349	15	0	0
T15	5358	0	0	0
T17	2466	0	0	0
T18	5567	0	0	0
T27	29279	0	0	0
T29	0	9	0	0
T30	0	10	0	0
T41	0	7	0	0
T81	0	8	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9688787	10968	0	0
T3	6071	5	0	0
T4	144692	283	0	0
T5	3051	10	0	0
T6	6091	5	0	0
T7	8436	9	0	0
T11	37385	44	0	0
T12	42858	29	0	0
T13	4819	0	0	0
T14	78349	74	0	0
T16	1672	0	0	0
T17	0	4	0	0
T18	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9688787	867	0	0
T3	6071	1	0	0
T4	144692	25	0	0
T5	3051	10	0	0
T6	6091	1	0	0
T7	8436	9	0	0
T14	78349	15	0	0
T15	5358	0	0	0
T17	2466	0	0	0
T18	5567	0	0	0
T27	29279	0	0	0
T29	0	9	0	0
T30	0	10	0	0
T41	0	7	0	0
T81	0	8	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9688787	10984	0	0
T3	6071	5	0	0
T4	144692	279	0	0
T5	3051	11	0	0
T6	6091	5	0	0
T7	8436	14	0	0
T11	37385	44	0	0
T12	42858	29	0	0
T13	4819	0	0	0
T14	78349	74	0	0
T16	1672	0	0	0
T17	0	4	0	0
T18	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9688787	878	0	0
T3	6071	1	0	0
T4	144692	22	0	0
T5	3051	11	0	0
T6	6091	1	0	0
T7	8436	14	0	0
T14	78349	14	0	0
T15	5358	0	0	0
T17	2466	0	0	0
T18	5567	0	0	0
T27	29279	0	0	0
T29	0	6	0	0
T30	0	11	0	0
T41	0	8	0	0
T81	0	8	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9688787	10984	0	0
T3	6071	5	0	0
T4	144692	279	0	0
T5	3051	11	0	0
T6	6091	5	0	0
T7	8436	14	0	0
T11	37385	44	0	0
T12	42858	29	0	0
T13	4819	0	0	0
T14	78349	74	0	0
T16	1672	0	0	0
T17	0	4	0	0
T18	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9688787	878	0	0
T3	6071	1	0	0
T4	144692	22	0	0
T5	3051	11	0	0
T6	6091	1	0	0
T7	8436	14	0	0
T14	78349	14	0	0
T15	5358	0	0	0
T17	2466	0	0	0
T18	5567	0	0	0
T27	29279	0	0	0
T29	0	6	0	0
T30	0	11	0	0
T41	0	8	0	0
T81	0	8	0	0