SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_aon |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_daon_lc_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_d0_lc_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_daon_lc_io_div4_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_d0_lc_io_div4_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_sys |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_sys_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_device |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_host0 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_host1 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | u_d0_usb_aon |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c0 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c1 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 654051630 | 351884392 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 654051630 | 351884392 | 0 | 0 |
T1 | 392484 | 41141 | 0 | 0 |
T2 | 392484 | 41213 | 0 | 0 |
T3 | 409746 | 329228 | 0 | 0 |
T4 | 9767966 | 4430542 | 0 | 0 |
T5 | 205940 | 158604 | 0 | 0 |
T6 | 411168 | 329392 | 0 | 0 |
T7 | 569460 | 513335 | 0 | 0 |
T11 | 2523636 | 1681017 | 0 | 0 |
T12 | 2893276 | 1672786 | 0 | 0 |
T16 | 112878 | 68292 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 40371236 | 24331284 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 40371236 | 24331284 | 0 | 0 |
T1 | 24236 | 2862 | 0 | 0 |
T2 | 24218 | 2871 | 0 | 0 |
T3 | 25292 | 21088 | 0 | 0 |
T4 | 602841 | 356280 | 0 | 0 |
T5 | 12713 | 10020 | 0 | 0 |
T6 | 25381 | 21268 | 0 | 0 |
T7 | 35152 | 32463 | 0 | 0 |
T11 | 155757 | 114428 | 0 | 0 |
T12 | 178578 | 114002 | 0 | 0 |
T16 | 6969 | 4257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 38754767 | 23356718 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 38754767 | 23356718 | 0 | 0 |
T1 | 23246 | 2748 | 0 | 0 |
T2 | 23267 | 2757 | 0 | 0 |
T3 | 24280 | 20245 | 0 | 0 |
T4 | 578772 | 342088 | 0 | 0 |
T5 | 12205 | 9619 | 0 | 0 |
T6 | 24369 | 20419 | 0 | 0 |
T7 | 33746 | 31163 | 0 | 0 |
T11 | 149499 | 109819 | 0 | 0 |
T12 | 171461 | 109446 | 0 | 0 |
T16 | 6691 | 4087 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 19377970 | 11675736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19377970 | 11675736 | 0 | 0 |
T1 | 11627 | 1367 | 0 | 0 |
T2 | 11629 | 1375 | 0 | 0 |
T3 | 12142 | 10123 | 0 | 0 |
T4 | 289375 | 170982 | 0 | 0 |
T5 | 6101 | 4809 | 0 | 0 |
T6 | 12182 | 10208 | 0 | 0 |
T7 | 16874 | 15582 | 0 | 0 |
T11 | 74770 | 54917 | 0 | 0 |
T12 | 85716 | 54710 | 0 | 0 |
T16 | 3344 | 2043 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 9688787 | 5835541 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9688787 | 5835541 | 0 | 0 |
T1 | 5814 | 685 | 0 | 0 |
T2 | 5816 | 686 | 0 | 0 |
T3 | 6071 | 5062 | 0 | 0 |
T4 | 144692 | 85479 | 0 | 0 |
T5 | 3051 | 2404 | 0 | 0 |
T6 | 6091 | 5104 | 0 | 0 |
T7 | 8436 | 7790 | 0 | 0 |
T11 | 37385 | 27454 | 0 | 0 |
T12 | 42858 | 27349 | 0 | 0 |
T16 | 1672 | 1021 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 19377952 | 11675749 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19377952 | 11675749 | 0 | 0 |
T1 | 11630 | 1367 | 0 | 0 |
T2 | 11629 | 1375 | 0 | 0 |
T3 | 12142 | 10123 | 0 | 0 |
T4 | 289353 | 170965 | 0 | 0 |
T5 | 6102 | 4809 | 0 | 0 |
T6 | 12182 | 10208 | 0 | 0 |
T7 | 16874 | 15582 | 0 | 0 |
T11 | 74756 | 54909 | 0 | 0 |
T12 | 85715 | 54709 | 0 | 0 |
T16 | 3344 | 2043 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 40371236 | 21546448 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 40371236 | 21546448 | 0 | 0 |
T1 | 24236 | 2781 | 0 | 0 |
T2 | 24218 | 2783 | 0 | 0 |
T3 | 25292 | 20286 | 0 | 0 |
T4 | 602841 | 263262 | 0 | 0 |
T5 | 12713 | 10014 | 0 | 0 |
T6 | 25381 | 20265 | 0 | 0 |
T7 | 35152 | 32455 | 0 | 0 |
T11 | 155757 | 102331 | 0 | 0 |
T12 | 178578 | 102125 | 0 | 0 |
T16 | 6969 | 4249 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 40371236 | 21007854 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 40371236 | 21007854 | 0 | 0 |
T1 | 24236 | 2288 | 0 | 0 |
T2 | 24218 | 2292 | 0 | 0 |
T3 | 25292 | 20120 | 0 | 0 |
T4 | 602841 | 253753 | 0 | 0 |
T5 | 12713 | 9947 | 0 | 0 |
T6 | 25381 | 20097 | 0 | 0 |
T7 | 35152 | 32389 | 0 | 0 |
T11 | 155757 | 100702 | 0 | 0 |
T12 | 178578 | 99947 | 0 | 0 |
T16 | 6969 | 4183 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 40371236 | 21546219 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 40371236 | 21546219 | 0 | 0 |
T1 | 24236 | 2780 | 0 | 0 |
T2 | 24218 | 2784 | 0 | 0 |
T3 | 25292 | 20286 | 0 | 0 |
T4 | 602841 | 263262 | 0 | 0 |
T5 | 12713 | 10014 | 0 | 0 |
T6 | 25381 | 20265 | 0 | 0 |
T7 | 35152 | 32455 | 0 | 0 |
T11 | 155757 | 102331 | 0 | 0 |
T12 | 178578 | 102125 | 0 | 0 |
T16 | 6969 | 4249 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 40371236 | 21009397 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 40371236 | 21009397 | 0 | 0 |
T1 | 24236 | 2288 | 0 | 0 |
T2 | 24218 | 2292 | 0 | 0 |
T3 | 25292 | 20120 | 0 | 0 |
T4 | 602841 | 253753 | 0 | 0 |
T5 | 12713 | 9947 | 0 | 0 |
T6 | 25381 | 20097 | 0 | 0 |
T7 | 35152 | 32389 | 0 | 0 |
T11 | 155757 | 100702 | 0 | 0 |
T12 | 178578 | 99947 | 0 | 0 |
T16 | 6969 | 4183 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 1223397 | 639077 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1223397 | 639077 | 0 | 0 |
T1 | 729 | 73 | 0 | 0 |
T2 | 729 | 74 | 0 | 0 |
T3 | 757 | 602 | 0 | 0 |
T4 | 18500 | 7874 | 0 | 0 |
T5 | 380 | 299 | 0 | 0 |
T6 | 760 | 602 | 0 | 0 |
T7 | 1053 | 972 | 0 | 0 |
T11 | 4786 | 3114 | 0 | 0 |
T12 | 5415 | 3049 | 0 | 0 |
T16 | 207 | 126 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 38754767 | 20684512 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 38754767 | 20684512 | 0 | 0 |
T1 | 23246 | 2708 | 0 | 0 |
T2 | 23267 | 2710 | 0 | 0 |
T3 | 24280 | 19476 | 0 | 0 |
T4 | 578772 | 252767 | 0 | 0 |
T5 | 12205 | 9613 | 0 | 0 |
T6 | 24369 | 19457 | 0 | 0 |
T7 | 33746 | 31156 | 0 | 0 |
T11 | 149499 | 98210 | 0 | 0 |
T12 | 171461 | 98042 | 0 | 0 |
T16 | 6691 | 4079 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 38754767 | 20166370 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 38754767 | 20166370 | 0 | 0 |
T1 | 23246 | 2196 | 0 | 0 |
T2 | 23267 | 2198 | 0 | 0 |
T3 | 24280 | 19316 | 0 | 0 |
T4 | 578772 | 243647 | 0 | 0 |
T5 | 12205 | 9549 | 0 | 0 |
T6 | 24369 | 19297 | 0 | 0 |
T7 | 33746 | 31092 | 0 | 0 |
T11 | 149499 | 96642 | 0 | 0 |
T12 | 171461 | 95954 | 0 | 0 |
T16 | 6691 | 4015 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 19377970 | 10334471 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19377970 | 10334471 | 0 | 0 |
T1 | 11627 | 1351 | 0 | 0 |
T2 | 11629 | 1351 | 0 | 0 |
T3 | 12142 | 9737 | 0 | 0 |
T4 | 289375 | 126196 | 0 | 0 |
T5 | 6101 | 4806 | 0 | 0 |
T6 | 12182 | 9724 | 0 | 0 |
T7 | 16874 | 15579 | 0 | 0 |
T11 | 74770 | 49090 | 0 | 0 |
T12 | 85716 | 48994 | 0 | 0 |
T16 | 3344 | 2039 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 19377970 | 10075552 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19377970 | 10075552 | 0 | 0 |
T1 | 11627 | 1095 | 0 | 0 |
T2 | 11629 | 1095 | 0 | 0 |
T3 | 12142 | 9657 | 0 | 0 |
T4 | 289375 | 121636 | 0 | 0 |
T5 | 6101 | 4774 | 0 | 0 |
T6 | 12182 | 9644 | 0 | 0 |
T7 | 16874 | 15547 | 0 | 0 |
T11 | 74770 | 48306 | 0 | 0 |
T12 | 85716 | 47950 | 0 | 0 |
T16 | 3344 | 2007 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 9688787 | 5146316 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9688787 | 5146316 | 0 | 0 |
T1 | 5814 | 659 | 0 | 0 |
T2 | 5816 | 660 | 0 | 0 |
T3 | 6071 | 4861 | 0 | 0 |
T4 | 144692 | 62632 | 0 | 0 |
T5 | 3051 | 2402 | 0 | 0 |
T6 | 6091 | 4855 | 0 | 0 |
T7 | 8436 | 7788 | 0 | 0 |
T11 | 37385 | 24463 | 0 | 0 |
T12 | 42858 | 24428 | 0 | 0 |
T16 | 1672 | 1019 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 9688787 | 5016816 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9688787 | 5016816 | 0 | 0 |
T1 | 5814 | 531 | 0 | 0 |
T2 | 5816 | 532 | 0 | 0 |
T3 | 6071 | 4821 | 0 | 0 |
T4 | 144692 | 60352 | 0 | 0 |
T5 | 3051 | 2386 | 0 | 0 |
T6 | 6091 | 4815 | 0 | 0 |
T7 | 8436 | 7772 | 0 | 0 |
T11 | 37385 | 24071 | 0 | 0 |
T12 | 42858 | 23906 | 0 | 0 |
T16 | 1672 | 1003 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 9688787 | 5146316 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9688787 | 5146316 | 0 | 0 |
T1 | 5814 | 659 | 0 | 0 |
T2 | 5816 | 660 | 0 | 0 |
T3 | 6071 | 4861 | 0 | 0 |
T4 | 144692 | 62632 | 0 | 0 |
T5 | 3051 | 2402 | 0 | 0 |
T6 | 6091 | 4855 | 0 | 0 |
T7 | 8436 | 7788 | 0 | 0 |
T11 | 37385 | 24463 | 0 | 0 |
T12 | 42858 | 24428 | 0 | 0 |
T16 | 1672 | 1019 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 9688787 | 5016816 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9688787 | 5016816 | 0 | 0 |
T1 | 5814 | 531 | 0 | 0 |
T2 | 5816 | 532 | 0 | 0 |
T3 | 6071 | 4821 | 0 | 0 |
T4 | 144692 | 60352 | 0 | 0 |
T5 | 3051 | 2386 | 0 | 0 |
T6 | 6091 | 4815 | 0 | 0 |
T7 | 8436 | 7772 | 0 | 0 |
T11 | 37385 | 24071 | 0 | 0 |
T12 | 42858 | 23906 | 0 | 0 |
T16 | 1672 | 1003 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 19377952 | 10334606 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19377952 | 10334606 | 0 | 0 |
T1 | 11630 | 1351 | 0 | 0 |
T2 | 11629 | 1351 | 0 | 0 |
T3 | 12142 | 9737 | 0 | 0 |
T4 | 289353 | 126180 | 0 | 0 |
T5 | 6102 | 4806 | 0 | 0 |
T6 | 12182 | 9724 | 0 | 0 |
T7 | 16874 | 15579 | 0 | 0 |
T11 | 74756 | 49080 | 0 | 0 |
T12 | 85715 | 48993 | 0 | 0 |
T16 | 3344 | 2039 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 19377952 | 10075491 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19377952 | 10075491 | 0 | 0 |
T1 | 11630 | 1095 | 0 | 0 |
T2 | 11629 | 1095 | 0 | 0 |
T3 | 12142 | 9657 | 0 | 0 |
T4 | 289353 | 121620 | 0 | 0 |
T5 | 6102 | 4774 | 0 | 0 |
T6 | 12182 | 9644 | 0 | 0 |
T7 | 16874 | 15547 | 0 | 0 |
T11 | 74756 | 48296 | 0 | 0 |
T12 | 85715 | 47949 | 0 | 0 |
T16 | 3344 | 2007 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 40371236 | 20776548 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 40371236 | 20776548 | 0 | 0 |
T1 | 24236 | 2288 | 0 | 0 |
T2 | 24218 | 2292 | 0 | 0 |
T3 | 25292 | 20061 | 0 | 0 |
T4 | 602841 | 247639 | 0 | 0 |
T5 | 12713 | 9947 | 0 | 0 |
T6 | 25381 | 19960 | 0 | 0 |
T7 | 35152 | 32389 | 0 | 0 |
T11 | 155757 | 99728 | 0 | 0 |
T12 | 178578 | 99204 | 0 | 0 |
T16 | 6969 | 4183 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 9688787 | 5090836 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9688787 | 5090836 | 0 | 0 |
T1 | 5814 | 669 | 0 | 0 |
T2 | 5816 | 670 | 0 | 0 |
T3 | 6071 | 4847 | 0 | 0 |
T4 | 144692 | 61163 | 0 | 0 |
T5 | 3051 | 2402 | 0 | 0 |
T6 | 6091 | 4822 | 0 | 0 |
T7 | 8436 | 7788 | 0 | 0 |
T11 | 37385 | 24230 | 0 | 0 |
T12 | 42858 | 24249 | 0 | 0 |
T16 | 1672 | 1019 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 9688787 | 4927172 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9688787 | 4927172 | 0 | 0 |
T1 | 5814 | 541 | 0 | 0 |
T2 | 5816 | 542 | 0 | 0 |
T3 | 6071 | 4821 | 0 | 0 |
T4 | 144692 | 57483 | 0 | 0 |
T5 | 3051 | 2192 | 0 | 0 |
T6 | 6091 | 4815 | 0 | 0 |
T7 | 8436 | 7307 | 0 | 0 |
T11 | 37385 | 24071 | 0 | 0 |
T12 | 42858 | 23906 | 0 | 0 |
T16 | 1672 | 1003 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 38754767 | 19819654 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 38754767 | 19819654 | 0 | 0 |
T1 | 23246 | 2196 | 0 | 0 |
T2 | 23267 | 2198 | 0 | 0 |
T3 | 24280 | 19316 | 0 | 0 |
T4 | 578772 | 226884 | 0 | 0 |
T5 | 12205 | 8442 | 0 | 0 |
T6 | 24369 | 19297 | 0 | 0 |
T7 | 33746 | 26949 | 0 | 0 |
T11 | 149499 | 96642 | 0 | 0 |
T12 | 171461 | 95954 | 0 | 0 |
T16 | 6691 | 4015 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 19377970 | 9896648 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19377970 | 9896648 | 0 | 0 |
T1 | 11627 | 1095 | 0 | 0 |
T2 | 11629 | 1095 | 0 | 0 |
T3 | 12142 | 9403 | 0 | 0 |
T4 | 289375 | 117364 | 0 | 0 |
T5 | 6101 | 4299 | 0 | 0 |
T6 | 12182 | 9644 | 0 | 0 |
T7 | 16874 | 13640 | 0 | 0 |
T11 | 74770 | 48306 | 0 | 0 |
T12 | 85716 | 47950 | 0 | 0 |
T16 | 3344 | 2007 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 19377952 | 9882946 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19377952 | 9882946 | 0 | 0 |
T1 | 11630 | 1095 | 0 | 0 |
T2 | 11629 | 1095 | 0 | 0 |
T3 | 12142 | 9657 | 0 | 0 |
T4 | 289353 | 112308 | 0 | 0 |
T5 | 6102 | 4331 | 0 | 0 |
T6 | 12182 | 9389 | 0 | 0 |
T7 | 16874 | 13178 | 0 | 0 |
T11 | 74756 | 48296 | 0 | 0 |
T12 | 85715 | 47949 | 0 | 0 |
T16 | 3344 | 2007 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 1223397 | 610807 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1223397 | 610807 | 0 | 0 |
T1 | 729 | 57 | 0 | 0 |
T2 | 729 | 58 | 0 | 0 |
T3 | 757 | 598 | 0 | 0 |
T4 | 18500 | 7103 | 0 | 0 |
T5 | 380 | 267 | 0 | 0 |
T6 | 760 | 598 | 0 | 0 |
T7 | 1053 | 804 | 0 | 0 |
T11 | 4786 | 3064 | 0 | 0 |
T12 | 5415 | 2985 | 0 | 0 |
T16 | 207 | 124 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 9688787 | 4932001 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9688787 | 4932001 | 0 | 0 |
T1 | 5814 | 541 | 0 | 0 |
T2 | 5816 | 542 | 0 | 0 |
T3 | 6071 | 4821 | 0 | 0 |
T4 | 144692 | 58618 | 0 | 0 |
T5 | 3051 | 2080 | 0 | 0 |
T6 | 6091 | 4815 | 0 | 0 |
T7 | 8436 | 6937 | 0 | 0 |
T11 | 37385 | 24071 | 0 | 0 |
T12 | 42858 | 23906 | 0 | 0 |
T16 | 1672 | 1003 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 9688787 | 4921681 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9688787 | 4921681 | 0 | 0 |
T1 | 5814 | 541 | 0 | 0 |
T2 | 5816 | 542 | 0 | 0 |
T3 | 6071 | 4719 | 0 | 0 |
T4 | 144692 | 56919 | 0 | 0 |
T5 | 3051 | 2120 | 0 | 0 |
T6 | 6091 | 4700 | 0 | 0 |
T7 | 8436 | 7164 | 0 | 0 |
T11 | 37385 | 24071 | 0 | 0 |
T12 | 42858 | 23906 | 0 | 0 |
T16 | 1672 | 1003 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 9688787 | 4930009 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9688787 | 4930009 | 0 | 0 |
T1 | 5814 | 541 | 0 | 0 |
T2 | 5816 | 542 | 0 | 0 |
T3 | 6071 | 4722 | 0 | 0 |
T4 | 144692 | 57297 | 0 | 0 |
T5 | 3051 | 2144 | 0 | 0 |
T6 | 6091 | 4713 | 0 | 0 |
T7 | 8436 | 6373 | 0 | 0 |
T11 | 37385 | 24071 | 0 | 0 |
T12 | 42858 | 23906 | 0 | 0 |
T16 | 1672 | 1003 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 1223397 | 744228 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1223397 | 744228 | 0 | 0 |
T1 | 729 | 89 | 0 | 0 |
T2 | 729 | 90 | 0 | 0 |
T3 | 757 | 634 | 0 | 0 |
T4 | 18500 | 11136 | 0 | 0 |
T5 | 380 | 301 | 0 | 0 |
T6 | 760 | 640 | 0 | 0 |
T7 | 1053 | 974 | 0 | 0 |
T11 | 4786 | 3553 | 0 | 0 |
T12 | 5415 | 3485 | 0 | 0 |
T16 | 207 | 128 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 1223397 | 730573 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1223397 | 730573 | 0 | 0 |
T1 | 729 | 73 | 0 | 0 |
T2 | 729 | 74 | 0 | 0 |
T3 | 757 | 630 | 0 | 0 |
T4 | 18500 | 10916 | 0 | 0 |
T5 | 380 | 299 | 0 | 0 |
T6 | 760 | 636 | 0 | 0 |
T7 | 1053 | 972 | 0 | 0 |
T11 | 4786 | 3515 | 0 | 0 |
T12 | 5415 | 3427 | 0 | 0 |
T16 | 207 | 126 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |