Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	9345780	8131	0	0
alert_regwen_rd_A	9345780	5484	0	0
cpu_regwen_rd_A	9345780	5532	0	0
sw_rst_ctrl_n_0_rd_A	9345780	8252	0	0
sw_rst_ctrl_n_1_rd_A	9345780	8348	0	0
sw_rst_ctrl_n_2_rd_A	9345780	8185	0	0
sw_rst_ctrl_n_3_rd_A	9345780	8101	0	0
sw_rst_ctrl_n_4_rd_A	9345780	8075	0	0
sw_rst_ctrl_n_5_rd_A	9345780	8315	0	0
sw_rst_ctrl_n_6_rd_A	9345780	7877	0	0
sw_rst_ctrl_n_7_rd_A	9345780	8190	0	0
sw_rst_regwen_0_rd_A	9345780	5739	0	0
sw_rst_regwen_1_rd_A	9345780	5904	0	0
sw_rst_regwen_2_rd_A	9345780	5637	0	0
sw_rst_regwen_3_rd_A	9345780	5923	0	0
sw_rst_regwen_4_rd_A	9345780	5651	0	0
sw_rst_regwen_5_rd_A	9345780	5888	0	0
sw_rst_regwen_6_rd_A	9345780	6115	0	0
sw_rst_regwen_7_rd_A	9345780	5753	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9345780	8131	0	0
T10	4742	279	0	0
T66	9127	1	0	0
T69	4811	168	0	0
T70	5330	181	0	0
T74	21565	1	0	0
T85	2163	88	0	0
T86	2763	234	0	0
T87	3674	114	0	0
T88	0	453	0	0
T90	2409	0	0	0
T91	1693	0	0	0
T119	0	12	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9345780	5484	0	0
T8	1638	1	0	0
T68	11321	32	0	0
T74	21565	90	0	0
T86	2763	0	0	0
T87	3674	0	0	0
T91	1693	0	0	0
T92	1793	7	0	0
T96	2280	0	0	0
T98	2254	16	0	0
T100	0	68	0	0
T112	3578	22	0	0
T117	0	74	0	0
T120	0	73	0	0
T121	0	16	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9345780	5532	0	0
T8	1638	7	0	0
T68	11321	26	0	0
T74	21565	75	0	0
T86	2763	0	0	0
T87	3674	0	0	0
T91	1693	0	0	0
T92	1793	6	0	0
T96	2280	0	0	0
T98	2254	4	0	0
T100	0	83	0	0
T101	0	4	0	0
T111	3207	32	0	0
T112	0	27	0	0
T122	0	6	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9345780	8252	0	0
T3	5780	16	0	0
T4	113252	0	0	0
T5	3032	0	0	0
T6	5804	7	0	0
T7	8345	0	0	0
T74	21565	2	0	0
T86	2763	0	0	0
T87	3674	0	0	0
T91	1693	0	0	0
T100	0	59	0	0
T106	0	9	0	0
T111	3207	1	0	0
T112	0	10	0	0
T121	0	11	0	0
T123	0	16	0	0
T124	0	1	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9345780	8348	0	0
T3	5780	13	0	0
T4	113252	0	0	0
T5	3032	0	0	0
T6	5804	12	0	0
T7	8345	0	0	0
T88	4635	0	0	0
T89	4162	0	0	0
T94	10162	0	0	0
T100	0	95	0	0
T112	3578	37	0	0
T119	4185	0	0	0
T121	0	18	0	0
T123	0	9	0	0
T124	0	7	0	0
T125	0	19	0	0
T126	0	16	0	0
T127	0	8	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9345780	8185	0	0
T3	5780	9	0	0
T4	113252	0	0	0
T5	3032	0	0	0
T6	5804	14	0	0
T7	8345	0	0	0
T74	21565	3	0	0
T86	2763	0	0	0
T87	3674	0	0	0
T91	1693	0	0	0
T100	0	93	0	0
T111	3207	29	0	0
T112	0	16	0	0
T117	0	6	0	0
T120	0	3	0	0
T121	0	6	0	0
T123	0	26	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9345780	8101	0	0
T3	5780	17	0	0
T4	113252	0	0	0
T5	3032	0	0	0
T6	5804	19	0	0
T7	8345	0	0	0
T74	21565	1	0	0
T86	2763	0	0	0
T87	3674	0	0	0
T91	1693	0	0	0
T100	0	84	0	0
T111	3207	16	0	0
T112	0	36	0	0
T120	0	2	0	0
T121	0	14	0	0
T123	0	18	0	0
T124	0	25	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9345780	8075	0	0
T3	5780	14	0	0
T4	113252	0	0	0
T5	3032	0	0	0
T6	5804	17	0	0
T7	8345	0	0	0
T88	4635	0	0	0
T94	10162	0	0	0
T100	0	93	0	0
T111	3207	21	0	0
T112	3578	22	0	0
T119	4185	0	0	0
T121	0	8	0	0
T123	0	9	0	0
T124	0	16	0	0
T125	0	17	0	0
T128	0	51	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9345780	8315	0	0
T3	5780	14	0	0
T4	113252	0	0	0
T5	3032	0	0	0
T6	5804	3	0	0
T7	8345	0	0	0
T68	11321	3	0	0
T88	4635	0	0	0
T94	10162	0	0	0
T100	0	110	0	0
T112	3578	3	0	0
T116	0	7	0	0
T119	4185	0	0	0
T121	0	7	0	0
T123	0	29	0	0
T124	0	1	0	0
T129	0	8	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9345780	7877	0	0
T3	5780	6	0	0
T4	113252	0	0	0
T5	3032	0	0	0
T6	5804	20	0	0
T7	8345	0	0	0
T88	4635	0	0	0
T89	4162	0	0	0
T94	10162	0	0	0
T100	0	93	0	0
T106	0	4	0	0
T112	3578	34	0	0
T119	4185	0	0	0
T120	0	10	0	0
T121	0	11	0	0
T123	0	15	0	0
T124	0	32	0	0
T128	0	11	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9345780	8190	0	0
T3	5780	15	0	0
T4	113252	0	0	0
T5	3032	0	0	0
T6	5804	8	0	0
T7	8345	0	0	0
T68	11321	2	0	0
T88	4635	0	0	0
T100	0	70	0	0
T111	3207	5	0	0
T112	3578	27	0	0
T119	4185	0	0	0
T120	0	1	0	0
T121	0	3	0	0
T123	0	15	0	0
T124	0	4	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9345780	5739	0	0
T3	5780	15	0	0
T4	113252	0	0	0
T5	3032	0	0	0
T6	5804	13	0	0
T7	8345	0	0	0
T68	11321	47	0	0
T74	21565	70	0	0
T92	1793	9	0	0
T98	2254	15	0	0
T100	0	114	0	0
T101	0	10	0	0
T111	3207	8	0	0
T112	0	11	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9345780	5904	0	0
T3	5780	8	0	0
T4	113252	0	0	0
T5	3032	0	0	0
T6	5804	7	0	0
T7	8345	0	0	0
T8	1638	3	0	0
T68	11321	37	0	0
T74	0	70	0	0
T92	1793	6	0	0
T98	2254	11	0	0
T100	0	90	0	0
T111	3207	7	0	0
T112	0	47	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9345780	5637	0	0
T3	5780	6	0	0
T4	113252	0	0	0
T5	3032	0	0	0
T6	5804	10	0	0
T7	8345	0	0	0
T8	1638	6	0	0
T68	11321	38	0	0
T74	21565	62	0	0
T86	2763	0	0	0
T98	2254	13	0	0
T100	0	99	0	0
T101	0	8	0	0
T112	0	11	0	0
T122	0	3	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9345780	5923	0	0
T3	5780	9	0	0
T4	113252	0	0	0
T5	3032	0	0	0
T6	5804	9	0	0
T7	8345	0	0	0
T8	1638	9	0	0
T68	11321	32	0	0
T74	21565	65	0	0
T92	1793	4	0	0
T98	2254	6	0	0
T100	0	82	0	0
T112	0	31	0	0
T122	0	6	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9345780	5651	0	0
T3	5780	7	0	0
T4	113252	0	0	0
T5	3032	0	0	0
T6	5804	8	0	0
T7	8345	0	0	0
T8	1638	4	0	0
T68	11321	31	0	0
T74	21565	87	0	0
T92	1793	1	0	0
T98	2254	9	0	0
T100	0	88	0	0
T112	0	49	0	0
T122	0	7	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9345780	5888	0	0
T3	5780	9	0	0
T4	113252	0	0	0
T5	3032	0	0	0
T6	5804	1	0	0
T7	8345	0	0	0
T8	1638	2	0	0
T68	11321	41	0	0
T74	0	71	0	0
T92	1793	8	0	0
T98	2254	5	0	0
T100	0	79	0	0
T111	3207	40	0	0
T112	0	11	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9345780	6115	0	0
T3	5780	11	0	0
T4	113252	0	0	0
T5	3032	0	0	0
T6	5804	9	0	0
T7	8345	0	0	0
T8	1638	7	0	0
T68	11321	31	0	0
T74	0	92	0	0
T92	1793	6	0	0
T98	2254	5	0	0
T100	0	83	0	0
T111	3207	23	0	0
T112	0	10	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9345780	5753	0	0
T3	5780	3	0	0
T4	113252	0	0	0
T5	3032	0	0	0
T6	5804	5	0	0
T7	8345	0	0	0
T8	1638	3	0	0
T68	11321	39	0	0
T74	0	82	0	0
T92	1793	8	0	0
T98	2254	2	0	0
T100	0	98	0	0
T111	3207	10	0	0
T112	0	20	0	0