Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	8576729	10131	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	8576729	93427	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	8576729	5022291	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	8576729	149038	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	8576729	10131	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	8576729	93427	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	8576729	5022291	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	8576729	149038	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8576729	10131	0	0
T3	5780	4	0	0
T4	113252	260	0	0
T5	3032	0	0	0
T6	5804	4	0	0
T7	8345	0	0	0
T11	32922	44	0	0
T12	37145	29	0	0
T13	4729	0	0	0
T14	68706	60	0	0
T16	1653	0	0	0
T17	0	4	0	0
T18	0	4	0	0
T27	0	75	0	0
T28	0	4	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8576729	93427	0	0
T3	5780	37	0	0
T4	113252	2365	0	0
T5	3032	0	0	0
T6	5804	38	0	0
T7	8345	0	0	0
T11	32922	407	0	0
T12	37145	266	0	0
T13	4729	0	0	0
T14	68706	541	0	0
T16	1653	0	0	0
T17	0	38	0	0
T18	0	38	0	0
T27	0	700	0	0
T28	0	38	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8576729	5022291	0	0
T1	5462	564	0	0
T2	5461	565	0	0
T3	5780	4827	0	0
T4	113252	60257	0	0
T5	3032	2389	0	0
T6	5804	4805	0	0
T7	8345	7775	0	0
T11	32922	24067	0	0
T12	37145	23927	0	0
T16	1653	1005	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8576729	149038	0	0
T3	5780	51	0	0
T4	113252	3834	0	0
T5	3032	0	0	0
T6	5804	71	0	0
T7	8345	0	0	0
T11	32922	640	0	0
T12	37145	445	0	0
T13	4729	0	0	0
T14	68706	869	0	0
T16	1653	0	0	0
T17	0	61	0	0
T18	0	67	0	0
T27	0	1127	0	0
T28	0	57	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8576729	10131	0	0
T3	5780	4	0	0
T4	113252	260	0	0
T5	3032	0	0	0
T6	5804	4	0	0
T7	8345	0	0	0
T11	32922	44	0	0
T12	37145	29	0	0
T13	4729	0	0	0
T14	68706	60	0	0
T16	1653	0	0	0
T17	0	4	0	0
T18	0	4	0	0
T27	0	75	0	0
T28	0	4	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8576729	93427	0	0
T3	5780	37	0	0
T4	113252	2365	0	0
T5	3032	0	0	0
T6	5804	38	0	0
T7	8345	0	0	0
T11	32922	407	0	0
T12	37145	266	0	0
T13	4729	0	0	0
T14	68706	541	0	0
T16	1653	0	0	0
T17	0	38	0	0
T18	0	38	0	0
T27	0	700	0	0
T28	0	38	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8576729	5022291	0	0
T1	5462	564	0	0
T2	5461	565	0	0
T3	5780	4827	0	0
T4	113252	60257	0	0
T5	3032	2389	0	0
T6	5804	4805	0	0
T7	8345	7775	0	0
T11	32922	24067	0	0
T12	37145	23927	0	0
T16	1653	1005	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8576729	149038	0	0
T3	5780	51	0	0
T4	113252	3834	0	0
T5	3032	0	0	0
T6	5804	71	0	0
T7	8345	0	0	0
T11	32922	640	0	0
T12	37145	445	0	0
T13	4729	0	0	0
T14	68706	869	0	0
T16	1653	0	0	0
T17	0	61	0	0
T18	0	67	0	0
T27	0	1127	0	0
T28	0	57	0	0