Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T6
0	1	Covered	T4,T6,T11
1	0	Covered	T3,T4,T11

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T3,T4,T6
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	40371236	6490	0	0
CascadeEffAonToRstPorAboveRise_A	40371236	6490	0	0
CascadeEffAonToRstPorIoAboveFall_A	38754767	6490	0	0
CascadeEffAonToRstPorIoAboveRise_A	38754767	6490	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	19377970	6490	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	19377970	6490	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	9688787	6490	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	9688787	6490	0	0
CascadeEffAonToRstPorUcbAboveFall_A	19377952	6490	0	0
CascadeEffAonToRstPorUcbAboveRise_A	19377952	6490	0	0
CascadeLcToLcAboveFall_A	40371236	16621	0	0
CascadeLcToLcAboveRise_A	40371236	16621	0	0
CascadeLcToLcAonAboveFall_A	1223397	16621	0	0
CascadeLcToLcAonAboveRise_A	1223397	16621	0	0
CascadeLcToLcShadowedAboveFall_A	40371236	16621	0	0
CascadeLcToLcShadowedAboveRise_A	40371236	16621	0	0
CascadePorToAonAboveFall_A	1223397	5367	0	0
CascadeSysToSysAboveFall_A	40371236	16621	0	0
CascadeSysToSysAboveRise_A	40371236	16621	0	0
ScanRstToAonRise_A	1223397	155	0	0
StablePorToAonRise_A	1223397	6490	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	8576729	16621	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	8576729	16621	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	8576729	16621	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	8576729	16621	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	9688787	16621	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	9688787	16621	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	8576729	16621	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	8576729	16621	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	8576729	16621	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	8576729	16621	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40371236	6490	0	0
T1	24236	8	0	0
T2	24218	8	0	0
T3	25292	2	0	0
T4	602841	110	0	0
T5	12713	1	0	0
T6	25381	2	0	0
T7	35152	1	0	0
T11	155757	19	0	0
T12	178578	29	0	0
T16	6969	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40371236	6490	0	0
T1	24236	8	0	0
T2	24218	8	0	0
T3	25292	2	0	0
T4	602841	110	0	0
T5	12713	1	0	0
T6	25381	2	0	0
T7	35152	1	0	0
T11	155757	19	0	0
T12	178578	29	0	0
T16	6969	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38754767	6490	0	0
T1	23246	8	0	0
T2	23267	8	0	0
T3	24280	2	0	0
T4	578772	110	0	0
T5	12205	1	0	0
T6	24369	2	0	0
T7	33746	1	0	0
T11	149499	19	0	0
T12	171461	29	0	0
T16	6691	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38754767	6490	0	0
T1	23246	8	0	0
T2	23267	8	0	0
T3	24280	2	0	0
T4	578772	110	0	0
T5	12205	1	0	0
T6	24369	2	0	0
T7	33746	1	0	0
T11	149499	19	0	0
T12	171461	29	0	0
T16	6691	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377970	6490	0	0
T1	11627	8	0	0
T2	11629	8	0	0
T3	12142	2	0	0
T4	289375	110	0	0
T5	6101	1	0	0
T6	12182	2	0	0
T7	16874	1	0	0
T11	74770	19	0	0
T12	85716	29	0	0
T16	3344	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377970	6490	0	0
T1	11627	8	0	0
T2	11629	8	0	0
T3	12142	2	0	0
T4	289375	110	0	0
T5	6101	1	0	0
T6	12182	2	0	0
T7	16874	1	0	0
T11	74770	19	0	0
T12	85716	29	0	0
T16	3344	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9688787	6490	0	0
T1	5814	8	0	0
T2	5816	8	0	0
T3	6071	2	0	0
T4	144692	110	0	0
T5	3051	1	0	0
T6	6091	2	0	0
T7	8436	1	0	0
T11	37385	19	0	0
T12	42858	29	0	0
T16	1672	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9688787	6490	0	0
T1	5814	8	0	0
T2	5816	8	0	0
T3	6071	2	0	0
T4	144692	110	0	0
T5	3051	1	0	0
T6	6091	2	0	0
T7	8436	1	0	0
T11	37385	19	0	0
T12	42858	29	0	0
T16	1672	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377952	6490	0	0
T1	11630	8	0	0
T2	11629	8	0	0
T3	12142	2	0	0
T4	289353	110	0	0
T5	6102	1	0	0
T6	12182	2	0	0
T7	16874	1	0	0
T11	74756	19	0	0
T12	85715	29	0	0
T16	3344	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377952	6490	0	0
T1	11630	8	0	0
T2	11629	8	0	0
T3	12142	2	0	0
T4	289353	110	0	0
T5	6102	1	0	0
T6	12182	2	0	0
T7	16874	1	0	0
T11	74756	19	0	0
T12	85715	29	0	0
T16	3344	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40371236	16621	0	0
T1	24236	8	0	0
T2	24218	8	0	0
T3	25292	6	0	0
T4	602841	370	0	0
T5	12713	1	0	0
T6	25381	6	0	0
T7	35152	1	0	0
T11	155757	63	0	0
T12	178578	58	0	0
T16	6969	1	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40371236	16621	0	0
T1	24236	8	0	0
T2	24218	8	0	0
T3	25292	6	0	0
T4	602841	370	0	0
T5	12713	1	0	0
T6	25381	6	0	0
T7	35152	1	0	0
T11	155757	63	0	0
T12	178578	58	0	0
T16	6969	1	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1223397	16621	0	0
T1	729	8	0	0
T2	729	8	0	0
T3	757	6	0	0
T4	18500	370	0	0
T5	380	1	0	0
T6	760	6	0	0
T7	1053	1	0	0
T11	4786	63	0	0
T12	5415	58	0	0
T16	207	1	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1223397	16621	0	0
T1	729	8	0	0
T2	729	8	0	0
T3	757	6	0	0
T4	18500	370	0	0
T5	380	1	0	0
T6	760	6	0	0
T7	1053	1	0	0
T11	4786	63	0	0
T12	5415	58	0	0
T16	207	1	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40371236	16621	0	0
T1	24236	8	0	0
T2	24218	8	0	0
T3	25292	6	0	0
T4	602841	370	0	0
T5	12713	1	0	0
T6	25381	6	0	0
T7	35152	1	0	0
T11	155757	63	0	0
T12	178578	58	0	0
T16	6969	1	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40371236	16621	0	0
T1	24236	8	0	0
T2	24218	8	0	0
T3	25292	6	0	0
T4	602841	370	0	0
T5	12713	1	0	0
T6	25381	6	0	0
T7	35152	1	0	0
T11	155757	63	0	0
T12	178578	58	0	0
T16	6969	1	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1223397	5367	0	0
T1	729	8	0	0
T2	729	8	0	0
T3	757	1	0	0
T4	18500	64	0	0
T5	380	1	0	0
T6	760	1	0	0
T7	1053	1	0	0
T11	4786	10	0	0
T12	5415	17	0	0
T16	207	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40371236	16621	0	0
T1	24236	8	0	0
T2	24218	8	0	0
T3	25292	6	0	0
T4	602841	370	0	0
T5	12713	1	0	0
T6	25381	6	0	0
T7	35152	1	0	0
T11	155757	63	0	0
T12	178578	58	0	0
T16	6969	1	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40371236	16621	0	0
T1	24236	8	0	0
T2	24218	8	0	0
T3	25292	6	0	0
T4	602841	370	0	0
T5	12713	1	0	0
T6	25381	6	0	0
T7	35152	1	0	0
T11	155757	63	0	0
T12	178578	58	0	0
T16	6969	1	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1223397	155	0	0
T4	18500	7	0	0
T5	380	0	0	0
T6	760	1	0	0
T7	1053	0	0	0
T11	4786	1	0	0
T12	5415	2	0	0
T13	602	0	0	0
T14	9857	1	0	0
T15	669	0	0	0
T16	207	0	0	0
T29	0	3	0	0
T41	0	2	0	0
T42	0	4	0	0
T83	0	6	0	0
T130	0	2	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1223397	6490	0	0
T1	729	8	0	0
T2	729	8	0	0
T3	757	2	0	0
T4	18500	110	0	0
T5	380	1	0	0
T6	760	2	0	0
T7	1053	1	0	0
T11	4786	19	0	0
T12	5415	29	0	0
T16	207	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8576729	16621	0	0
T1	5462	8	0	0
T2	5461	8	0	0
T3	5780	6	0	0
T4	113252	370	0	0
T5	3032	1	0	0
T6	5804	6	0	0
T7	8345	1	0	0
T11	32922	63	0	0
T12	37145	58	0	0
T16	1653	1	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8576729	16621	0	0
T1	5462	8	0	0
T2	5461	8	0	0
T3	5780	6	0	0
T4	113252	370	0	0
T5	3032	1	0	0
T6	5804	6	0	0
T7	8345	1	0	0
T11	32922	63	0	0
T12	37145	58	0	0
T16	1653	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8576729	16621	0	0
T1	5462	8	0	0
T2	5461	8	0	0
T3	5780	6	0	0
T4	113252	370	0	0
T5	3032	1	0	0
T6	5804	6	0	0
T7	8345	1	0	0
T11	32922	63	0	0
T12	37145	58	0	0
T16	1653	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8576729	16621	0	0
T1	5462	8	0	0
T2	5461	8	0	0
T3	5780	6	0	0
T4	113252	370	0	0
T5	3032	1	0	0
T6	5804	6	0	0
T7	8345	1	0	0
T11	32922	63	0	0
T12	37145	58	0	0
T16	1653	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9688787	16621	0	0
T1	5814	8	0	0
T2	5816	8	0	0
T3	6071	6	0	0
T4	144692	370	0	0
T5	3051	1	0	0
T6	6091	6	0	0
T7	8436	1	0	0
T11	37385	63	0	0
T12	42858	58	0	0
T16	1672	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9688787	16621	0	0
T1	5814	8	0	0
T2	5816	8	0	0
T3	6071	6	0	0
T4	144692	370	0	0
T5	3051	1	0	0
T6	6091	6	0	0
T7	8436	1	0	0
T11	37385	63	0	0
T12	42858	58	0	0
T16	1672	1	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8576729	16621	0	0
T1	5462	8	0	0
T2	5461	8	0	0
T3	5780	6	0	0
T4	113252	370	0	0
T5	3032	1	0	0
T6	5804	6	0	0
T7	8345	1	0	0
T11	32922	63	0	0
T12	37145	58	0	0
T16	1653	1	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8576729	16621	0	0
T1	5462	8	0	0
T2	5461	8	0	0
T3	5780	6	0	0
T4	113252	370	0	0
T5	3032	1	0	0
T6	5804	6	0	0
T7	8345	1	0	0
T11	32922	63	0	0
T12	37145	58	0	0
T16	1653	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8576729	16621	0	0
T1	5462	8	0	0
T2	5461	8	0	0
T3	5780	6	0	0
T4	113252	370	0	0
T5	3032	1	0	0
T6	5804	6	0	0
T7	8345	1	0	0
T11	32922	63	0	0
T12	37145	58	0	0
T16	1653	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8576729	16621	0	0
T1	5462	8	0	0
T2	5461	8	0	0
T3	5780	6	0	0
T4	113252	370	0	0
T5	3032	1	0	0
T6	5804	6	0	0
T7	8345	1	0	0
T11	32922	63	0	0
T12	37145	58	0	0
T16	1653	1	0	0