Group : rstmgr_env_pkg::rstmgr_sw_rst_cg_wrap::sw_rst_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : rstmgr_env_pkg::rstmgr_sw_rst_cg_wrap::sw_rst_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

8 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
sw_rst_ctrl_n[0] 100.00 1 100 1 64 64
sw_rst_ctrl_n[1] 100.00 1 100 1 64 64
sw_rst_ctrl_n[2] 100.00 1 100 1 64 64
sw_rst_ctrl_n[3] 100.00 1 100 1 64 64
sw_rst_ctrl_n[4] 100.00 1 100 1 64 64
sw_rst_ctrl_n[5] 100.00 1 100 1 64 64
sw_rst_ctrl_n[6] 100.00 1 100 1 64 64
sw_rst_ctrl_n[7] 100.00 1 100 1 64 64




Group Instance : sw_rst_ctrl_n[0]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sw_rst_ctrl_n[0]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 4 0 4 100.00


Variables for Group Instance sw_rst_ctrl_n[0]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable 2 0 2 100.00 100 1 1 2
enable_cp 2 0 2 100.00 100 1 1 2
rst_n 2 0 2 100.00 100 1 1 2
rst_n_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sw_rst_ctrl_n[0]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sw_rst_cross 4 0 4 100.00 100 1 1 0



Group Instance : sw_rst_ctrl_n[1]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sw_rst_ctrl_n[1]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 4 0 4 100.00


Variables for Group Instance sw_rst_ctrl_n[1]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable 2 0 2 100.00 100 1 1 2
enable_cp 2 0 2 100.00 100 1 1 2
rst_n 2 0 2 100.00 100 1 1 2
rst_n_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sw_rst_ctrl_n[1]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sw_rst_cross 4 0 4 100.00 100 1 1 0



Group Instance : sw_rst_ctrl_n[2]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sw_rst_ctrl_n[2]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 4 0 4 100.00


Variables for Group Instance sw_rst_ctrl_n[2]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable 2 0 2 100.00 100 1 1 2
enable_cp 2 0 2 100.00 100 1 1 2
rst_n 2 0 2 100.00 100 1 1 2
rst_n_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sw_rst_ctrl_n[2]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sw_rst_cross 4 0 4 100.00 100 1 1 0



Group Instance : sw_rst_ctrl_n[3]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sw_rst_ctrl_n[3]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 4 0 4 100.00


Variables for Group Instance sw_rst_ctrl_n[3]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable 2 0 2 100.00 100 1 1 2
enable_cp 2 0 2 100.00 100 1 1 2
rst_n 2 0 2 100.00 100 1 1 2
rst_n_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sw_rst_ctrl_n[3]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sw_rst_cross 4 0 4 100.00 100 1 1 0



Group Instance : sw_rst_ctrl_n[4]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sw_rst_ctrl_n[4]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 4 0 4 100.00


Variables for Group Instance sw_rst_ctrl_n[4]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable 2 0 2 100.00 100 1 1 2
enable_cp 2 0 2 100.00 100 1 1 2
rst_n 2 0 2 100.00 100 1 1 2
rst_n_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sw_rst_ctrl_n[4]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sw_rst_cross 4 0 4 100.00 100 1 1 0



Group Instance : sw_rst_ctrl_n[5]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sw_rst_ctrl_n[5]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 4 0 4 100.00


Variables for Group Instance sw_rst_ctrl_n[5]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable 2 0 2 100.00 100 1 1 2
enable_cp 2 0 2 100.00 100 1 1 2
rst_n 2 0 2 100.00 100 1 1 2
rst_n_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sw_rst_ctrl_n[5]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sw_rst_cross 4 0 4 100.00 100 1 1 0



Group Instance : sw_rst_ctrl_n[6]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sw_rst_ctrl_n[6]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 4 0 4 100.00


Variables for Group Instance sw_rst_ctrl_n[6]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable 2 0 2 100.00 100 1 1 2
enable_cp 2 0 2 100.00 100 1 1 2
rst_n 2 0 2 100.00 100 1 1 2
rst_n_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sw_rst_ctrl_n[6]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sw_rst_cross 4 0 4 100.00 100 1 1 0



Group Instance : sw_rst_ctrl_n[7]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sw_rst_ctrl_n[7]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 4 0 4 100.00


Variables for Group Instance sw_rst_ctrl_n[7]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable 2 0 2 100.00 100 1 1 2
enable_cp 2 0 2 100.00 100 1 1 2
rst_n 2 0 2 100.00 100 1 1 2
rst_n_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sw_rst_ctrl_n[7]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sw_rst_cross 4 0 4 100.00 100 1 1 0


Summary for Variable enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1600 1 T6 32 T25 32 T48 32
auto[1] 4224 1 T3 3 T6 31 T9 101



Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1600 1 T6 32 T25 32 T48 32
auto[1] 4224 1 T3 3 T6 31 T9 101



Summary for Variable rst_n

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1677 1 T6 19 T9 37 T11 1
auto[1] 4147 1 T3 3 T6 44 T9 64



Summary for Variable rst_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1677 1 T6 19 T9 37 T11 1
auto[1] 4147 1 T3 3 T6 44 T9 64



Summary for Cross sw_rst_cross

Samples crossed: enable rst_n
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for sw_rst_cross

Bins
enablerst_nCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 400 1 T6 8 T25 8 T48 8
auto[0] auto[1] 1200 1 T6 24 T25 24 T48 24
auto[1] auto[0] 1277 1 T6 11 T9 37 T11 1
auto[1] auto[1] 2947 1 T3 3 T6 20 T9 64


Summary for Variable enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1469 1 T6 28 T11 3 T12 3
auto[1] 4113 1 T3 3 T6 35 T9 101



Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1469 1 T6 28 T11 3 T12 3
auto[1] 4113 1 T3 3 T6 35 T9 101



Summary for Variable rst_n

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1564 1 T6 18 T9 32 T11 1
auto[1] 4018 1 T3 3 T6 45 T9 69



Summary for Variable rst_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1564 1 T6 18 T9 32 T11 1
auto[1] 4018 1 T3 3 T6 45 T9 69



Summary for Cross sw_rst_cross

Samples crossed: enable rst_n
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for sw_rst_cross

Bins
enablerst_nCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 382 1 T6 7 T11 1 T12 2
auto[0] auto[1] 1087 1 T6 21 T11 2 T12 1
auto[1] auto[0] 1182 1 T6 11 T9 32 T25 10
auto[1] auto[1] 2931 1 T3 3 T6 24 T9 69


Summary for Variable enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1308 1 T3 3 T6 24 T11 3
auto[1] 4167 1 T6 39 T9 101 T12 3



Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1308 1 T3 3 T6 24 T11 3
auto[1] 4167 1 T6 39 T9 101 T12 3



Summary for Variable rst_n

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1567 1 T3 1 T6 16 T9 28
auto[1] 3908 1 T3 2 T6 47 T9 73



Summary for Variable rst_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1567 1 T3 1 T6 16 T9 28
auto[1] 3908 1 T3 2 T6 47 T9 73



Summary for Cross sw_rst_cross

Samples crossed: enable rst_n
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for sw_rst_cross

Bins
enablerst_nCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 359 1 T3 1 T6 6 T11 1
auto[0] auto[1] 949 1 T3 2 T6 18 T11 2
auto[1] auto[0] 1208 1 T6 10 T9 28 T25 8
auto[1] auto[1] 2959 1 T6 29 T9 73 T12 3


Summary for Variable enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1084 1 T6 20 T12 3 T25 20
auto[1] 4373 1 T3 3 T6 43 T9 101



Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1084 1 T6 20 T12 3 T25 20
auto[1] 4373 1 T3 3 T6 43 T9 101



Summary for Variable rst_n

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1508 1 T6 18 T9 31 T12 1
auto[1] 3949 1 T3 3 T6 45 T9 70



Summary for Variable rst_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1508 1 T6 18 T9 31 T12 1
auto[1] 3949 1 T3 3 T6 45 T9 70



Summary for Cross sw_rst_cross

Samples crossed: enable rst_n
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for sw_rst_cross

Bins
enablerst_nCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 295 1 T6 5 T12 1 T25 5
auto[0] auto[1] 789 1 T6 15 T12 2 T25 15
auto[1] auto[0] 1213 1 T6 13 T9 31 T25 6
auto[1] auto[1] 3160 1 T3 3 T6 30 T9 70


Summary for Variable enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 869 1 T3 3 T6 16 T12 3
auto[1] 4588 1 T6 47 T9 101 T11 3



Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 869 1 T3 3 T6 16 T12 3
auto[1] 4588 1 T6 47 T9 101 T11 3



Summary for Variable rst_n

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1526 1 T3 1 T6 19 T9 35
auto[1] 3931 1 T3 2 T6 44 T9 66



Summary for Variable rst_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1526 1 T3 1 T6 19 T9 35
auto[1] 3931 1 T3 2 T6 44 T9 66



Summary for Cross sw_rst_cross

Samples crossed: enable rst_n
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for sw_rst_cross

Bins
enablerst_nCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 235 1 T3 1 T6 4 T12 2
auto[0] auto[1] 634 1 T3 2 T6 12 T12 1
auto[1] auto[0] 1291 1 T6 15 T9 35 T11 1
auto[1] auto[1] 3297 1 T6 32 T9 66 T11 2


Summary for Variable enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 681 1 T3 3 T6 12 T11 3
auto[1] 4776 1 T6 51 T9 101 T12 3



Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 681 1 T3 3 T6 12 T11 3
auto[1] 4776 1 T6 51 T9 101 T12 3



Summary for Variable rst_n

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1481 1 T3 2 T6 21 T9 36
auto[1] 3976 1 T3 1 T6 42 T9 65



Summary for Variable rst_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1481 1 T3 2 T6 21 T9 36
auto[1] 3976 1 T3 1 T6 42 T9 65



Summary for Cross sw_rst_cross

Samples crossed: enable rst_n
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for sw_rst_cross

Bins
enablerst_nCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 195 1 T3 2 T6 3 T11 2
auto[0] auto[1] 486 1 T3 1 T6 9 T11 1
auto[1] auto[0] 1286 1 T6 18 T9 36 T12 1
auto[1] auto[1] 3490 1 T6 33 T9 65 T12 2


Summary for Variable enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 490 1 T3 3 T6 8 T11 3
auto[1] 4967 1 T6 55 T9 101 T25 44



Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 490 1 T3 3 T6 8 T11 3
auto[1] 4967 1 T6 55 T9 101 T25 44



Summary for Variable rst_n

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1545 1 T3 2 T6 18 T9 36
auto[1] 3912 1 T3 1 T6 45 T9 65



Summary for Variable rst_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1545 1 T3 2 T6 18 T9 36
auto[1] 3912 1 T3 1 T6 45 T9 65



Summary for Cross sw_rst_cross

Samples crossed: enable rst_n
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for sw_rst_cross

Bins
enablerst_nCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 146 1 T3 2 T6 2 T11 2
auto[0] auto[1] 344 1 T3 1 T6 6 T11 1
auto[1] auto[0] 1399 1 T6 16 T9 36 T25 14
auto[1] auto[1] 3568 1 T6 39 T9 65 T25 30


Summary for Variable enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 278 1 T6 4 T12 3 T25 4
auto[1] 5179 1 T3 3 T6 59 T9 101



Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 278 1 T6 4 T12 3 T25 4
auto[1] 5179 1 T3 3 T6 59 T9 101



Summary for Variable rst_n

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1539 1 T3 1 T6 17 T9 38
auto[1] 3918 1 T3 2 T6 46 T9 63



Summary for Variable rst_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1539 1 T3 1 T6 17 T9 38
auto[1] 3918 1 T3 2 T6 46 T9 63



Summary for Cross sw_rst_cross

Samples crossed: enable rst_n
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for sw_rst_cross

Bins
enablerst_nCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 85 1 T6 1 T12 2 T25 1
auto[0] auto[1] 193 1 T6 3 T12 1 T25 3
auto[1] auto[0] 1454 1 T3 1 T6 16 T9 38
auto[1] auto[1] 3725 1 T3 2 T6 43 T9 63

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%