Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	582929	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

349363

1

T1

1123

T2

5

T3

133

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	496087	1			T1	1500		T3	186		T4	1466
values[0x0]	217611	1			T1	834		T2	5		T3	92
values[0x1]	218594	1			T1	866		T2	10		T3	101

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	489249	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

443043

1

T1

1453

T2

6

T3

171

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3380	1			T3	7		T4	19		T6	4
valid_sources[0x01]	2871	1			T3	1		T4	12		T6	4
valid_sources[0x02]	4358	1			T3	2		T6	5		T9	198
valid_sources[0x03]	3726	1			T6	9		T10	1		T11	3
valid_sources[0x04]	3329	1			T3	2		T4	4		T6	5
valid_sources[0x05]	6455	1			T6	4		T9	156		T11	2
valid_sources[0x06]	3574	1			T3	2		T4	13		T6	4
valid_sources[0x07]	2741	1			T4	16		T6	9		T10	2
valid_sources[0x08]	3169	1			T4	8		T6	4		T9	183
valid_sources[0x09]	3287	1			T3	1		T4	10		T6	2
valid_sources[0x0a]	4324	1			T3	1		T4	4		T6	4
valid_sources[0x0b]	3385	1			T3	5		T4	18		T6	7
valid_sources[0x0c]	4224	1			T4	3		T6	7		T9	197
valid_sources[0x0d]	3010	1			T3	3		T6	2		T23	5
valid_sources[0x0e]	3207	1			T4	22		T9	2		T10	1
valid_sources[0x0f]	4404	1			T3	1		T4	18		T6	1
valid_sources[0x10]	3121	1			T4	5		T6	3		T23	9
valid_sources[0x11]	3231	1			T3	1		T4	12		T6	4
valid_sources[0x12]	3110	1			T3	1		T4	18		T6	2
valid_sources[0x13]	4325	1			T3	1		T4	4		T6	6
valid_sources[0x14]	3374	1			T4	6		T6	10		T9	35
valid_sources[0x15]	3762	1			T3	1		T4	13		T6	4
valid_sources[0x16]	3994	1			T3	1		T6	6		T10	1
valid_sources[0x17]	3432	1			T2	1		T3	4		T4	7
valid_sources[0x18]	2954	1			T3	2		T4	14		T6	7
valid_sources[0x19]	4294	1			T3	2		T4	10		T6	1
valid_sources[0x1a]	3849	1			T4	1		T6	10		T9	268
valid_sources[0x1b]	6268	1			T3	2		T4	3		T6	6
valid_sources[0x1c]	3238	1			T3	4		T4	2		T6	1
valid_sources[0x1d]	3040	1			T3	1		T4	7		T6	2
valid_sources[0x1e]	3717	1			T4	39		T6	5		T9	8
valid_sources[0x1f]	2761	1			T4	9		T6	5		T9	3
valid_sources[0x20]	2960	1			T6	2		T10	1		T11	1
valid_sources[0x21]	3208	1			T4	1		T6	10		T9	165
valid_sources[0x22]	3281	1			T3	2		T4	6		T6	5
valid_sources[0x23]	5078	1			T3	1		T4	19		T6	5
valid_sources[0x24]	4210	1			T4	7		T5	1		T6	4
valid_sources[0x25]	3412	1			T3	1		T4	13		T6	7
valid_sources[0x26]	3540	1			T4	4		T12	134		T23	15
valid_sources[0x27]	3367	1			T4	24		T6	3		T9	312
valid_sources[0x28]	2840	1			T3	4		T4	1		T6	7
valid_sources[0x29]	2791	1			T6	4		T23	6		T25	3
valid_sources[0x2a]	3414	1			T2	1		T3	3		T4	4
valid_sources[0x2b]	2830	1			T3	5		T4	36		T6	6
valid_sources[0x2c]	2828	1			T3	6		T4	7		T6	4
valid_sources[0x2d]	2915	1			T3	1		T4	10		T5	1
valid_sources[0x2e]	3760	1			T3	2		T4	9		T6	5
valid_sources[0x2f]	2708	1			T3	1		T6	7		T10	2
valid_sources[0x30]	2825	1			T3	1		T4	7		T6	4
valid_sources[0x31]	2784	1			T3	2		T6	3		T23	9
valid_sources[0x32]	3914	1			T4	14		T6	2		T10	1
valid_sources[0x33]	4039	1			T4	20		T6	3		T9	512
valid_sources[0x34]	2807	1			T3	2		T4	19		T6	8
valid_sources[0x35]	3216	1			T3	1		T6	3		T7	1
valid_sources[0x36]	3288	1			T2	2		T4	4		T5	1
valid_sources[0x37]	2775	1			T4	3		T6	1		T11	8
valid_sources[0x38]	3951	1			T4	1		T6	6		T11	1
valid_sources[0x39]	2883	1			T2	1		T3	1		T4	2
valid_sources[0x3a]	3088	1			T3	2		T4	15		T6	2
valid_sources[0x3b]	4791	1			T4	52		T5	1		T10	1
valid_sources[0x3c]	3422	1			T4	21		T9	236		T10	2
valid_sources[0x3d]	3633	1			T4	15		T6	7		T9	692
valid_sources[0x3e]	3658	1			T3	3		T4	13		T6	1
valid_sources[0x3f]	3728	1			T4	3		T6	1		T9	4
valid_sources[0x40]	6146	1			T3	2		T4	43		T6	8
valid_sources[0x41]	3091	1			T3	2		T4	2		T6	1
valid_sources[0x42]	3343	1			T3	2		T4	22		T6	2
valid_sources[0x43]	3144	1			T3	2		T4	11		T6	3
valid_sources[0x44]	3071	1			T4	26		T6	2		T9	55
valid_sources[0x45]	3179	1			T4	15		T6	2		T23	8
valid_sources[0x46]	3259	1			T3	4		T4	13		T6	7
valid_sources[0x47]	2904	1			T3	2		T4	36		T6	2
valid_sources[0x48]	3055	1			T3	3		T4	9		T6	4
valid_sources[0x49]	3373	1			T6	6		T9	111		T23	13
valid_sources[0x4a]	6081	1			T4	14		T6	4		T11	3
valid_sources[0x4b]	4171	1			T3	4		T6	6		T9	1
valid_sources[0x4c]	3207	1			T3	1		T4	14		T6	3
valid_sources[0x4d]	3453	1			T3	4		T4	8		T6	6
valid_sources[0x4e]	3071	1			T4	1		T6	7		T23	17
valid_sources[0x4f]	6538	1			T3	3		T4	4		T6	3
valid_sources[0x50]	3288	1			T3	6		T4	41		T6	5
valid_sources[0x51]	3113	1			T4	6		T6	4		T9	25
valid_sources[0x52]	3054	1			T4	7		T6	4		T10	3
valid_sources[0x53]	3580	1			T4	4		T6	5		T23	20
valid_sources[0x54]	3212	1			T3	2		T4	7		T6	6
valid_sources[0x55]	4530	1			T3	1		T4	19		T6	3
valid_sources[0x56]	2870	1			T4	5		T6	4		T10	1
valid_sources[0x57]	3817	1			T3	1		T4	16		T5	1
valid_sources[0x58]	3222	1			T4	28		T5	1		T6	6
valid_sources[0x59]	4339	1			T4	5		T6	7		T9	229
valid_sources[0x5a]	3105	1			T4	3		T6	4		T10	2
valid_sources[0x5b]	3306	1			T2	1		T3	9		T4	11
valid_sources[0x5c]	3646	1			T2	1		T3	8		T4	8
valid_sources[0x5d]	3253	1			T4	4		T5	1		T6	5
valid_sources[0x5e]	5263	1			T2	1		T3	2		T4	1
valid_sources[0x5f]	3017	1			T3	1		T4	18		T6	8
valid_sources[0x60]	3146	1			T3	2		T4	5		T6	8
valid_sources[0x61]	3162	1			T4	7		T6	9		T10	1
valid_sources[0x62]	3671	1			T3	1		T4	10		T6	4
valid_sources[0x63]	2992	1			T3	4		T4	16		T6	2
valid_sources[0x64]	3899	1			T3	1		T4	29		T5	1
valid_sources[0x65]	3434	1			T3	5		T4	24		T6	5
valid_sources[0x66]	4596	1			T3	4		T4	16		T6	3
valid_sources[0x67]	3603	1			T3	1		T4	23		T6	6
valid_sources[0x68]	3078	1			T3	4		T6	2		T9	123
valid_sources[0x69]	4569	1			T4	4		T5	1		T6	4
valid_sources[0x6a]	3283	1			T3	2		T4	14		T6	4
valid_sources[0x6b]	3148	1			T4	33		T6	6		T9	12
valid_sources[0x6c]	3237	1			T3	1		T4	22		T6	4
valid_sources[0x6d]	3946	1			T4	8		T6	5		T23	15
valid_sources[0x6e]	3434	1			T3	2		T4	20		T6	1
valid_sources[0x6f]	2707	1			T3	6		T4	2		T6	7
valid_sources[0x70]	3843	1			T4	15		T6	3		T10	1
valid_sources[0x71]	3647	1			T3	1		T4	7		T6	2
valid_sources[0x72]	4070	1			T2	1		T3	1		T6	7
valid_sources[0x73]	3295	1			T3	1		T4	8		T5	1
valid_sources[0x74]	3963	1			T4	21		T5	1		T6	5
valid_sources[0x75]	3418	1			T3	1		T4	9		T6	4
valid_sources[0x76]	4132	1			T3	2		T4	4		T6	3
valid_sources[0x77]	3619	1			T3	1		T4	15		T6	6
valid_sources[0x78]	3481	1			T3	5		T4	11		T6	6
valid_sources[0x79]	2987	1			T3	2		T4	17		T6	4
valid_sources[0x7a]	4226	1			T4	17		T6	5		T10	2
valid_sources[0x7b]	2939	1			T3	2		T6	3		T23	8
valid_sources[0x7c]	3337	1			T3	3		T4	1		T6	2
valid_sources[0x7d]	3286	1			T2	1		T4	13		T6	7
valid_sources[0x7e]	3850	1			T3	4		T4	3		T6	1
valid_sources[0x7f]	2869	1			T2	1		T5	1		T6	2
valid_sources[0x80]	2965	1			T4	18		T6	3		T23	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

232666

1

T1

687

T3

84

T4

694

values[0x0]

all_enables

biggest_size

76157

1

T1

277

T2

3

T3

34

values[0x1]

all_enables

biggest_size

40540

1

T1

159

T2

2

T3

15