SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_aon |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_daon_lc_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_d0_lc_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_daon_lc_io_div4_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_d0_lc_io_div4_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_sys |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_sys_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_device |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_host0 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_host1 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | u_d0_usb_aon |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c0 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c1 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 16599 | 16599 | 0 | 0 |
OutputsKnown_A | 368956929 | 214418779 | 0 | 0 |
gen_no_flops.OutputDelay_A | 368956929 | 214418779 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 16599 | 16599 | 0 | 0 |
T1 | 33 | 33 | 0 | 0 |
T2 | 33 | 33 | 0 | 0 |
T3 | 33 | 33 | 0 | 0 |
T4 | 33 | 33 | 0 | 0 |
T5 | 33 | 33 | 0 | 0 |
T6 | 33 | 33 | 0 | 0 |
T7 | 33 | 33 | 0 | 0 |
T8 | 33 | 33 | 0 | 0 |
T9 | 33 | 33 | 0 | 0 |
T10 | 33 | 33 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 368956929 | 214418779 | 0 | 0 |
T1 | 1397750 | 822810 | 0 | 0 |
T2 | 53056 | 33943 | 0 | 0 |
T3 | 168526 | 135056 | 0 | 0 |
T4 | 948134 | 654176 | 0 | 0 |
T5 | 52083 | 31699 | 0 | 0 |
T6 | 125080 | 104563 | 0 | 0 |
T7 | 89749 | 28262 | 0 | 0 |
T8 | 121249 | 87514 | 0 | 0 |
T9 | 3459453 | 1830413 | 0 | 0 |
T10 | 73365 | 41766 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 368956929 | 214418779 | 0 | 0 |
T1 | 1397750 | 822810 | 0 | 0 |
T2 | 53056 | 33943 | 0 | 0 |
T3 | 168526 | 135056 | 0 | 0 |
T4 | 948134 | 654176 | 0 | 0 |
T5 | 52083 | 31699 | 0 | 0 |
T6 | 125080 | 104563 | 0 | 0 |
T7 | 89749 | 28262 | 0 | 0 |
T8 | 121249 | 87514 | 0 | 0 |
T9 | 3459453 | 1830413 | 0 | 0 |
T10 | 73365 | 41766 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 12560289 | 7534619 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12560289 | 7534619 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12560289 | 7534619 | 0 | 0 |
T1 | 45302 | 27962 | 0 | 0 |
T2 | 1696 | 1047 | 0 | 0 |
T3 | 5294 | 4336 | 0 | 0 |
T4 | 32774 | 23168 | 0 | 0 |
T5 | 1619 | 979 | 0 | 0 |
T6 | 3832 | 3187 | 0 | 0 |
T7 | 2901 | 1094 | 0 | 0 |
T8 | 3809 | 2842 | 0 | 0 |
T9 | 129789 | 75533 | 0 | 0 |
T10 | 2549 | 1510 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12560289 | 7534619 | 0 | 0 |
T1 | 45302 | 27962 | 0 | 0 |
T2 | 1696 | 1047 | 0 | 0 |
T3 | 5294 | 4336 | 0 | 0 |
T4 | 32774 | 23168 | 0 | 0 |
T5 | 1619 | 979 | 0 | 0 |
T6 | 3832 | 3187 | 0 | 0 |
T7 | 2901 | 1094 | 0 | 0 |
T8 | 3809 | 2842 | 0 | 0 |
T9 | 129789 | 75533 | 0 | 0 |
T10 | 2549 | 1510 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 503 | 503 | 0 | 0 |
OutputsKnown_A | 11137395 | 6465130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11137395 | 6465130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 503 | 503 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11137395 | 6465130 | 0 | 0 |
T1 | 42264 | 24839 | 0 | 0 |
T2 | 1605 | 1028 | 0 | 0 |
T3 | 5101 | 4085 | 0 | 0 |
T4 | 28605 | 19719 | 0 | 0 |
T5 | 1577 | 960 | 0 | 0 |
T6 | 3789 | 3168 | 0 | 0 |
T7 | 2714 | 849 | 0 | 0 |
T8 | 3670 | 2646 | 0 | 0 |
T9 | 104052 | 54840 | 0 | 0 |
T10 | 2213 | 1258 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |