Module Definition
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Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_aon_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_rst_pd_n[0].u_rst_pd_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_aon_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_rst_pd_n[0].u_rst_pd_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_root_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_clean_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_out_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1245766 1213574 0 0
selKnown1 163520 131328 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1245766 1213574 0 0
T1 5853 5789 0 0
T2 64 0 0 0
T3 348 284 0 0
T4 2960 2896 0 0
T5 64 0 0 0
T6 152 88 0 0
T7 138 74 0 0
T8 347 283 0 0
T9 18816 18752 0 0
T10 347 283 0 0
T11 0 286 0 0
T12 0 284 0 0
T13 0 243 0 0
T14 0 19 0 0
T23 0 10 0 0
T24 0 7 0 0
T49 0 94 0 0
T50 0 16 0 0
T91 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 163520 131328 0 0
T3 128 64 0 0
T4 512 448 0 0
T5 64 0 0 0
T6 64 0 0 0
T7 64 0 0 0
T8 128 64 0 0
T9 2624 2560 0 0
T10 128 64 0 0
T11 128 64 0 0
T12 128 64 0 0
T13 0 64 0 0
T23 0 704 0 0
T47 0 64 0 0

Line Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21123 20620 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21123 20620 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21123 20620 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21123 20620 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21123 20620 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21123 20620 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21123 20620 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21123 20620 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 8497 7994 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 8497 7994 0 0
T1 27 26 0 0
T2 1 0 0 0
T3 2 1 0 0
T4 18 17 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 2 1 0 0
T9 100 99 0 0
T10 2 1 0 0
T11 0 1 0 0
T12 0 1 0 0
T13 0 1 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21173 20670 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21173 20670 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 8497 7994 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 8497 7994 0 0
T1 27 26 0 0
T2 1 0 0 0
T3 2 1 0 0
T4 18 17 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 2 1 0 0
T9 100 99 0 0
T10 2 1 0 0
T11 0 1 0 0
T12 0 1 0 0
T13 0 1 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21173 20670 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21173 20670 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 8497 7994 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 8497 7994 0 0
T1 27 26 0 0
T2 1 0 0 0
T3 2 1 0 0
T4 18 17 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 2 1 0 0
T9 100 99 0 0
T10 2 1 0 0
T11 0 1 0 0
T12 0 1 0 0
T13 0 1 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21173 20670 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21173 20670 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 8497 7994 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 8497 7994 0 0
T1 27 26 0 0
T2 1 0 0 0
T3 2 1 0 0
T4 18 17 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 2 1 0 0
T9 100 99 0 0
T10 2 1 0 0
T11 0 1 0 0
T12 0 1 0 0
T13 0 1 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21173 20670 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21173 20670 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 8497 7994 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 8497 7994 0 0
T1 27 26 0 0
T2 1 0 0 0
T3 2 1 0 0
T4 18 17 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 2 1 0 0
T9 100 99 0 0
T10 2 1 0 0
T11 0 1 0 0
T12 0 1 0 0
T13 0 1 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21173 20670 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21173 20670 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21123 20620 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21123 20620 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21173 20670 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21173 20670 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21123 20620 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21123 20620 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21173 20670 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21173 20670 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21123 20620 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21123 20620 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21173 20670 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21173 20670 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21123 20620 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21123 20620 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21173 20670 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21173 20670 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21123 20620 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21123 20620 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21059 20556 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21059 20556 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 322 321 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21123 20620 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21123 20620 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21173 20670 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21173 20670 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21123 20620 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21123 20620 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21173 20670 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21173 20670 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21123 20620 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21123 20620 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21173 20670 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21173 20670 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21123 20620 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21123 20620 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21173 20670 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21173 20670 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21123 20620 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21123 20620 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21123 20620 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21123 20620 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21123 20620 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21123 20620 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21123 20620 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21123 20620 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21123 20620 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21123 20620 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21173 20670 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21173 20670 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21123 20620 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21123 20620 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21173 20670 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21173 20670 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21123 20620 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21123 20620 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21173 20670 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21173 20670 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21123 20620 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21123 20620 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21173 20670 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21173 20670 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21922 21419 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21922 21419 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 8 7 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 349 348 0 0
T10 6 5 0 0
T11 0 6 0 0
T12 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21173 20670 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21173 20670 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21949 21446 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21949 21446 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 9 8 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 346 345 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21173 20670 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21173 20670 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 22018 21515 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 22018 21515 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 8 7 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 346 345 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21173 20670 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21173 20670 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 22045 21542 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 22045 21542 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 13 12 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 348 347 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21173 20670 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21173 20670 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 22094 21591 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 22094 21591 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 14 13 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 346 345 0 0
T10 6 5 0 0
T11 0 6 0 0
T12 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21059 20556 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21059 20556 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 322 321 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 22146 21643 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 22146 21643 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 16 15 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 345 344 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 6 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21173 20670 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21173 20670 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 22216 21713 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 22216 21713 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 14 13 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 348 347 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21173 20670 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21173 20670 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 22259 21756 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 22259 21756 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 7 6 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 14 13 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 349 348 0 0
T10 6 5 0 0
T11 0 6 0 0
T12 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 21173 20670 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 21173 20670 0 0
T1 102 101 0 0
T2 1 0 0 0
T3 6 5 0 0
T4 51 50 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 6 5 0 0
T9 323 322 0 0
T10 6 5 0 0
T11 0 5 0 0
T12 0 5 0 0
T13 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 6888 6385 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 6888 6385 0 0
T1 27 26 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 11 10 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 7 6 0 0
T8 1 0 0 0
T9 60 59 0 0
T10 1 0 0 0
T14 0 19 0 0
T23 0 10 0 0
T24 0 7 0 0
T49 0 94 0 0
T50 0 16 0 0
T91 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 8897 8394 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 8897 8394 0 0
T1 27 26 0 0
T2 1 0 0 0
T3 2 1 0 0
T4 18 17 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 7 6 0 0
T8 2 1 0 0
T9 100 99 0 0
T10 2 1 0 0
T11 0 1 0 0
T12 0 1 0 0
T13 0 1 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 8497 7994 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 8497 7994 0 0
T1 27 26 0 0
T2 1 0 0 0
T3 2 1 0 0
T4 18 17 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 2 1 0 0
T9 100 99 0 0
T10 2 1 0 0
T11 0 1 0 0
T12 0 1 0 0
T13 0 1 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 8497 7994 0 0
selKnown1 2555 2052 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 8497 7994 0 0
T1 27 26 0 0
T2 1 0 0 0
T3 2 1 0 0
T4 18 17 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 2 1 0 0
T8 2 1 0 0
T9 100 99 0 0
T10 2 1 0 0
T11 0 1 0 0
T12 0 1 0 0
T13 0 1 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2555 2052 0 0
T3 2 1 0 0
T4 8 7 0 0
T5 1 0 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T9 41 40 0 0
T10 2 1 0 0
T11 2 1 0 0
T12 2 1 0 0
T13 0 1 0 0
T23 0 11 0 0
T47 0 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%