Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T9,T11
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T9,T25
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T9,T25
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T9,T25
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T9,T11
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T9,T12
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T9,T25
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T9
1	0	Covered	T1,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12560289	13425	0	0
gen_assertions[0].RstEnOn_A	12560289	992	0	0
gen_assertions[0].RstNOff_A	12560289	13425	0	0
gen_assertions[0].RstNOn_A	12560289	992	0	0
gen_assertions[1].RstEnOff_A	50240270	12167	0	0
gen_assertions[1].RstEnOn_A	50240270	931	0	0
gen_assertions[1].RstNOff_A	50240270	12167	0	0
gen_assertions[1].RstNOn_A	50240270	931	0	0
gen_assertions[2].RstEnOff_A	25121023	12236	0	0
gen_assertions[2].RstEnOn_A	25121023	945	0	0
gen_assertions[2].RstNOff_A	25121023	12236	0	0
gen_assertions[2].RstNOn_A	25121023	945	0	0
gen_assertions[3].RstEnOff_A	25120854	12263	0	0
gen_assertions[3].RstEnOn_A	25120854	963	0	0
gen_assertions[3].RstNOff_A	25120854	12263	0	0
gen_assertions[3].RstNOn_A	25120854	963	0	0
gen_assertions[4].RstEnOff_A	1585816	20803	0	0
gen_assertions[4].RstEnOn_A	1585816	1025	0	0
gen_assertions[4].RstNOff_A	1585816	20803	0	0
gen_assertions[4].RstNOn_A	1585816	1025	0	0
gen_assertions[5].RstEnOff_A	12560289	13649	0	0
gen_assertions[5].RstEnOn_A	12560289	1046	0	0
gen_assertions[5].RstNOff_A	12560289	13649	0	0
gen_assertions[5].RstNOn_A	12560289	1046	0	0
gen_assertions[6].RstEnOff_A	12560289	13719	0	0
gen_assertions[6].RstEnOn_A	12560289	1131	0	0
gen_assertions[6].RstNOff_A	12560289	13719	0	0
gen_assertions[6].RstNOn_A	12560289	1131	0	0
gen_assertions[7].RstEnOff_A	12560289	13762	0	0
gen_assertions[7].RstEnOn_A	12560289	1179	0	0
gen_assertions[7].RstNOff_A	12560289	13762	0	0
gen_assertions[7].RstNOn_A	12560289	1179	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12560289	13425	0	0
T1	45302	75	0	0
T2	1696	0	0	0
T3	5294	4	0	0
T4	32774	33	0	0
T5	1619	0	0	0
T6	3832	7	0	0
T7	2901	0	0	0
T8	3809	4	0	0
T9	129789	249	0	0
T10	2549	4	0	0
T11	0	5	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12560289	992	0	0
T6	3832	7	0	0
T7	2901	0	0	0
T8	3809	0	0	0
T9	129789	30	0	0
T10	2549	0	0	0
T11	2855	1	0	0
T12	2859	0	0	0
T13	2532	0	0	0
T23	22325	0	0	0
T24	5821	0	0	0
T25	0	3	0	0
T47	0	1	0	0
T48	0	5	0	0
T49	0	9	0	0
T50	0	19	0	0
T93	0	4	0	0
T94	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12560289	13425	0	0
T1	45302	75	0	0
T2	1696	0	0	0
T3	5294	4	0	0
T4	32774	33	0	0
T5	1619	0	0	0
T6	3832	7	0	0
T7	2901	0	0	0
T8	3809	4	0	0
T9	129789	249	0	0
T10	2549	4	0	0
T11	0	5	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12560289	992	0	0
T6	3832	7	0	0
T7	2901	0	0	0
T8	3809	0	0	0
T9	129789	30	0	0
T10	2549	0	0	0
T11	2855	1	0	0
T12	2859	0	0	0
T13	2532	0	0	0
T23	22325	0	0	0
T24	5821	0	0	0
T25	0	3	0	0
T47	0	1	0	0
T48	0	5	0	0
T49	0	9	0	0
T50	0	19	0	0
T93	0	4	0	0
T94	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50240270	12167	0	0
T1	181234	63	0	0
T2	6784	0	0	0
T3	21182	4	0	0
T4	131106	29	0	0
T5	6482	0	0	0
T6	15334	8	0	0
T7	11608	0	0	0
T8	15238	4	0	0
T9	519096	214	0	0
T10	10201	3	0	0
T11	0	4	0	0
T12	0	4	0	0
T13	0	3	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50240270	931	0	0
T6	15334	8	0	0
T7	11608	0	0	0
T8	15238	0	0	0
T9	519096	26	0	0
T10	10201	0	0	0
T11	11425	0	0	0
T12	11443	0	0	0
T13	10133	0	0	0
T23	89305	0	0	0
T24	23286	0	0	0
T25	0	8	0	0
T48	0	7	0	0
T49	0	9	0	0
T50	0	19	0	0
T51	0	5	0	0
T93	0	6	0	0
T94	0	2	0	0
T95	0	6	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50240270	12167	0	0
T1	181234	63	0	0
T2	6784	0	0	0
T3	21182	4	0	0
T4	131106	29	0	0
T5	6482	0	0	0
T6	15334	8	0	0
T7	11608	0	0	0
T8	15238	4	0	0
T9	519096	214	0	0
T10	10201	3	0	0
T11	0	4	0	0
T12	0	4	0	0
T13	0	3	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50240270	931	0	0
T6	15334	8	0	0
T7	11608	0	0	0
T8	15238	0	0	0
T9	519096	26	0	0
T10	10201	0	0	0
T11	11425	0	0	0
T12	11443	0	0	0
T13	10133	0	0	0
T23	89305	0	0	0
T24	23286	0	0	0
T25	0	8	0	0
T48	0	7	0	0
T49	0	9	0	0
T50	0	19	0	0
T51	0	5	0	0
T93	0	6	0	0
T94	0	2	0	0
T95	0	6	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25121023	12236	0	0
T1	90615	63	0	0
T2	3391	0	0	0
T3	10587	4	0	0
T4	65552	29	0	0
T5	3241	0	0	0
T6	7667	7	0	0
T7	5804	0	0	0
T8	7616	4	0	0
T9	259568	214	0	0
T10	5098	3	0	0
T11	0	4	0	0
T12	0	4	0	0
T13	0	3	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25121023	945	0	0
T6	7667	7	0	0
T7	5804	0	0	0
T8	7616	0	0	0
T9	259568	24	0	0
T10	5098	0	0	0
T11	5711	0	0	0
T12	5722	0	0	0
T13	5065	0	0	0
T23	44659	0	0	0
T24	11650	0	0	0
T25	0	5	0	0
T48	0	6	0	0
T49	0	12	0	0
T50	0	21	0	0
T51	0	8	0	0
T93	0	5	0	0
T94	0	3	0	0
T95	0	6	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25121023	12236	0	0
T1	90615	63	0	0
T2	3391	0	0	0
T3	10587	4	0	0
T4	65552	29	0	0
T5	3241	0	0	0
T6	7667	7	0	0
T7	5804	0	0	0
T8	7616	4	0	0
T9	259568	214	0	0
T10	5098	3	0	0
T11	0	4	0	0
T12	0	4	0	0
T13	0	3	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25121023	945	0	0
T6	7667	7	0	0
T7	5804	0	0	0
T8	7616	0	0	0
T9	259568	24	0	0
T10	5098	0	0	0
T11	5711	0	0	0
T12	5722	0	0	0
T13	5065	0	0	0
T23	44659	0	0	0
T24	11650	0	0	0
T25	0	5	0	0
T48	0	6	0	0
T49	0	12	0	0
T50	0	21	0	0
T51	0	8	0	0
T93	0	5	0	0
T94	0	3	0	0
T95	0	6	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25120854	12263	0	0
T1	90612	63	0	0
T2	3391	0	0	0
T3	10588	4	0	0
T4	65560	29	0	0
T5	3241	0	0	0
T6	7666	12	0	0
T7	5804	0	0	0
T8	7620	4	0	0
T9	259580	216	0	0
T10	5098	3	0	0
T11	0	4	0	0
T12	0	4	0	0
T13	0	3	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25120854	963	0	0
T6	7666	12	0	0
T7	5804	0	0	0
T8	7620	0	0	0
T9	259580	28	0	0
T10	5098	0	0	0
T11	5711	0	0	0
T12	5723	0	0	0
T13	5066	0	0	0
T23	44652	0	0	0
T24	11643	0	0	0
T25	0	6	0	0
T48	0	10	0	0
T49	0	10	0	0
T50	0	18	0	0
T51	0	8	0	0
T93	0	6	0	0
T94	0	4	0	0
T95	0	5	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25120854	12263	0	0
T1	90612	63	0	0
T2	3391	0	0	0
T3	10588	4	0	0
T4	65560	29	0	0
T5	3241	0	0	0
T6	7666	12	0	0
T7	5804	0	0	0
T8	7620	4	0	0
T9	259580	216	0	0
T10	5098	3	0	0
T11	0	4	0	0
T12	0	4	0	0
T13	0	3	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25120854	963	0	0
T6	7666	12	0	0
T7	5804	0	0	0
T8	7620	0	0	0
T9	259580	28	0	0
T10	5098	0	0	0
T11	5711	0	0	0
T12	5723	0	0	0
T13	5066	0	0	0
T23	44652	0	0	0
T24	11643	0	0	0
T25	0	6	0	0
T48	0	10	0	0
T49	0	10	0	0
T50	0	18	0	0
T51	0	8	0	0
T93	0	6	0	0
T94	0	4	0	0
T95	0	5	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1585816	20803	0	0
T1	5678	93	0	0
T2	210	1	0	0
T3	661	6	0	0
T4	4152	51	0	0
T5	202	1	0	0
T6	478	14	0	0
T7	360	2	0	0
T8	474	6	0	0
T9	16650	334	0	0
T10	317	5	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1585816	1025	0	0
T6	478	13	0	0
T7	360	0	0	0
T8	474	0	0	0
T9	16650	26	0	0
T10	317	0	0	0
T11	356	1	0	0
T12	357	0	0	0
T13	316	0	0	0
T23	2858	0	0	0
T24	729	0	0	0
T25	0	9	0	0
T47	0	1	0	0
T48	0	8	0	0
T49	0	11	0	0
T50	0	18	0	0
T93	0	8	0	0
T94	0	4	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1585816	20803	0	0
T1	5678	93	0	0
T2	210	1	0	0
T3	661	6	0	0
T4	4152	51	0	0
T5	202	1	0	0
T6	478	14	0	0
T7	360	2	0	0
T8	474	6	0	0
T9	16650	334	0	0
T10	317	5	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1585816	1025	0	0
T6	478	13	0	0
T7	360	0	0	0
T8	474	0	0	0
T9	16650	26	0	0
T10	317	0	0	0
T11	356	1	0	0
T12	357	0	0	0
T13	316	0	0	0
T23	2858	0	0	0
T24	729	0	0	0
T25	0	9	0	0
T47	0	1	0	0
T48	0	8	0	0
T49	0	11	0	0
T50	0	18	0	0
T93	0	8	0	0
T94	0	4	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12560289	13649	0	0
T1	45302	75	0	0
T2	1696	0	0	0
T3	5294	4	0	0
T4	32774	33	0	0
T5	1619	0	0	0
T6	3832	15	0	0
T7	2901	0	0	0
T8	3809	4	0	0
T9	129789	245	0	0
T10	2549	4	0	0
T11	0	4	0	0
T12	0	5	0	0
T13	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12560289	1046	0	0
T6	3832	15	0	0
T7	2901	0	0	0
T8	3809	0	0	0
T9	129789	25	0	0
T10	2549	0	0	0
T11	2855	0	0	0
T12	2859	1	0	0
T13	2532	0	0	0
T23	22325	0	0	0
T24	5821	0	0	0
T25	0	11	0	0
T48	0	11	0	0
T49	0	8	0	0
T50	0	20	0	0
T51	0	12	0	0
T93	0	10	0	0
T94	0	5	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12560289	13649	0	0
T1	45302	75	0	0
T2	1696	0	0	0
T3	5294	4	0	0
T4	32774	33	0	0
T5	1619	0	0	0
T6	3832	15	0	0
T7	2901	0	0	0
T8	3809	4	0	0
T9	129789	245	0	0
T10	2549	4	0	0
T11	0	4	0	0
T12	0	5	0	0
T13	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12560289	1046	0	0
T6	3832	15	0	0
T7	2901	0	0	0
T8	3809	0	0	0
T9	129789	25	0	0
T10	2549	0	0	0
T11	2855	0	0	0
T12	2859	1	0	0
T13	2532	0	0	0
T23	22325	0	0	0
T24	5821	0	0	0
T25	0	11	0	0
T48	0	11	0	0
T49	0	8	0	0
T50	0	20	0	0
T51	0	12	0	0
T93	0	10	0	0
T94	0	5	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12560289	13719	0	0
T1	45302	75	0	0
T2	1696	0	0	0
T3	5294	4	0	0
T4	32774	33	0	0
T5	1619	0	0	0
T6	3832	13	0	0
T7	2901	0	0	0
T8	3809	4	0	0
T9	129789	248	0	0
T10	2549	4	0	0
T11	0	4	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12560289	1131	0	0
T6	3832	13	0	0
T7	2901	0	0	0
T8	3809	0	0	0
T9	129789	27	0	0
T10	2549	0	0	0
T11	2855	0	0	0
T12	2859	0	0	0
T13	2532	0	0	0
T23	22325	0	0	0
T24	5821	0	0	0
T25	0	11	0	0
T48	0	13	0	0
T49	0	14	0	0
T50	0	19	0	0
T51	0	11	0	0
T93	0	9	0	0
T94	0	7	0	0
T95	0	11	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12560289	13719	0	0
T1	45302	75	0	0
T2	1696	0	0	0
T3	5294	4	0	0
T4	32774	33	0	0
T5	1619	0	0	0
T6	3832	13	0	0
T7	2901	0	0	0
T8	3809	4	0	0
T9	129789	248	0	0
T10	2549	4	0	0
T11	0	4	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12560289	1131	0	0
T6	3832	13	0	0
T7	2901	0	0	0
T8	3809	0	0	0
T9	129789	27	0	0
T10	2549	0	0	0
T11	2855	0	0	0
T12	2859	0	0	0
T13	2532	0	0	0
T23	22325	0	0	0
T24	5821	0	0	0
T25	0	11	0	0
T48	0	13	0	0
T49	0	14	0	0
T50	0	19	0	0
T51	0	11	0	0
T93	0	9	0	0
T94	0	7	0	0
T95	0	11	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12560289	13762	0	0
T1	45302	75	0	0
T2	1696	0	0	0
T3	5294	5	0	0
T4	32774	33	0	0
T5	1619	0	0	0
T6	3832	13	0	0
T7	2901	0	0	0
T8	3809	4	0	0
T9	129789	249	0	0
T10	2549	4	0	0
T11	0	5	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12560289	1179	0	0
T3	5294	1	0	0
T4	32774	0	0	0
T5	1619	0	0	0
T6	3832	13	0	0
T7	2901	0	0	0
T8	3809	0	0	0
T9	129789	29	0	0
T10	2549	0	0	0
T11	2855	1	0	0
T12	2859	0	0	0
T25	0	12	0	0
T48	0	11	0	0
T49	0	11	0	0
T50	0	21	0	0
T93	0	11	0	0
T94	0	7	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12560289	13762	0	0
T1	45302	75	0	0
T2	1696	0	0	0
T3	5294	5	0	0
T4	32774	33	0	0
T5	1619	0	0	0
T6	3832	13	0	0
T7	2901	0	0	0
T8	3809	4	0	0
T9	129789	249	0	0
T10	2549	4	0	0
T11	0	5	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12560289	1179	0	0
T3	5294	1	0	0
T4	32774	0	0	0
T5	1619	0	0	0
T6	3832	13	0	0
T7	2901	0	0	0
T8	3809	0	0	0
T9	129789	29	0	0
T10	2549	0	0	0
T11	2855	1	0	0
T12	2859	0	0	0
T25	0	12	0	0
T48	0	11	0	0
T49	0	11	0	0
T50	0	21	0	0
T93	0	11	0	0
T94	0	7	0	0