SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_aon |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_daon_lc_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_d0_lc_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_daon_lc_io_div4_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_d0_lc_io_div4_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_sys |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_sys_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_device |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_host0 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_host1 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | u_d0_usb_aon |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c0 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c1 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 847887874 | 455132442 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 847887874 | 455132442 | 0 | 0 |
T1 | 3058136 | 1743535 | 0 | 0 |
T2 | 114466 | 70044 | 0 | 0 |
T3 | 357390 | 280640 | 0 | 0 |
T4 | 2212628 | 1391414 | 0 | 0 |
T5 | 109372 | 65473 | 0 | 0 |
T6 | 258744 | 210258 | 0 | 0 |
T7 | 195866 | 65401 | 0 | 0 |
T8 | 257138 | 182691 | 0 | 0 |
T9 | 8761780 | 4027564 | 0 | 0 |
T10 | 172090 | 89935 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 52335522 | 31415483 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 52335522 | 31415483 | 0 | 0 |
T1 | 188760 | 116597 | 0 | 0 |
T2 | 7067 | 4364 | 0 | 0 |
T3 | 22063 | 18072 | 0 | 0 |
T4 | 136568 | 96601 | 0 | 0 |
T5 | 6753 | 4081 | 0 | 0 |
T6 | 15974 | 13283 | 0 | 0 |
T7 | 12092 | 4563 | 0 | 0 |
T8 | 15876 | 11846 | 0 | 0 |
T9 | 540719 | 314777 | 0 | 0 |
T10 | 10624 | 6291 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 50240270 | 30157690 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 50240270 | 30157690 | 0 | 0 |
T1 | 181234 | 111959 | 0 | 0 |
T2 | 6784 | 4189 | 0 | 0 |
T3 | 21182 | 17350 | 0 | 0 |
T4 | 131106 | 92729 | 0 | 0 |
T5 | 6482 | 3918 | 0 | 0 |
T6 | 15334 | 12751 | 0 | 0 |
T7 | 11608 | 4381 | 0 | 0 |
T8 | 15238 | 11368 | 0 | 0 |
T9 | 519096 | 302187 | 0 | 0 |
T10 | 10201 | 6042 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 25121023 | 15075558 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 25121023 | 15075558 | 0 | 0 |
T1 | 90615 | 55978 | 0 | 0 |
T2 | 3391 | 2094 | 0 | 0 |
T3 | 10587 | 8671 | 0 | 0 |
T4 | 65552 | 46357 | 0 | 0 |
T5 | 3241 | 1959 | 0 | 0 |
T6 | 7667 | 6376 | 0 | 0 |
T7 | 5804 | 2190 | 0 | 0 |
T8 | 7616 | 5680 | 0 | 0 |
T9 | 259568 | 151070 | 0 | 0 |
T10 | 5098 | 3019 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 12560289 | 7534619 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12560289 | 7534619 | 0 | 0 |
T1 | 45302 | 27962 | 0 | 0 |
T2 | 1696 | 1047 | 0 | 0 |
T3 | 5294 | 4336 | 0 | 0 |
T4 | 32774 | 23168 | 0 | 0 |
T5 | 1619 | 979 | 0 | 0 |
T6 | 3832 | 3187 | 0 | 0 |
T7 | 2901 | 1094 | 0 | 0 |
T8 | 3809 | 2842 | 0 | 0 |
T9 | 129789 | 75533 | 0 | 0 |
T10 | 2549 | 1510 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 25120854 | 15075486 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 25120854 | 15075486 | 0 | 0 |
T1 | 90612 | 55980 | 0 | 0 |
T2 | 3391 | 2094 | 0 | 0 |
T3 | 10588 | 8672 | 0 | 0 |
T4 | 65560 | 46359 | 0 | 0 |
T5 | 3241 | 1959 | 0 | 0 |
T6 | 7666 | 6376 | 0 | 0 |
T7 | 5804 | 2190 | 0 | 0 |
T8 | 7620 | 5684 | 0 | 0 |
T9 | 259580 | 151072 | 0 | 0 |
T10 | 5098 | 3019 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 52335522 | 27896553 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 52335522 | 27896553 | 0 | 0 |
T1 | 188760 | 107236 | 0 | 0 |
T2 | 7067 | 4358 | 0 | 0 |
T3 | 22063 | 17272 | 0 | 0 |
T4 | 136568 | 84317 | 0 | 0 |
T5 | 6753 | 4075 | 0 | 0 |
T6 | 15974 | 13277 | 0 | 0 |
T7 | 12092 | 4551 | 0 | 0 |
T8 | 15876 | 11264 | 0 | 0 |
T9 | 540719 | 241229 | 0 | 0 |
T10 | 10624 | 5487 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 52335522 | 27199540 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 52335522 | 27199540 | 0 | 0 |
T1 | 188760 | 104827 | 0 | 0 |
T2 | 7067 | 4292 | 0 | 0 |
T3 | 22063 | 17106 | 0 | 0 |
T4 | 136568 | 82844 | 0 | 0 |
T5 | 6753 | 4009 | 0 | 0 |
T6 | 15974 | 13211 | 0 | 0 |
T7 | 12092 | 3552 | 0 | 0 |
T8 | 15876 | 11098 | 0 | 0 |
T9 | 540719 | 232697 | 0 | 0 |
T10 | 10624 | 5320 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 52335522 | 27896942 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 52335522 | 27896942 | 0 | 0 |
T1 | 188760 | 107266 | 0 | 0 |
T2 | 7067 | 4358 | 0 | 0 |
T3 | 22063 | 17272 | 0 | 0 |
T4 | 136568 | 84317 | 0 | 0 |
T5 | 6753 | 4075 | 0 | 0 |
T6 | 15974 | 13277 | 0 | 0 |
T7 | 12092 | 4551 | 0 | 0 |
T8 | 15876 | 11264 | 0 | 0 |
T9 | 540719 | 241229 | 0 | 0 |
T10 | 10624 | 5487 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 52335522 | 27200863 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 52335522 | 27200863 | 0 | 0 |
T1 | 188760 | 104885 | 0 | 0 |
T2 | 7067 | 4292 | 0 | 0 |
T3 | 22063 | 17106 | 0 | 0 |
T4 | 136568 | 82844 | 0 | 0 |
T5 | 6753 | 4009 | 0 | 0 |
T6 | 15974 | 13211 | 0 | 0 |
T7 | 12092 | 3552 | 0 | 0 |
T8 | 15876 | 11098 | 0 | 0 |
T9 | 540719 | 232697 | 0 | 0 |
T10 | 10624 | 5320 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 1585816 | 827573 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1585816 | 827573 | 0 | 0 |
T1 | 5678 | 3120 | 0 | 0 |
T2 | 210 | 129 | 0 | 0 |
T3 | 661 | 511 | 0 | 0 |
T4 | 4152 | 2529 | 0 | 0 |
T5 | 202 | 121 | 0 | 0 |
T6 | 478 | 397 | 0 | 0 |
T7 | 360 | 134 | 0 | 0 |
T8 | 474 | 329 | 0 | 0 |
T9 | 16650 | 7299 | 0 | 0 |
T10 | 317 | 159 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 50240270 | 26780998 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 50240270 | 26780998 | 0 | 0 |
T1 | 181234 | 102986 | 0 | 0 |
T2 | 6784 | 4183 | 0 | 0 |
T3 | 21182 | 16582 | 0 | 0 |
T4 | 131106 | 80936 | 0 | 0 |
T5 | 6482 | 3913 | 0 | 0 |
T6 | 15334 | 12745 | 0 | 0 |
T7 | 11608 | 4369 | 0 | 0 |
T8 | 15238 | 10810 | 0 | 0 |
T9 | 519096 | 231565 | 0 | 0 |
T10 | 10201 | 5272 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 50240270 | 26109690 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 50240270 | 26109690 | 0 | 0 |
T1 | 181234 | 100658 | 0 | 0 |
T2 | 6784 | 4119 | 0 | 0 |
T3 | 21182 | 16422 | 0 | 0 |
T4 | 131106 | 79520 | 0 | 0 |
T5 | 6482 | 3849 | 0 | 0 |
T6 | 15334 | 12681 | 0 | 0 |
T7 | 11608 | 3409 | 0 | 0 |
T8 | 15238 | 10650 | 0 | 0 |
T9 | 519096 | 223382 | 0 | 0 |
T10 | 10201 | 5112 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 25121023 | 13380894 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 25121023 | 13380894 | 0 | 0 |
T1 | 90615 | 51430 | 0 | 0 |
T2 | 3391 | 2091 | 0 | 0 |
T3 | 10587 | 8285 | 0 | 0 |
T4 | 65552 | 40444 | 0 | 0 |
T5 | 3241 | 1956 | 0 | 0 |
T6 | 7667 | 6373 | 0 | 0 |
T7 | 5804 | 2184 | 0 | 0 |
T8 | 7616 | 5400 | 0 | 0 |
T9 | 259568 | 115645 | 0 | 0 |
T10 | 5098 | 2631 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 25121023 | 13045237 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 25121023 | 13045237 | 0 | 0 |
T1 | 90615 | 50262 | 0 | 0 |
T2 | 3391 | 2059 | 0 | 0 |
T3 | 10587 | 8205 | 0 | 0 |
T4 | 65552 | 39736 | 0 | 0 |
T5 | 3241 | 1924 | 0 | 0 |
T6 | 7667 | 6341 | 0 | 0 |
T7 | 5804 | 1704 | 0 | 0 |
T8 | 7616 | 5320 | 0 | 0 |
T9 | 259568 | 111553 | 0 | 0 |
T10 | 5098 | 2551 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 12560289 | 6663786 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12560289 | 6663786 | 0 | 0 |
T1 | 45302 | 25577 | 0 | 0 |
T2 | 1696 | 1045 | 0 | 0 |
T3 | 5294 | 4136 | 0 | 0 |
T4 | 32774 | 20155 | 0 | 0 |
T5 | 1619 | 977 | 0 | 0 |
T6 | 3832 | 3185 | 0 | 0 |
T7 | 2901 | 1090 | 0 | 0 |
T8 | 3809 | 2695 | 0 | 0 |
T9 | 129789 | 57434 | 0 | 0 |
T10 | 2549 | 1309 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 12560289 | 6496006 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12560289 | 6496006 | 0 | 0 |
T1 | 45302 | 24995 | 0 | 0 |
T2 | 1696 | 1029 | 0 | 0 |
T3 | 5294 | 4096 | 0 | 0 |
T4 | 32774 | 19801 | 0 | 0 |
T5 | 1619 | 961 | 0 | 0 |
T6 | 3832 | 3169 | 0 | 0 |
T7 | 2901 | 850 | 0 | 0 |
T8 | 3809 | 2655 | 0 | 0 |
T9 | 129789 | 55388 | 0 | 0 |
T10 | 2549 | 1269 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 12560289 | 6663786 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12560289 | 6663786 | 0 | 0 |
T1 | 45302 | 25577 | 0 | 0 |
T2 | 1696 | 1045 | 0 | 0 |
T3 | 5294 | 4136 | 0 | 0 |
T4 | 32774 | 20155 | 0 | 0 |
T5 | 1619 | 977 | 0 | 0 |
T6 | 3832 | 3185 | 0 | 0 |
T7 | 2901 | 1090 | 0 | 0 |
T8 | 3809 | 2695 | 0 | 0 |
T9 | 129789 | 57434 | 0 | 0 |
T10 | 2549 | 1309 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 12560289 | 6496006 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12560289 | 6496006 | 0 | 0 |
T1 | 45302 | 24995 | 0 | 0 |
T2 | 1696 | 1029 | 0 | 0 |
T3 | 5294 | 4096 | 0 | 0 |
T4 | 32774 | 19801 | 0 | 0 |
T5 | 1619 | 961 | 0 | 0 |
T6 | 3832 | 3169 | 0 | 0 |
T7 | 2901 | 850 | 0 | 0 |
T8 | 3809 | 2655 | 0 | 0 |
T9 | 129789 | 55388 | 0 | 0 |
T10 | 2549 | 1269 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 25120854 | 13380829 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 25120854 | 13380829 | 0 | 0 |
T1 | 90612 | 51434 | 0 | 0 |
T2 | 3391 | 2091 | 0 | 0 |
T3 | 10588 | 8286 | 0 | 0 |
T4 | 65560 | 40447 | 0 | 0 |
T5 | 3241 | 1956 | 0 | 0 |
T6 | 7666 | 6373 | 0 | 0 |
T7 | 5804 | 2184 | 0 | 0 |
T8 | 7620 | 5404 | 0 | 0 |
T9 | 259580 | 115646 | 0 | 0 |
T10 | 5098 | 2631 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 25120854 | 13045324 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 25120854 | 13045324 | 0 | 0 |
T1 | 90612 | 50272 | 0 | 0 |
T2 | 3391 | 2059 | 0 | 0 |
T3 | 10588 | 8206 | 0 | 0 |
T4 | 65560 | 39739 | 0 | 0 |
T5 | 3241 | 1924 | 0 | 0 |
T6 | 7666 | 6341 | 0 | 0 |
T7 | 5804 | 1704 | 0 | 0 |
T8 | 7620 | 5324 | 0 | 0 |
T9 | 259580 | 111554 | 0 | 0 |
T10 | 5098 | 2551 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 52335522 | 26910420 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 52335522 | 26910420 | 0 | 0 |
T1 | 188760 | 103131 | 0 | 0 |
T2 | 7067 | 4292 | 0 | 0 |
T3 | 22063 | 16989 | 0 | 0 |
T4 | 136568 | 82075 | 0 | 0 |
T5 | 6753 | 4009 | 0 | 0 |
T6 | 15974 | 13211 | 0 | 0 |
T7 | 12092 | 3552 | 0 | 0 |
T8 | 15876 | 10994 | 0 | 0 |
T9 | 540719 | 227599 | 0 | 0 |
T10 | 10624 | 5262 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 12560289 | 6594500 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12560289 | 6594500 | 0 | 0 |
T1 | 45302 | 25142 | 0 | 0 |
T2 | 1696 | 1045 | 0 | 0 |
T3 | 5294 | 4108 | 0 | 0 |
T4 | 32774 | 19971 | 0 | 0 |
T5 | 1619 | 977 | 0 | 0 |
T6 | 3832 | 3185 | 0 | 0 |
T7 | 2901 | 1090 | 0 | 0 |
T8 | 3809 | 2670 | 0 | 0 |
T9 | 129789 | 56209 | 0 | 0 |
T10 | 2549 | 1295 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 12560289 | 6356928 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12560289 | 6356928 | 0 | 0 |
T1 | 45302 | 24995 | 0 | 0 |
T2 | 1696 | 1029 | 0 | 0 |
T3 | 5294 | 4096 | 0 | 0 |
T4 | 32774 | 19801 | 0 | 0 |
T5 | 1619 | 961 | 0 | 0 |
T6 | 3832 | 2817 | 0 | 0 |
T7 | 2901 | 850 | 0 | 0 |
T8 | 3809 | 2655 | 0 | 0 |
T9 | 129789 | 50542 | 0 | 0 |
T10 | 2549 | 1269 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 50240270 | 25585483 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 50240270 | 25585483 | 0 | 0 |
T1 | 181234 | 100710 | 0 | 0 |
T2 | 6784 | 4119 | 0 | 0 |
T3 | 21182 | 16422 | 0 | 0 |
T4 | 131106 | 79520 | 0 | 0 |
T5 | 6482 | 3849 | 0 | 0 |
T6 | 15334 | 11322 | 0 | 0 |
T7 | 11608 | 3409 | 0 | 0 |
T8 | 15238 | 10650 | 0 | 0 |
T9 | 519096 | 211927 | 0 | 0 |
T10 | 10201 | 5112 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 25121023 | 12758613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 25121023 | 12758613 | 0 | 0 |
T1 | 90615 | 50292 | 0 | 0 |
T2 | 3391 | 2059 | 0 | 0 |
T3 | 10587 | 8205 | 0 | 0 |
T4 | 65552 | 39736 | 0 | 0 |
T5 | 3241 | 1924 | 0 | 0 |
T6 | 7667 | 5749 | 0 | 0 |
T7 | 5804 | 1704 | 0 | 0 |
T8 | 7616 | 5320 | 0 | 0 |
T9 | 259568 | 109057 | 0 | 0 |
T10 | 5098 | 2551 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 25120854 | 12776022 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 25120854 | 12776022 | 0 | 0 |
T1 | 90612 | 50268 | 0 | 0 |
T2 | 3391 | 2059 | 0 | 0 |
T3 | 10588 | 8206 | 0 | 0 |
T4 | 65560 | 39739 | 0 | 0 |
T5 | 3241 | 1924 | 0 | 0 |
T6 | 7666 | 5582 | 0 | 0 |
T7 | 5804 | 1704 | 0 | 0 |
T8 | 7620 | 5324 | 0 | 0 |
T9 | 259580 | 103990 | 0 | 0 |
T10 | 5098 | 2551 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 1585816 | 789687 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1585816 | 789687 | 0 | 0 |
T1 | 5678 | 3048 | 0 | 0 |
T2 | 210 | 127 | 0 | 0 |
T3 | 661 | 504 | 0 | 0 |
T4 | 4152 | 2484 | 0 | 0 |
T5 | 202 | 119 | 0 | 0 |
T6 | 478 | 346 | 0 | 0 |
T7 | 360 | 104 | 0 | 0 |
T8 | 474 | 324 | 0 | 0 |
T9 | 16650 | 6666 | 0 | 0 |
T10 | 317 | 154 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 12560289 | 6382044 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12560289 | 6382044 | 0 | 0 |
T1 | 45302 | 24981 | 0 | 0 |
T2 | 1696 | 1029 | 0 | 0 |
T3 | 5294 | 4096 | 0 | 0 |
T4 | 32774 | 19801 | 0 | 0 |
T5 | 1619 | 961 | 0 | 0 |
T6 | 3832 | 2726 | 0 | 0 |
T7 | 2901 | 850 | 0 | 0 |
T8 | 3809 | 2655 | 0 | 0 |
T9 | 129789 | 52245 | 0 | 0 |
T10 | 2549 | 1269 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 12560289 | 6365018 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12560289 | 6365018 | 0 | 0 |
T1 | 45302 | 24995 | 0 | 0 |
T2 | 1696 | 1029 | 0 | 0 |
T3 | 5294 | 4096 | 0 | 0 |
T4 | 32774 | 19801 | 0 | 0 |
T5 | 1619 | 961 | 0 | 0 |
T6 | 3832 | 2803 | 0 | 0 |
T7 | 2901 | 850 | 0 | 0 |
T8 | 3809 | 2655 | 0 | 0 |
T9 | 129789 | 53355 | 0 | 0 |
T10 | 2549 | 1269 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 12560289 | 6367190 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12560289 | 6367190 | 0 | 0 |
T1 | 45302 | 24995 | 0 | 0 |
T2 | 1696 | 1029 | 0 | 0 |
T3 | 5294 | 4018 | 0 | 0 |
T4 | 32774 | 19801 | 0 | 0 |
T5 | 1619 | 961 | 0 | 0 |
T6 | 3832 | 2813 | 0 | 0 |
T7 | 2901 | 850 | 0 | 0 |
T8 | 3809 | 2655 | 0 | 0 |
T9 | 129789 | 51605 | 0 | 0 |
T10 | 2549 | 1269 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 1585816 | 960745 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1585816 | 960745 | 0 | 0 |
T1 | 5678 | 3518 | 0 | 0 |
T2 | 210 | 131 | 0 | 0 |
T3 | 661 | 543 | 0 | 0 |
T4 | 4152 | 2961 | 0 | 0 |
T5 | 202 | 123 | 0 | 0 |
T6 | 478 | 399 | 0 | 0 |
T7 | 360 | 138 | 0 | 0 |
T8 | 474 | 356 | 0 | 0 |
T9 | 16650 | 9895 | 0 | 0 |
T10 | 317 | 190 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 1585816 | 942929 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1585816 | 942929 | 0 | 0 |
T1 | 5678 | 3464 | 0 | 0 |
T2 | 210 | 129 | 0 | 0 |
T3 | 661 | 539 | 0 | 0 |
T4 | 4152 | 2925 | 0 | 0 |
T5 | 202 | 121 | 0 | 0 |
T6 | 478 | 397 | 0 | 0 |
T7 | 360 | 108 | 0 | 0 |
T8 | 474 | 352 | 0 | 0 |
T9 | 16650 | 9695 | 0 | 0 |
T10 | 317 | 186 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |