Toggle Coverage for Module :
prim_onehot_check
| Total | Covered | Percent |
Totals |
5 |
5 |
100.00 |
Total Bits |
54 |
54 |
100.00 |
Total Bits 0->1 |
27 |
27 |
100.00 |
Total Bits 1->0 |
27 |
27 |
100.00 |
| | | |
Ports |
5 |
5 |
100.00 |
Port Bits |
54 |
54 |
100.00 |
Port Bits 0->1 |
27 |
27 |
100.00 |
Port Bits 1->0 |
27 |
27 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T2,T3 |
INPUT |
oh_i[4:0] |
Yes |
Yes |
*T2,*T5,*T76 |
Yes |
T2,T5,T76 |
INPUT |
oh_i[6:5] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
oh_i[8:7] |
Yes |
Yes |
*T76,*T77,*T78 |
Yes |
T76,T77,T78 |
INPUT |
oh_i[10:9] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
oh_i[26:11] |
Yes |
Yes |
*T3,T6,*T11 |
Yes |
T3,T6,T11 |
INPUT |
oh_i[27] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
addr_i[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
en_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
err_o |
Yes |
Yes |
T76,T77,T78 |
Yes |
T76,T77,T78 |
OUTPUT |
*Tests covering at least one bit in the range