Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11898967	6151	0	0
alert_regwen_rd_A	11898967	5116	0	0
cpu_regwen_rd_A	11898967	5080	0	0
sw_rst_ctrl_n_0_rd_A	11898967	8675	0	0
sw_rst_ctrl_n_1_rd_A	11898967	8624	0	0
sw_rst_ctrl_n_2_rd_A	11898967	8687	0	0
sw_rst_ctrl_n_3_rd_A	11898967	8754	0	0
sw_rst_ctrl_n_4_rd_A	11898967	8667	0	0
sw_rst_ctrl_n_5_rd_A	11898967	8944	0	0
sw_rst_ctrl_n_6_rd_A	11898967	8737	0	0
sw_rst_ctrl_n_7_rd_A	11898967	8573	0	0
sw_rst_regwen_0_rd_A	11898967	5388	0	0
sw_rst_regwen_1_rd_A	11898967	5406	0	0
sw_rst_regwen_2_rd_A	11898967	5541	0	0
sw_rst_regwen_3_rd_A	11898967	5900	0	0
sw_rst_regwen_4_rd_A	11898967	5520	0	0
sw_rst_regwen_5_rd_A	11898967	5636	0	0
sw_rst_regwen_6_rd_A	11898967	5511	0	0
sw_rst_regwen_7_rd_A	11898967	5854	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11898967	6151	0	0
T70	3971	7	0	0
T71	4715	29	0	0
T72	2545	345	0	0
T73	4865	153	0	0
T74	18415	1	0	0
T80	2165	9	0	0
T92	11569	1	0	0
T96	3683	77	0	0
T97	2663	333	0	0
T100	10337	0	0	0
T102	0	13	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11898967	5116	0	0
T16	3139	0	0	0
T27	42119	0	0	0
T35	26297	0	0	0
T42	31955	18	0	0
T43	5625	0	0	0
T44	5685	0	0	0
T45	2264	0	0	0
T49	350779	577	0	0
T63	84841	69	0	0
T64	5251	0	0	0
T65	0	1	0	0
T69	0	256	0	0
T70	0	14	0	0
T85	0	72	0	0
T106	0	23	0	0
T109	0	2	0	0
T129	0	67	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11898967	5080	0	0
T16	3139	0	0	0
T27	42119	0	0	0
T35	26297	0	0	0
T42	31955	16	0	0
T43	5625	0	0	0
T44	5685	0	0	0
T45	2264	0	0	0
T49	350779	530	0	0
T63	84841	99	0	0
T64	5251	0	0	0
T69	0	241	0	0
T70	0	20	0	0
T73	0	6	0	0
T85	0	46	0	0
T106	0	49	0	0
T109	0	3	0	0
T129	0	59	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11898967	8675	0	0
T3	5101	13	0	0
T4	28605	0	0	0
T5	1577	0	0	0
T6	3789	0	0	0
T7	2714	0	0	0
T8	3670	0	0	0
T9	104052	0	0	0
T10	2213	0	0	0
T11	2661	0	0	0
T12	2669	0	0	0
T42	0	22	0	0
T43	0	2	0	0
T44	0	17	0	0
T49	0	679	0	0
T63	0	161	0	0
T64	0	26	0	0
T93	0	177	0	0
T130	0	35	0	0
T131	0	9	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11898967	8624	0	0
T3	5101	1	0	0
T4	28605	0	0	0
T5	1577	0	0	0
T6	3789	0	0	0
T7	2714	0	0	0
T8	3670	0	0	0
T9	104052	0	0	0
T10	2213	0	0	0
T11	2661	0	0	0
T12	2669	0	0	0
T42	0	34	0	0
T43	0	8	0	0
T44	0	12	0	0
T49	0	715	0	0
T63	0	186	0	0
T64	0	15	0	0
T93	0	152	0	0
T106	0	54	0	0
T130	0	31	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11898967	8687	0	0
T3	5101	7	0	0
T4	28605	0	0	0
T5	1577	0	0	0
T6	3789	0	0	0
T7	2714	0	0	0
T8	3670	0	0	0
T9	104052	0	0	0
T10	2213	0	0	0
T11	2661	0	0	0
T12	2669	0	0	0
T42	0	30	0	0
T43	0	18	0	0
T44	0	16	0	0
T49	0	663	0	0
T63	0	135	0	0
T64	0	4	0	0
T93	0	165	0	0
T130	0	23	0	0
T131	0	3	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11898967	8754	0	0
T3	5101	23	0	0
T4	28605	0	0	0
T5	1577	0	0	0
T6	3789	0	0	0
T7	2714	0	0	0
T8	3670	0	0	0
T9	104052	0	0	0
T10	2213	0	0	0
T11	2661	0	0	0
T12	2669	0	0	0
T42	0	28	0	0
T43	0	6	0	0
T44	0	17	0	0
T49	0	679	0	0
T63	0	125	0	0
T64	0	11	0	0
T93	0	175	0	0
T130	0	35	0	0
T131	0	7	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11898967	8667	0	0
T3	5101	16	0	0
T4	28605	0	0	0
T5	1577	0	0	0
T6	3789	0	0	0
T7	2714	0	0	0
T8	3670	0	0	0
T9	104052	0	0	0
T10	2213	0	0	0
T11	2661	0	0	0
T12	2669	0	0	0
T42	0	30	0	0
T43	0	19	0	0
T44	0	8	0	0
T49	0	606	0	0
T63	0	126	0	0
T64	0	9	0	0
T93	0	172	0	0
T130	0	37	0	0
T131	0	6	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11898967	8944	0	0
T3	5101	3	0	0
T4	28605	0	0	0
T5	1577	0	0	0
T6	3789	0	0	0
T7	2714	0	0	0
T8	3670	0	0	0
T9	104052	0	0	0
T10	2213	0	0	0
T11	2661	0	0	0
T12	2669	0	0	0
T42	0	16	0	0
T43	0	15	0	0
T44	0	9	0	0
T49	0	646	0	0
T63	0	164	0	0
T64	0	14	0	0
T93	0	161	0	0
T106	0	54	0	0
T130	0	48	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11898967	8737	0	0
T3	5101	3	0	0
T4	28605	0	0	0
T5	1577	0	0	0
T6	3789	0	0	0
T7	2714	0	0	0
T8	3670	0	0	0
T9	104052	0	0	0
T10	2213	0	0	0
T11	2661	0	0	0
T12	2669	0	0	0
T42	0	41	0	0
T43	0	14	0	0
T44	0	6	0	0
T49	0	640	0	0
T63	0	111	0	0
T64	0	10	0	0
T93	0	131	0	0
T130	0	21	0	0
T131	0	12	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11898967	8573	0	0
T3	5101	8	0	0
T4	28605	0	0	0
T5	1577	0	0	0
T6	3789	0	0	0
T7	2714	0	0	0
T8	3670	0	0	0
T9	104052	0	0	0
T10	2213	0	0	0
T11	2661	0	0	0
T12	2669	0	0	0
T42	0	41	0	0
T43	0	5	0	0
T44	0	6	0	0
T49	0	666	0	0
T63	0	161	0	0
T64	0	1	0	0
T93	0	182	0	0
T130	0	32	0	0
T131	0	15	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11898967	5388	0	0
T15	2292	0	0	0
T42	0	27	0	0
T43	0	4	0	0
T44	0	9	0	0
T49	350779	499	0	0
T51	3470	0	0	0
T52	104372	0	0	0
T63	0	87	0	0
T64	0	4	0	0
T75	5661	0	0	0
T85	0	63	0	0
T93	10651	31	0	0
T94	6144	0	0	0
T95	3103	0	0	0
T106	0	35	0	0
T130	3622	0	0	0
T131	0	1	0	0
T132	4173	0	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11898967	5406	0	0
T15	2292	0	0	0
T42	0	14	0	0
T43	0	1	0	0
T44	0	5	0	0
T49	350779	434	0	0
T51	3470	0	0	0
T52	104372	0	0	0
T63	0	57	0	0
T64	0	9	0	0
T75	5661	0	0	0
T84	0	9	0	0
T93	10651	38	0	0
T94	6144	0	0	0
T95	3103	0	0	0
T106	0	59	0	0
T130	3622	0	0	0
T131	0	4	0	0
T132	4173	0	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11898967	5541	0	0
T3	5101	4	0	0
T4	28605	0	0	0
T5	1577	0	0	0
T6	3789	0	0	0
T7	2714	0	0	0
T8	3670	0	0	0
T9	104052	0	0	0
T10	2213	0	0	0
T11	2661	0	0	0
T12	2669	0	0	0
T42	0	42	0	0
T43	0	1	0	0
T44	0	10	0	0
T49	0	560	0	0
T63	0	71	0	0
T64	0	9	0	0
T93	0	34	0	0
T106	0	32	0	0
T131	0	10	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11898967	5900	0	0
T3	5101	18	0	0
T4	28605	0	0	0
T5	1577	0	0	0
T6	3789	0	0	0
T7	2714	0	0	0
T8	3670	0	0	0
T9	104052	0	0	0
T10	2213	0	0	0
T11	2661	0	0	0
T12	2669	0	0	0
T42	0	38	0	0
T43	0	7	0	0
T44	0	5	0	0
T49	0	586	0	0
T63	0	117	0	0
T64	0	2	0	0
T93	0	31	0	0
T106	0	48	0	0
T131	0	2	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11898967	5520	0	0
T3	5101	1	0	0
T4	28605	0	0	0
T5	1577	0	0	0
T6	3789	0	0	0
T7	2714	0	0	0
T8	3670	0	0	0
T9	104052	0	0	0
T10	2213	0	0	0
T11	2661	0	0	0
T12	2669	0	0	0
T42	0	25	0	0
T43	0	8	0	0
T44	0	9	0	0
T49	0	607	0	0
T63	0	72	0	0
T84	0	4	0	0
T93	0	30	0	0
T106	0	47	0	0
T131	0	5	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11898967	5636	0	0
T3	5101	7	0	0
T4	28605	0	0	0
T5	1577	0	0	0
T6	3789	0	0	0
T7	2714	0	0	0
T8	3670	0	0	0
T9	104052	0	0	0
T10	2213	0	0	0
T11	2661	0	0	0
T12	2669	0	0	0
T42	0	28	0	0
T43	0	2	0	0
T44	0	4	0	0
T49	0	502	0	0
T63	0	62	0	0
T64	0	5	0	0
T93	0	32	0	0
T106	0	59	0	0
T131	0	11	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11898967	5511	0	0
T3	5101	6	0	0
T4	28605	0	0	0
T5	1577	0	0	0
T6	3789	0	0	0
T7	2714	0	0	0
T8	3670	0	0	0
T9	104052	0	0	0
T10	2213	0	0	0
T11	2661	0	0	0
T12	2669	0	0	0
T42	0	14	0	0
T43	0	5	0	0
T44	0	9	0	0
T49	0	484	0	0
T63	0	92	0	0
T64	0	6	0	0
T93	0	13	0	0
T106	0	34	0	0
T131	0	6	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11898967	5854	0	0
T3	5101	1	0	0
T4	28605	0	0	0
T5	1577	0	0	0
T6	3789	0	0	0
T7	2714	0	0	0
T8	3670	0	0	0
T9	104052	0	0	0
T10	2213	0	0	0
T11	2661	0	0	0
T12	2669	0	0	0
T42	0	45	0	0
T44	0	5	0	0
T49	0	567	0	0
T63	0	72	0	0
T64	0	13	0	0
T84	0	3	0	0
T85	0	52	0	0
T93	0	24	0	0
T106	0	60	0	0