Unified Coverage Report :: Module :: rstmgr_cnsty_chk

Module : rstmgr_cnsty_chk

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_cnsty_chk_0/rtl/rstmgr_cnsty_chk.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_rst_chk	82.35			82.35
tb.dut.u_daon_por.gen_rst_chk.u_rst_chk	100.00			100.00
tb.dut.u_daon_por_io.gen_rst_chk.u_rst_chk	100.00			100.00
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_rst_chk	100.00			100.00
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_rst_chk	100.00			100.00
tb.dut.u_daon_por_usb.gen_rst_chk.u_rst_chk	100.00			100.00
tb.dut.u_daon_lc.gen_rst_chk.u_rst_chk	100.00			100.00
tb.dut.u_d0_lc.gen_rst_chk.u_rst_chk	100.00			100.00
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_rst_chk	100.00			100.00
tb.dut.u_daon_lc_aon.gen_rst_chk.u_rst_chk	100.00			100.00
tb.dut.u_daon_lc_io.gen_rst_chk.u_rst_chk	100.00			100.00
tb.dut.u_d0_lc_io.gen_rst_chk.u_rst_chk	100.00			100.00
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_rst_chk	100.00			100.00
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_rst_chk	100.00			100.00
tb.dut.u_daon_lc_usb.gen_rst_chk.u_rst_chk	100.00			100.00
tb.dut.u_d0_lc_usb.gen_rst_chk.u_rst_chk	100.00			100.00
tb.dut.u_d0_sys.gen_rst_chk.u_rst_chk	100.00			100.00
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_rst_chk	100.00			100.00
tb.dut.u_d0_spi_device.gen_rst_chk.u_rst_chk	100.00			100.00
tb.dut.u_d0_spi_host0.gen_rst_chk.u_rst_chk	100.00			100.00
tb.dut.u_d0_spi_host1.gen_rst_chk.u_rst_chk	100.00			100.00
tb.dut.u_d0_usb.gen_rst_chk.u_rst_chk	100.00			100.00
tb.dut.u_d0_usb_aon.gen_rst_chk.u_rst_chk	100.00			100.00
tb.dut.u_d0_i2c0.gen_rst_chk.u_rst_chk	100.00			100.00
tb.dut.u_d0_i2c1.gen_rst_chk.u_rst_chk	100.00			100.00
tb.dut.u_d0_i2c2.gen_rst_chk.u_rst_chk	100.00			100.00

---

Module Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_rst_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.35			82.35

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.35			82.35

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por.gen_rst_chk.u_rst_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_rst_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_io

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_rst_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_io_div2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_rst_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_rst_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc.gen_rst_chk.u_rst_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc.gen_rst_chk.u_rst_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_rst_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_rst_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_rst_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_io

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_rst_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_io

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_rst_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_io_div2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_rst_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_io_div2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_rst_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_rst_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_sys.gen_rst_chk.u_rst_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_sys

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_rst_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_sys_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_rst_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_spi_device

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_rst_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_spi_host0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_rst_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_spi_host1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_usb.gen_rst_chk.u_rst_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_rst_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_d0_usb_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_rst_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_i2c0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_rst_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_i2c1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_rst_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_i2c2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : rstmgr_cnsty_chk

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00

Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_chk_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
parent_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
sw_rst_req_i	Yes	Yes	T1,T26,T27	Yes	T1,T26,T27	INPUT
sw_rst_req_clr_o	Yes	Yes	T1,T26,T27	Yes	T1,T26,T27	OUTPUT
err_o	Yes	Yes	T1,T24,T75	Yes	T1,T24,T75	OUTPUT
fsm_err_o	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT

Toggle Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_rst_chk

	Total	Covered	Percent
Totals	9	7	77.78
Total Bits	17	14	82.35
Total Bits 0->1	9	7	77.78
Total Bits 1->0	8	7	87.50

Ports	9	7	77.78
Port Bits	17	14	82.35
Port Bits 0->1	9	7	77.78
Port Bits 1->0	8	7	87.50

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_chk_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
parent_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
sw_rst_req_i	Unreachable	Unreachable		Unreachable		INPUT
sw_rst_req_clr_o	No	No		No		OUTPUT
err_o	No	Excluded		No		OUTPUT	1->0:VC_COV_UNR
fsm_err_o	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT

Toggle Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_rst_chk

	Total	Covered	Percent
Totals	9	9	100.00
Total Bits	18	18	100.00
Total Bits 0->1	9	9	100.00
Total Bits 1->0	9	9	100.00

Ports	9	9	100.00
Port Bits	18	18	100.00
Port Bits 0->1	9	9	100.00
Port Bits 1->0	9	9	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_chk_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
parent_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
sw_rst_req_i	Unreachable	Unreachable		Unreachable		INPUT
sw_rst_req_clr_o	Yes	Yes	T1,T26,T27	Yes	T1,T26,T27	OUTPUT
err_o	Yes	Yes	T1,T26,T27	Yes	T1,T26,T27	OUTPUT
fsm_err_o	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT

Toggle Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_rst_chk

	Total	Covered	Percent
Totals	9	9	100.00
Total Bits	18	18	100.00
Total Bits 0->1	9	9	100.00
Total Bits 1->0	9	9	100.00

Ports	9	9	100.00
Port Bits	18	18	100.00
Port Bits 0->1	9	9	100.00
Port Bits 1->0	9	9	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_chk_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
parent_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
sw_rst_req_i	Unreachable	Unreachable		Unreachable		INPUT
sw_rst_req_clr_o	Yes	Yes	T1,T26,T28	Yes	T1,T26,T28	OUTPUT
err_o	Yes	Yes	T1,T26,T27	Yes	T1,T26,T27	OUTPUT
fsm_err_o	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT

Toggle Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_rst_chk

	Total	Covered	Percent
Totals	9	9	100.00
Total Bits	18	18	100.00
Total Bits 0->1	9	9	100.00
Total Bits 1->0	9	9	100.00

Ports	9	9	100.00
Port Bits	18	18	100.00
Port Bits 0->1	9	9	100.00
Port Bits 1->0	9	9	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_chk_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
parent_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
sw_rst_req_i	Unreachable	Unreachable		Unreachable		INPUT
sw_rst_req_clr_o	Yes	Yes	T26,T35,T30	Yes	T26,T35,T30	OUTPUT
err_o	Yes	Yes	T1,T26,T27	Yes	T1,T26,T27	OUTPUT
fsm_err_o	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT

Toggle Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_rst_chk

	Total	Covered	Percent
Totals	9	9	100.00
Total Bits	18	18	100.00
Total Bits 0->1	9	9	100.00
Total Bits 1->0	9	9	100.00

Ports	9	9	100.00
Port Bits	18	18	100.00
Port Bits 0->1	9	9	100.00
Port Bits 1->0	9	9	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_chk_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
parent_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
sw_rst_req_i	Unreachable	Unreachable		Unreachable		INPUT
sw_rst_req_clr_o	Yes	Yes	T28,T29,T36	Yes	T28,T29,T36	OUTPUT
err_o	Yes	Yes	T1,T26,T27	Yes	T1,T26,T27	OUTPUT
fsm_err_o	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT

Toggle Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_rst_chk

	Total	Covered	Percent
Totals	9	9	100.00
Total Bits	18	18	100.00
Total Bits 0->1	9	9	100.00
Total Bits 1->0	9	9	100.00

Ports	9	9	100.00
Port Bits	18	18	100.00
Port Bits 0->1	9	9	100.00
Port Bits 1->0	9	9	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_chk_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
parent_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
sw_rst_req_i	Unreachable	Unreachable		Unreachable		INPUT
sw_rst_req_clr_o	Yes	Yes	T56,T29,T30	Yes	T56,T29,T30	OUTPUT
err_o	Yes	Yes	T1,T26,T27	Yes	T1,T26,T27	OUTPUT
fsm_err_o	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT

Toggle Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_rst_chk

	Total	Covered	Percent
Totals	9	9	100.00
Total Bits	18	18	100.00
Total Bits 0->1	9	9	100.00
Total Bits 1->0	9	9	100.00

Ports	9	9	100.00
Port Bits	18	18	100.00
Port Bits 0->1	9	9	100.00
Port Bits 1->0	9	9	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_chk_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
parent_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
sw_rst_req_i	Unreachable	Unreachable		Unreachable		INPUT
sw_rst_req_clr_o	Yes	Yes	T1,T26,T35	Yes	T1,T26,T35	OUTPUT
err_o	Yes	Yes	T1,T24,T75	Yes	T1,T24,T75	OUTPUT
fsm_err_o	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT

Toggle Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_rst_chk

	Total	Covered	Percent
Totals	9	9	100.00
Total Bits	18	18	100.00
Total Bits 0->1	9	9	100.00
Total Bits 1->0	9	9	100.00

Ports	9	9	100.00
Port Bits	18	18	100.00
Port Bits 0->1	9	9	100.00
Port Bits 1->0	9	9	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_chk_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
parent_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
sw_rst_req_i	Unreachable	Unreachable		Unreachable		INPUT
sw_rst_req_clr_o	Yes	Yes	T1,T56,T28	Yes	T1,T56,T28	OUTPUT
err_o	Yes	Yes	T1,T26,T27	Yes	T1,T26,T27	OUTPUT
fsm_err_o	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT

Toggle Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_rst_chk

	Total	Covered	Percent
Totals	9	9	100.00
Total Bits	18	18	100.00
Total Bits 0->1	9	9	100.00
Total Bits 1->0	9	9	100.00

Ports	9	9	100.00
Port Bits	18	18	100.00
Port Bits 0->1	9	9	100.00
Port Bits 1->0	9	9	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_chk_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
parent_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
sw_rst_req_i	Unreachable	Unreachable		Unreachable		INPUT
sw_rst_req_clr_o	Yes	Yes	T1,T35,T28	Yes	T1,T35,T28	OUTPUT
err_o	Yes	Yes	T1,T24,T75	Yes	T1,T24,T75	OUTPUT
fsm_err_o	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT

Toggle Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_rst_chk

	Total	Covered	Percent
Totals	9	9	100.00
Total Bits	18	18	100.00
Total Bits 0->1	9	9	100.00
Total Bits 1->0	9	9	100.00

Ports	9	9	100.00
Port Bits	18	18	100.00
Port Bits 0->1	9	9	100.00
Port Bits 1->0	9	9	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_chk_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
parent_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
sw_rst_req_i	Unreachable	Unreachable		Unreachable		INPUT
sw_rst_req_clr_o	Yes	Yes	T1,T33,T36	Yes	T1,T33,T36	OUTPUT
err_o	Yes	Yes	T1,T26,T27	Yes	T1,T26,T27	OUTPUT
fsm_err_o	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT

Toggle Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_rst_chk

	Total	Covered	Percent
Totals	9	9	100.00
Total Bits	18	18	100.00
Total Bits 0->1	9	9	100.00
Total Bits 1->0	9	9	100.00

Ports	9	9	100.00
Port Bits	18	18	100.00
Port Bits 0->1	9	9	100.00
Port Bits 1->0	9	9	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_chk_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
parent_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
sw_rst_req_i	Unreachable	Unreachable		Unreachable		INPUT
sw_rst_req_clr_o	Yes	Yes	T1,T26,T27	Yes	T1,T26,T27	OUTPUT
err_o	Yes	Yes	T1,T26,T27	Yes	T1,T26,T27	OUTPUT
fsm_err_o	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT

Toggle Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_rst_chk

	Total	Covered	Percent
Totals	9	9	100.00
Total Bits	18	18	100.00
Total Bits 0->1	9	9	100.00
Total Bits 1->0	9	9	100.00

Ports	9	9	100.00
Port Bits	18	18	100.00
Port Bits 0->1	9	9	100.00
Port Bits 1->0	9	9	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_chk_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
parent_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
sw_rst_req_i	Unreachable	Unreachable		Unreachable		INPUT
sw_rst_req_clr_o	Yes	Yes	T1,T27,T35	Yes	T1,T27,T35	OUTPUT
err_o	Yes	Yes	T1,T26,T27	Yes	T1,T26,T27	OUTPUT
fsm_err_o	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT

Toggle Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_rst_chk

	Total	Covered	Percent
Totals	9	9	100.00
Total Bits	18	18	100.00
Total Bits 0->1	9	9	100.00
Total Bits 1->0	9	9	100.00

Ports	9	9	100.00
Port Bits	18	18	100.00
Port Bits 0->1	9	9	100.00
Port Bits 1->0	9	9	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_chk_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
parent_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
sw_rst_req_i	Unreachable	Unreachable		Unreachable		INPUT
sw_rst_req_clr_o	Yes	Yes	T1,T27,T35	Yes	T1,T27,T35	OUTPUT
err_o	Yes	Yes	T1,T26,T27	Yes	T1,T26,T27	OUTPUT
fsm_err_o	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT

Toggle Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_rst_chk

	Total	Covered	Percent
Totals	9	9	100.00
Total Bits	18	18	100.00
Total Bits 0->1	9	9	100.00
Total Bits 1->0	9	9	100.00

Ports	9	9	100.00
Port Bits	18	18	100.00
Port Bits 0->1	9	9	100.00
Port Bits 1->0	9	9	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_chk_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
parent_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
sw_rst_req_i	Unreachable	Unreachable		Unreachable		INPUT
sw_rst_req_clr_o	Yes	Yes	T1,T27,T35	Yes	T1,T27,T35	OUTPUT
err_o	Yes	Yes	T1,T26,T27	Yes	T1,T26,T27	OUTPUT
fsm_err_o	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT

Toggle Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_rst_chk

	Total	Covered	Percent
Totals	9	9	100.00
Total Bits	18	18	100.00
Total Bits 0->1	9	9	100.00
Total Bits 1->0	9	9	100.00

Ports	9	9	100.00
Port Bits	18	18	100.00
Port Bits 0->1	9	9	100.00
Port Bits 1->0	9	9	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_chk_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
parent_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
sw_rst_req_i	Unreachable	Unreachable		Unreachable		INPUT
sw_rst_req_clr_o	Yes	Yes	T1,T27,T28	Yes	T1,T27,T28	OUTPUT
err_o	Yes	Yes	T1,T26,T27	Yes	T1,T26,T27	OUTPUT
fsm_err_o	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT

Toggle Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_rst_chk

	Total	Covered	Percent
Totals	9	9	100.00
Total Bits	18	18	100.00
Total Bits 0->1	9	9	100.00
Total Bits 1->0	9	9	100.00

Ports	9	9	100.00
Port Bits	18	18	100.00
Port Bits 0->1	9	9	100.00
Port Bits 1->0	9	9	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_chk_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
parent_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
sw_rst_req_i	Unreachable	Unreachable		Unreachable		INPUT
sw_rst_req_clr_o	Yes	Yes	T1,T35,T29	Yes	T1,T35,T29	OUTPUT
err_o	Yes	Yes	T1,T26,T27	Yes	T1,T26,T27	OUTPUT
fsm_err_o	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT

Toggle Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_rst_chk

	Total	Covered	Percent
Totals	9	9	100.00
Total Bits	18	18	100.00
Total Bits 0->1	9	9	100.00
Total Bits 1->0	9	9	100.00

Ports	9	9	100.00
Port Bits	18	18	100.00
Port Bits 0->1	9	9	100.00
Port Bits 1->0	9	9	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_chk_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
parent_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
sw_rst_req_i	Unreachable	Unreachable		Unreachable		INPUT
sw_rst_req_clr_o	Yes	Yes	T27,T56,T28	Yes	T27,T56,T28	OUTPUT
err_o	Yes	Yes	T1,T26,T27	Yes	T1,T26,T27	OUTPUT
fsm_err_o	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT

Toggle Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_rst_chk

	Total	Covered	Percent
Totals	9	9	100.00
Total Bits	18	18	100.00
Total Bits 0->1	9	9	100.00
Total Bits 1->0	9	9	100.00

Ports	9	9	100.00
Port Bits	18	18	100.00
Port Bits 0->1	9	9	100.00
Port Bits 1->0	9	9	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_chk_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
parent_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
sw_rst_req_i	Unreachable	Unreachable		Unreachable		INPUT
sw_rst_req_clr_o	Yes	Yes	T1,T26,T35	Yes	T1,T26,T35	OUTPUT
err_o	Yes	Yes	T1,T26,T27	Yes	T1,T26,T27	OUTPUT
fsm_err_o	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT

Toggle Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_rst_chk

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00

Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_chk_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
parent_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
sw_rst_req_i	Yes	Yes	T6,T9,T11	Yes	T6,T9,T11	INPUT
sw_rst_req_clr_o	Yes	Yes	T6,T9,T11	Yes	T6,T9,T11	OUTPUT
err_o	Yes	Yes	T1,T26,T27	Yes	T1,T26,T27	OUTPUT
fsm_err_o	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT

Toggle Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_rst_chk

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00

Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_chk_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
parent_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
sw_rst_req_i	Yes	Yes	T6,T9,T25	Yes	T6,T9,T25	INPUT
sw_rst_req_clr_o	Yes	Yes	T6,T9,T25	Yes	T6,T9,T25	OUTPUT
err_o	Yes	Yes	T1,T26,T27	Yes	T1,T26,T27	OUTPUT
fsm_err_o	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT

Toggle Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_rst_chk

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00

Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_chk_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
parent_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
sw_rst_req_i	Yes	Yes	T6,T9,T25	Yes	T6,T9,T25	INPUT
sw_rst_req_clr_o	Yes	Yes	T6,T9,T25	Yes	T6,T9,T25	OUTPUT
err_o	Yes	Yes	T1,T26,T27	Yes	T1,T26,T27	OUTPUT
fsm_err_o	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT

Toggle Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_rst_chk

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00

Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_chk_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
parent_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
sw_rst_req_i	Yes	Yes	T1,T6,T9	Yes	T1,T6,T9	INPUT
sw_rst_req_clr_o	Yes	Yes	T1,T6,T9	Yes	T1,T6,T9	OUTPUT
err_o	Yes	Yes	T1,T26,T27	Yes	T1,T26,T27	OUTPUT
fsm_err_o	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT

Toggle Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_rst_chk

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00

Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_chk_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
parent_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
sw_rst_req_i	Yes	Yes	T6,T9,T11	Yes	T6,T9,T11	INPUT
sw_rst_req_clr_o	Yes	Yes	T6,T9,T11	Yes	T6,T9,T11	OUTPUT
err_o	Yes	Yes	T1,T26,T27	Yes	T1,T26,T27	OUTPUT
fsm_err_o	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT

Toggle Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_rst_chk

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00

Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_chk_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
parent_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
sw_rst_req_i	Yes	Yes	T1,T6,T9	Yes	T1,T6,T9	INPUT
sw_rst_req_clr_o	Yes	Yes	T1,T6,T9	Yes	T1,T6,T9	OUTPUT
err_o	Yes	Yes	T1,T26,T27	Yes	T1,T26,T27	OUTPUT
fsm_err_o	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT

Toggle Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_rst_chk

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00

Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_chk_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
parent_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
sw_rst_req_i	Yes	Yes	T6,T9,T25	Yes	T6,T9,T25	INPUT
sw_rst_req_clr_o	Yes	Yes	T6,T9,T25	Yes	T6,T9,T25	OUTPUT
err_o	Yes	Yes	T1,T26,T27	Yes	T1,T26,T27	OUTPUT
fsm_err_o	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT

Toggle Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_rst_chk

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00

Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
child_chk_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
parent_rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
sw_rst_req_i	Yes	Yes	T3,T6,T9	Yes	T3,T6,T9	INPUT
sw_rst_req_clr_o	Yes	Yes	T3,T6,T9	Yes	T3,T6,T9	OUTPUT
err_o	Yes	Yes	T1,T26,T27	Yes	T1,T26,T27	OUTPUT
fsm_err_o	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT