Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T3,T4

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11137395	12626	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11137395	116371	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11137395	6504319	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11137395	185747	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11137395	12626	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11137395	116371	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11137395	6504319	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11137395	185747	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11137395	12626	0	0
T1	42264	75	0	0
T2	1605	0	0	0
T3	5101	4	0	0
T4	28605	33	0	0
T5	1577	0	0	0
T6	3789	0	0	0
T7	2714	0	0	0
T8	3670	4	0	0
T9	104052	223	0	0
T10	2213	4	0	0
T11	0	4	0	0
T12	0	4	0	0
T13	0	4	0	0
T23	0	34	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11137395	116371	0	0
T1	42264	717	0	0
T2	1605	0	0	0
T3	5101	37	0	0
T4	28605	303	0	0
T5	1577	0	0	0
T6	3789	0	0	0
T7	2714	0	0	0
T8	3670	38	0	0
T9	104052	2023	0	0
T10	2213	38	0	0
T11	0	37	0	0
T12	0	38	0	0
T13	0	38	0	0
T23	0	307	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11137395	6504319	0	0
T1	42264	24967	0	0
T2	1605	1031	0	0
T3	5101	4089	0	0
T4	28605	19815	0	0
T5	1577	963	0	0
T6	3789	3172	0	0
T7	2714	855	0	0
T8	3670	2651	0	0
T9	104052	55316	0	0
T10	2213	1277	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11137395	185747	0	0
T1	42264	1138	0	0
T2	1605	0	0	0
T3	5101	65	0	0
T4	28605	487	0	0
T5	1577	0	0	0
T6	3789	0	0	0
T7	2714	0	0	0
T8	3670	63	0	0
T9	104052	3248	0	0
T10	2213	52	0	0
T11	0	48	0	0
T12	0	57	0	0
T13	0	50	0	0
T23	0	503	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11137395	12626	0	0
T1	42264	75	0	0
T2	1605	0	0	0
T3	5101	4	0	0
T4	28605	33	0	0
T5	1577	0	0	0
T6	3789	0	0	0
T7	2714	0	0	0
T8	3670	4	0	0
T9	104052	223	0	0
T10	2213	4	0	0
T11	0	4	0	0
T12	0	4	0	0
T13	0	4	0	0
T23	0	34	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11137395	116371	0	0
T1	42264	717	0	0
T2	1605	0	0	0
T3	5101	37	0	0
T4	28605	303	0	0
T5	1577	0	0	0
T6	3789	0	0	0
T7	2714	0	0	0
T8	3670	38	0	0
T9	104052	2023	0	0
T10	2213	38	0	0
T11	0	37	0	0
T12	0	38	0	0
T13	0	38	0	0
T23	0	307	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11137395	6504319	0	0
T1	42264	24967	0	0
T2	1605	1031	0	0
T3	5101	4089	0	0
T4	28605	19815	0	0
T5	1577	963	0	0
T6	3789	3172	0	0
T7	2714	855	0	0
T8	3670	2651	0	0
T9	104052	55316	0	0
T10	2213	1277	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11137395	185747	0	0
T1	42264	1138	0	0
T2	1605	0	0	0
T3	5101	65	0	0
T4	28605	487	0	0
T5	1577	0	0	0
T6	3789	0	0	0
T7	2714	0	0	0
T8	3670	63	0	0
T9	104052	3248	0	0
T10	2213	52	0	0
T11	0	48	0	0
T12	0	57	0	0
T13	0	50	0	0
T23	0	503	0	0