Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T8
0	1	Covered	T3,T4,T9
1	0	Covered	T4,T9,T11

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T7
1	0	Covered	T3,T4,T8
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	52335522	8497	0	0
CascadeEffAonToRstPorAboveRise_A	52335522	8497	0	0
CascadeEffAonToRstPorIoAboveFall_A	50240270	8497	0	0
CascadeEffAonToRstPorIoAboveRise_A	50240270	8497	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25121023	8497	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25121023	8497	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12560289	8497	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12560289	8497	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25120854	8497	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25120854	8497	0	0
CascadeLcToLcAboveFall_A	52335522	21123	0	0
CascadeLcToLcAboveRise_A	52335522	21123	0	0
CascadeLcToLcAonAboveFall_A	1585816	21123	0	0
CascadeLcToLcAonAboveRise_A	1585816	21123	0	0
CascadeLcToLcShadowedAboveFall_A	52335522	21123	0	0
CascadeLcToLcShadowedAboveRise_A	52335522	21123	0	0
CascadePorToAonAboveFall_A	1585816	6902	0	0
CascadeSysToSysAboveFall_A	52335522	21123	0	0
CascadeSysToSysAboveRise_A	52335522	21123	0	0
ScanRstToAonRise_A	1585816	168	0	0
StablePorToAonRise_A	1585816	8497	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11137395	21123	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11137395	21123	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11137395	21123	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11137395	21123	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12560289	21123	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12560289	21123	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11137395	21123	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11137395	21123	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11137395	21123	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11137395	21123	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52335522	8497	0	0
T1	188760	27	0	0
T2	7067	1	0	0
T3	22063	2	0	0
T4	136568	18	0	0
T5	6753	1	0	0
T6	15974	1	0	0
T7	12092	2	0	0
T8	15876	2	0	0
T9	540719	100	0	0
T10	10624	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52335522	8497	0	0
T1	188760	27	0	0
T2	7067	1	0	0
T3	22063	2	0	0
T4	136568	18	0	0
T5	6753	1	0	0
T6	15974	1	0	0
T7	12092	2	0	0
T8	15876	2	0	0
T9	540719	100	0	0
T10	10624	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50240270	8497	0	0
T1	181234	27	0	0
T2	6784	1	0	0
T3	21182	2	0	0
T4	131106	18	0	0
T5	6482	1	0	0
T6	15334	1	0	0
T7	11608	2	0	0
T8	15238	2	0	0
T9	519096	100	0	0
T10	10201	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50240270	8497	0	0
T1	181234	27	0	0
T2	6784	1	0	0
T3	21182	2	0	0
T4	131106	18	0	0
T5	6482	1	0	0
T6	15334	1	0	0
T7	11608	2	0	0
T8	15238	2	0	0
T9	519096	100	0	0
T10	10201	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25121023	8497	0	0
T1	90615	27	0	0
T2	3391	1	0	0
T3	10587	2	0	0
T4	65552	18	0	0
T5	3241	1	0	0
T6	7667	1	0	0
T7	5804	2	0	0
T8	7616	2	0	0
T9	259568	100	0	0
T10	5098	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25121023	8497	0	0
T1	90615	27	0	0
T2	3391	1	0	0
T3	10587	2	0	0
T4	65552	18	0	0
T5	3241	1	0	0
T6	7667	1	0	0
T7	5804	2	0	0
T8	7616	2	0	0
T9	259568	100	0	0
T10	5098	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12560289	8497	0	0
T1	45302	27	0	0
T2	1696	1	0	0
T3	5294	2	0	0
T4	32774	18	0	0
T5	1619	1	0	0
T6	3832	1	0	0
T7	2901	2	0	0
T8	3809	2	0	0
T9	129789	100	0	0
T10	2549	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12560289	8497	0	0
T1	45302	27	0	0
T2	1696	1	0	0
T3	5294	2	0	0
T4	32774	18	0	0
T5	1619	1	0	0
T6	3832	1	0	0
T7	2901	2	0	0
T8	3809	2	0	0
T9	129789	100	0	0
T10	2549	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25120854	8497	0	0
T1	90612	27	0	0
T2	3391	1	0	0
T3	10588	2	0	0
T4	65560	18	0	0
T5	3241	1	0	0
T6	7666	1	0	0
T7	5804	2	0	0
T8	7620	2	0	0
T9	259580	100	0	0
T10	5098	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25120854	8497	0	0
T1	90612	27	0	0
T2	3391	1	0	0
T3	10588	2	0	0
T4	65560	18	0	0
T5	3241	1	0	0
T6	7666	1	0	0
T7	5804	2	0	0
T8	7620	2	0	0
T9	259580	100	0	0
T10	5098	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52335522	21123	0	0
T1	188760	102	0	0
T2	7067	1	0	0
T3	22063	6	0	0
T4	136568	51	0	0
T5	6753	1	0	0
T6	15974	1	0	0
T7	12092	2	0	0
T8	15876	6	0	0
T9	540719	323	0	0
T10	10624	6	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52335522	21123	0	0
T1	188760	102	0	0
T2	7067	1	0	0
T3	22063	6	0	0
T4	136568	51	0	0
T5	6753	1	0	0
T6	15974	1	0	0
T7	12092	2	0	0
T8	15876	6	0	0
T9	540719	323	0	0
T10	10624	6	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1585816	21123	0	0
T1	5678	102	0	0
T2	210	1	0	0
T3	661	6	0	0
T4	4152	51	0	0
T5	202	1	0	0
T6	478	1	0	0
T7	360	2	0	0
T8	474	6	0	0
T9	16650	323	0	0
T10	317	6	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1585816	21123	0	0
T1	5678	102	0	0
T2	210	1	0	0
T3	661	6	0	0
T4	4152	51	0	0
T5	202	1	0	0
T6	478	1	0	0
T7	360	2	0	0
T8	474	6	0	0
T9	16650	323	0	0
T10	317	6	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52335522	21123	0	0
T1	188760	102	0	0
T2	7067	1	0	0
T3	22063	6	0	0
T4	136568	51	0	0
T5	6753	1	0	0
T6	15974	1	0	0
T7	12092	2	0	0
T8	15876	6	0	0
T9	540719	323	0	0
T10	10624	6	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52335522	21123	0	0
T1	188760	102	0	0
T2	7067	1	0	0
T3	22063	6	0	0
T4	136568	51	0	0
T5	6753	1	0	0
T6	15974	1	0	0
T7	12092	2	0	0
T8	15876	6	0	0
T9	540719	323	0	0
T10	10624	6	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1585816	6902	0	0
T1	5678	27	0	0
T2	210	1	0	0
T3	661	1	0	0
T4	4152	11	0	0
T5	202	1	0	0
T6	478	1	0	0
T7	360	7	0	0
T8	474	1	0	0
T9	16650	60	0	0
T10	317	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52335522	21123	0	0
T1	188760	102	0	0
T2	7067	1	0	0
T3	22063	6	0	0
T4	136568	51	0	0
T5	6753	1	0	0
T6	15974	1	0	0
T7	12092	2	0	0
T8	15876	6	0	0
T9	540719	323	0	0
T10	10624	6	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52335522	21123	0	0
T1	188760	102	0	0
T2	7067	1	0	0
T3	22063	6	0	0
T4	136568	51	0	0
T5	6753	1	0	0
T6	15974	1	0	0
T7	12092	2	0	0
T8	15876	6	0	0
T9	540719	323	0	0
T10	10624	6	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1585816	168	0	0
T4	4152	3	0	0
T5	202	0	0	0
T6	478	0	0	0
T7	360	0	0	0
T8	474	0	0	0
T9	16650	1	0	0
T10	317	0	0	0
T11	356	0	0	0
T12	357	0	0	0
T13	316	0	0	0
T42	0	1	0	0
T49	0	6	0	0
T50	0	2	0	0
T61	0	3	0	0
T111	0	5	0	0
T133	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1585816	8497	0	0
T1	5678	27	0	0
T2	210	1	0	0
T3	661	2	0	0
T4	4152	18	0	0
T5	202	1	0	0
T6	478	1	0	0
T7	360	2	0	0
T8	474	2	0	0
T9	16650	100	0	0
T10	317	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11137395	21123	0	0
T1	42264	102	0	0
T2	1605	1	0	0
T3	5101	6	0	0
T4	28605	51	0	0
T5	1577	1	0	0
T6	3789	1	0	0
T7	2714	2	0	0
T8	3670	6	0	0
T9	104052	323	0	0
T10	2213	6	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11137395	21123	0	0
T1	42264	102	0	0
T2	1605	1	0	0
T3	5101	6	0	0
T4	28605	51	0	0
T5	1577	1	0	0
T6	3789	1	0	0
T7	2714	2	0	0
T8	3670	6	0	0
T9	104052	323	0	0
T10	2213	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11137395	21123	0	0
T1	42264	102	0	0
T2	1605	1	0	0
T3	5101	6	0	0
T4	28605	51	0	0
T5	1577	1	0	0
T6	3789	1	0	0
T7	2714	2	0	0
T8	3670	6	0	0
T9	104052	323	0	0
T10	2213	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11137395	21123	0	0
T1	42264	102	0	0
T2	1605	1	0	0
T3	5101	6	0	0
T4	28605	51	0	0
T5	1577	1	0	0
T6	3789	1	0	0
T7	2714	2	0	0
T8	3670	6	0	0
T9	104052	323	0	0
T10	2213	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12560289	21123	0	0
T1	45302	102	0	0
T2	1696	1	0	0
T3	5294	6	0	0
T4	32774	51	0	0
T5	1619	1	0	0
T6	3832	1	0	0
T7	2901	2	0	0
T8	3809	6	0	0
T9	129789	323	0	0
T10	2549	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12560289	21123	0	0
T1	45302	102	0	0
T2	1696	1	0	0
T3	5294	6	0	0
T4	32774	51	0	0
T5	1619	1	0	0
T6	3832	1	0	0
T7	2901	2	0	0
T8	3809	6	0	0
T9	129789	323	0	0
T10	2549	6	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11137395	21123	0	0
T1	42264	102	0	0
T2	1605	1	0	0
T3	5101	6	0	0
T4	28605	51	0	0
T5	1577	1	0	0
T6	3789	1	0	0
T7	2714	2	0	0
T8	3670	6	0	0
T9	104052	323	0	0
T10	2213	6	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11137395	21123	0	0
T1	42264	102	0	0
T2	1605	1	0	0
T3	5101	6	0	0
T4	28605	51	0	0
T5	1577	1	0	0
T6	3789	1	0	0
T7	2714	2	0	0
T8	3670	6	0	0
T9	104052	323	0	0
T10	2213	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11137395	21123	0	0
T1	42264	102	0	0
T2	1605	1	0	0
T3	5101	6	0	0
T4	28605	51	0	0
T5	1577	1	0	0
T6	3789	1	0	0
T7	2714	2	0	0
T8	3670	6	0	0
T9	104052	323	0	0
T10	2213	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11137395	21123	0	0
T1	42264	102	0	0
T2	1605	1	0	0
T3	5101	6	0	0
T4	28605	51	0	0
T5	1577	1	0	0
T6	3789	1	0	0
T7	2714	2	0	0
T8	3670	6	0	0
T9	104052	323	0	0
T10	2213	6	0	0