Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T11,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T51,T52
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T11,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T51,T86
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T51
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T12,T51
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T12,T51
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T51
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12024033	13334	0	0
gen_assertions[0].RstEnOn_A	12024033	991	0	0
gen_assertions[0].RstNOff_A	12024033	13334	0	0
gen_assertions[0].RstNOn_A	12024033	991	0	0
gen_assertions[1].RstEnOff_A	48095554	12122	0	0
gen_assertions[1].RstEnOn_A	48095554	960	0	0
gen_assertions[1].RstNOff_A	48095554	12122	0	0
gen_assertions[1].RstNOn_A	48095554	960	0	0
gen_assertions[2].RstEnOff_A	24048534	12188	0	0
gen_assertions[2].RstEnOn_A	24048534	982	0	0
gen_assertions[2].RstNOff_A	24048534	12188	0	0
gen_assertions[2].RstNOn_A	24048534	982	0	0
gen_assertions[3].RstEnOff_A	24048569	12232	0	0
gen_assertions[3].RstEnOn_A	24048569	1014	0	0
gen_assertions[3].RstNOff_A	24048569	12232	0	0
gen_assertions[3].RstNOn_A	24048569	1014	0	0
gen_assertions[4].RstEnOff_A	1518377	20524	0	0
gen_assertions[4].RstEnOn_A	1518377	1052	0	0
gen_assertions[4].RstNOff_A	1518377	20524	0	0
gen_assertions[4].RstNOn_A	1518377	1052	0	0
gen_assertions[5].RstEnOff_A	12024033	13583	0	0
gen_assertions[5].RstEnOn_A	12024033	1112	0	0
gen_assertions[5].RstNOff_A	12024033	13583	0	0
gen_assertions[5].RstNOn_A	12024033	1112	0	0
gen_assertions[6].RstEnOff_A	12024033	13651	0	0
gen_assertions[6].RstEnOn_A	12024033	1167	0	0
gen_assertions[6].RstNOff_A	12024033	13651	0	0
gen_assertions[6].RstNOn_A	12024033	1167	0	0
gen_assertions[7].RstEnOff_A	12024033	13678	0	0
gen_assertions[7].RstEnOn_A	12024033	1204	0	0
gen_assertions[7].RstNOff_A	12024033	13678	0	0
gen_assertions[7].RstNOn_A	12024033	1204	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12024033	13334	0	0
T1	45453	75	0	0
T2	3030	0	0	0
T3	29544	75	0	0
T4	2139	0	0	0
T5	3131	0	0	0
T6	6789	19	0	0
T7	35289	33	0	0
T8	5010	4	0	0
T9	55916	75	0	0
T10	1531	0	0	0
T11	0	5	0	0
T12	0	7	0	0
T21	0	75	0	0
T22	0	4	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12024033	991	0	0
T6	6789	3	0	0
T7	35289	0	0	0
T8	5010	0	0	0
T9	55916	0	0	0
T10	1531	0	0	0
T11	4808	1	0	0
T12	3348	7	0	0
T13	1768	0	0	0
T38	0	1	0	0
T40	0	2	0	0
T45	1706	0	0	0
T51	0	2	0	0
T52	0	6	0	0
T68	1818	0	0	0
T86	0	1	0	0
T87	0	7	0	0
T88	0	4	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12024033	13334	0	0
T1	45453	75	0	0
T2	3030	0	0	0
T3	29544	75	0	0
T4	2139	0	0	0
T5	3131	0	0	0
T6	6789	19	0	0
T7	35289	33	0	0
T8	5010	4	0	0
T9	55916	75	0	0
T10	1531	0	0	0
T11	0	5	0	0
T12	0	7	0	0
T21	0	75	0	0
T22	0	4	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12024033	991	0	0
T6	6789	3	0	0
T7	35289	0	0	0
T8	5010	0	0	0
T9	55916	0	0	0
T10	1531	0	0	0
T11	4808	1	0	0
T12	3348	7	0	0
T13	1768	0	0	0
T38	0	1	0	0
T40	0	2	0	0
T45	1706	0	0	0
T51	0	2	0	0
T52	0	6	0	0
T68	1818	0	0	0
T86	0	1	0	0
T87	0	7	0	0
T88	0	4	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48095554	12122	0	0
T1	181825	70	0	0
T2	12127	0	0	0
T3	118137	73	0	0
T4	8556	0	0	0
T5	12525	0	0	0
T6	27156	15	0	0
T7	141163	30	0	0
T8	20040	4	0	0
T9	223654	65	0	0
T10	6129	0	0	0
T11	0	4	0	0
T12	0	6	0	0
T21	0	65	0	0
T22	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48095554	960	0	0
T12	13393	6	0	0
T13	7079	0	0	0
T21	117564	0	0	0
T22	10517	0	0	0
T23	117732	0	0	0
T38	0	2	0	0
T40	0	4	0	0
T42	0	4	0	0
T43	0	18	0	0
T45	6827	0	0	0
T51	10805	2	0	0
T52	0	7	0	0
T68	7275	0	0	0
T78	91130	0	0	0
T83	5514	0	0	0
T87	0	8	0	0
T88	0	7	0	0
T89	0	5	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48095554	12122	0	0
T1	181825	70	0	0
T2	12127	0	0	0
T3	118137	73	0	0
T4	8556	0	0	0
T5	12525	0	0	0
T6	27156	15	0	0
T7	141163	30	0	0
T8	20040	4	0	0
T9	223654	65	0	0
T10	6129	0	0	0
T11	0	4	0	0
T12	0	6	0	0
T21	0	65	0	0
T22	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48095554	960	0	0
T12	13393	6	0	0
T13	7079	0	0	0
T21	117564	0	0	0
T22	10517	0	0	0
T23	117732	0	0	0
T38	0	2	0	0
T40	0	4	0	0
T42	0	4	0	0
T43	0	18	0	0
T45	6827	0	0	0
T51	10805	2	0	0
T52	0	7	0	0
T68	7275	0	0	0
T78	91130	0	0	0
T83	5514	0	0	0
T87	0	8	0	0
T88	0	7	0	0
T89	0	5	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24048534	12188	0	0
T1	90904	70	0	0
T2	6064	0	0	0
T3	59083	73	0	0
T4	4278	0	0	0
T5	6261	0	0	0
T6	13578	15	0	0
T7	70577	30	0	0
T8	10023	5	0	0
T9	111825	65	0	0
T10	3064	0	0	0
T11	0	5	0	0
T12	0	8	0	0
T21	0	65	0	0
T22	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24048534	982	0	0
T8	10023	1	0	0
T9	111825	0	0	0
T10	3064	0	0	0
T11	9620	1	0	0
T12	6696	8	0	0
T13	3539	0	0	0
T21	58773	0	0	0
T38	0	4	0	0
T40	0	5	0	0
T42	0	4	0	0
T45	3413	0	0	0
T51	0	3	0	0
T52	0	10	0	0
T68	3637	0	0	0
T83	2757	0	0	0
T87	0	8	0	0
T88	0	8	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24048534	12188	0	0
T1	90904	70	0	0
T2	6064	0	0	0
T3	59083	73	0	0
T4	4278	0	0	0
T5	6261	0	0	0
T6	13578	15	0	0
T7	70577	30	0	0
T8	10023	5	0	0
T9	111825	65	0	0
T10	3064	0	0	0
T11	0	5	0	0
T12	0	8	0	0
T21	0	65	0	0
T22	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24048534	982	0	0
T8	10023	1	0	0
T9	111825	0	0	0
T10	3064	0	0	0
T11	9620	1	0	0
T12	6696	8	0	0
T13	3539	0	0	0
T21	58773	0	0	0
T38	0	4	0	0
T40	0	5	0	0
T42	0	4	0	0
T45	3413	0	0	0
T51	0	3	0	0
T52	0	10	0	0
T68	3637	0	0	0
T83	2757	0	0	0
T87	0	8	0	0
T88	0	8	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24048569	12232	0	0
T1	90918	70	0	0
T2	6064	0	0	0
T3	59093	73	0	0
T4	4278	0	0	0
T5	6262	0	0	0
T6	13578	15	0	0
T7	70573	30	0	0
T8	10024	4	0	0
T9	111834	65	0	0
T10	3063	0	0	0
T11	0	4	0	0
T12	0	8	0	0
T21	0	65	0	0
T22	0	4	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24048569	1014	0	0
T12	6697	8	0	0
T13	3539	0	0	0
T21	58774	0	0	0
T22	5256	0	0	0
T23	58853	0	0	0
T38	0	6	0	0
T40	0	5	0	0
T42	0	6	0	0
T45	3413	0	0	0
T51	5402	4	0	0
T52	0	11	0	0
T68	3637	0	0	0
T78	45568	0	0	0
T83	2757	0	0	0
T86	0	1	0	0
T87	0	9	0	0
T88	0	9	0	0
T90	0	1	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24048569	12232	0	0
T1	90918	70	0	0
T2	6064	0	0	0
T3	59093	73	0	0
T4	4278	0	0	0
T5	6262	0	0	0
T6	13578	15	0	0
T7	70573	30	0	0
T8	10024	4	0	0
T9	111834	65	0	0
T10	3063	0	0	0
T11	0	4	0	0
T12	0	8	0	0
T21	0	65	0	0
T22	0	4	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24048569	1014	0	0
T12	6697	8	0	0
T13	3539	0	0	0
T21	58774	0	0	0
T22	5256	0	0	0
T23	58853	0	0	0
T38	0	6	0	0
T40	0	5	0	0
T42	0	6	0	0
T45	3413	0	0	0
T51	5402	4	0	0
T52	0	11	0	0
T68	3637	0	0	0
T78	45568	0	0	0
T83	2757	0	0	0
T86	0	1	0	0
T87	0	9	0	0
T88	0	9	0	0
T90	0	1	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1518377	20524	0	0
T1	5696	90	0	0
T2	378	2	0	0
T3	3708	77	0	0
T4	266	1	0	0
T5	390	2	0	0
T6	847	19	0	0
T7	4471	53	0	0
T8	624	6	0	0
T9	7004	99	0	0
T10	191	1	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1518377	1052	0	0
T11	600	1	0	0
T12	417	10	0	0
T13	219	0	0	0
T21	3689	0	0	0
T22	327	0	0	0
T23	3692	0	0	0
T38	0	5	0	0
T40	0	6	0	0
T42	0	7	0	0
T45	213	0	0	0
T51	0	5	0	0
T52	0	10	0	0
T68	227	0	0	0
T78	2919	0	0	0
T83	170	0	0	0
T86	0	1	0	0
T87	0	12	0	0
T88	0	8	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1518377	20524	0	0
T1	5696	90	0	0
T2	378	2	0	0
T3	3708	77	0	0
T4	266	1	0	0
T5	390	2	0	0
T6	847	19	0	0
T7	4471	53	0	0
T8	624	6	0	0
T9	7004	99	0	0
T10	191	1	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1518377	1052	0	0
T11	600	1	0	0
T12	417	10	0	0
T13	219	0	0	0
T21	3689	0	0	0
T22	327	0	0	0
T23	3692	0	0	0
T38	0	5	0	0
T40	0	6	0	0
T42	0	7	0	0
T45	213	0	0	0
T51	0	5	0	0
T52	0	10	0	0
T68	227	0	0	0
T78	2919	0	0	0
T83	170	0	0	0
T86	0	1	0	0
T87	0	12	0	0
T88	0	8	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12024033	13583	0	0
T1	45453	75	0	0
T2	3030	0	0	0
T3	29544	75	0	0
T4	2139	0	0	0
T5	3131	0	0	0
T6	6789	19	0	0
T7	35289	33	0	0
T8	5010	5	0	0
T9	55916	75	0	0
T10	1531	0	0	0
T11	0	4	0	0
T12	0	11	0	0
T21	0	75	0	0
T22	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12024033	1112	0	0
T8	5010	1	0	0
T9	55916	0	0	0
T10	1531	0	0	0
T11	4808	0	0	0
T12	3348	11	0	0
T13	1768	0	0	0
T21	29396	0	0	0
T38	0	7	0	0
T40	0	7	0	0
T42	0	8	0	0
T43	0	16	0	0
T45	1706	0	0	0
T51	0	7	0	0
T52	0	12	0	0
T68	1818	0	0	0
T83	1377	0	0	0
T87	0	12	0	0
T88	0	11	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12024033	13583	0	0
T1	45453	75	0	0
T2	3030	0	0	0
T3	29544	75	0	0
T4	2139	0	0	0
T5	3131	0	0	0
T6	6789	19	0	0
T7	35289	33	0	0
T8	5010	5	0	0
T9	55916	75	0	0
T10	1531	0	0	0
T11	0	4	0	0
T12	0	11	0	0
T21	0	75	0	0
T22	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12024033	1112	0	0
T8	5010	1	0	0
T9	55916	0	0	0
T10	1531	0	0	0
T11	4808	0	0	0
T12	3348	11	0	0
T13	1768	0	0	0
T21	29396	0	0	0
T38	0	7	0	0
T40	0	7	0	0
T42	0	8	0	0
T43	0	16	0	0
T45	1706	0	0	0
T51	0	7	0	0
T52	0	12	0	0
T68	1818	0	0	0
T83	1377	0	0	0
T87	0	12	0	0
T88	0	11	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12024033	13651	0	0
T1	45453	75	0	0
T2	3030	0	0	0
T3	29544	75	0	0
T4	2139	0	0	0
T5	3131	0	0	0
T6	6789	19	0	0
T7	35289	33	0	0
T8	5010	5	0	0
T9	55916	75	0	0
T10	1531	0	0	0
T11	0	4	0	0
T12	0	12	0	0
T21	0	75	0	0
T22	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12024033	1167	0	0
T8	5010	1	0	0
T9	55916	0	0	0
T10	1531	0	0	0
T11	4808	0	0	0
T12	3348	12	0	0
T13	1768	0	0	0
T21	29396	0	0	0
T38	0	8	0	0
T40	0	9	0	0
T42	0	9	0	0
T45	1706	0	0	0
T51	0	8	0	0
T52	0	12	0	0
T68	1818	0	0	0
T83	1377	0	0	0
T86	0	1	0	0
T87	0	13	0	0
T88	0	11	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12024033	13651	0	0
T1	45453	75	0	0
T2	3030	0	0	0
T3	29544	75	0	0
T4	2139	0	0	0
T5	3131	0	0	0
T6	6789	19	0	0
T7	35289	33	0	0
T8	5010	5	0	0
T9	55916	75	0	0
T10	1531	0	0	0
T11	0	4	0	0
T12	0	12	0	0
T21	0	75	0	0
T22	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12024033	1167	0	0
T8	5010	1	0	0
T9	55916	0	0	0
T10	1531	0	0	0
T11	4808	0	0	0
T12	3348	12	0	0
T13	1768	0	0	0
T21	29396	0	0	0
T38	0	8	0	0
T40	0	9	0	0
T42	0	9	0	0
T45	1706	0	0	0
T51	0	8	0	0
T52	0	12	0	0
T68	1818	0	0	0
T83	1377	0	0	0
T86	0	1	0	0
T87	0	13	0	0
T88	0	11	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12024033	13678	0	0
T1	45453	75	0	0
T2	3030	0	0	0
T3	29544	75	0	0
T4	2139	0	0	0
T5	3131	0	0	0
T6	6789	19	0	0
T7	35289	33	0	0
T8	5010	4	0	0
T9	55916	75	0	0
T10	1531	0	0	0
T11	0	5	0	0
T12	0	14	0	0
T21	0	75	0	0
T22	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12024033	1204	0	0
T11	4808	1	0	0
T12	3348	14	0	0
T13	1768	0	0	0
T21	29396	0	0	0
T22	2627	0	0	0
T23	29426	0	0	0
T38	0	10	0	0
T40	0	9	0	0
T42	0	11	0	0
T45	1706	0	0	0
T51	0	7	0	0
T52	0	15	0	0
T59	0	1	0	0
T68	1818	0	0	0
T78	22778	0	0	0
T83	1377	0	0	0
T87	0	13	0	0
T88	0	13	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12024033	13678	0	0
T1	45453	75	0	0
T2	3030	0	0	0
T3	29544	75	0	0
T4	2139	0	0	0
T5	3131	0	0	0
T6	6789	19	0	0
T7	35289	33	0	0
T8	5010	4	0	0
T9	55916	75	0	0
T10	1531	0	0	0
T11	0	5	0	0
T12	0	14	0	0
T21	0	75	0	0
T22	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12024033	1204	0	0
T11	4808	1	0	0
T12	3348	14	0	0
T13	1768	0	0	0
T21	29396	0	0	0
T22	2627	0	0	0
T23	29426	0	0	0
T38	0	10	0	0
T40	0	9	0	0
T42	0	11	0	0
T45	1706	0	0	0
T51	0	7	0	0
T52	0	15	0	0
T59	0	1	0	0
T68	1818	0	0	0
T78	22778	0	0	0
T83	1377	0	0	0
T87	0	13	0	0
T88	0	13	0	0