SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
99.58 | 99.40 | 99.31 | 99.88 | 99.83 | 99.46 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
tb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_alert_tx[0].u_prim_alert_sender | 100.00 | 100.00 | |||||
gen_alert_tx[1].u_prim_alert_sender | 100.00 | 100.00 | |||||
gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender | 100.00 | 100.00 | 100.00 | 100.00 | |||
gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon | 96.65 | 95.83 | 97.44 | 93.33 | 100.00 | ||
gen_rst_por_aon[0].u_por_scanmode_sync | 100.00 | 100.00 | 100.00 | ||||
gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux | 100.00 | 100.00 | 100.00 | 100.00 | |||
gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_sync | 100.00 | 100.00 | 100.00 | ||||
gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender | 100.00 | 100.00 | 100.00 | 100.00 | |||
gen_rst_por_aon[1].u_por_scanmode_sync | 100.00 | 100.00 | 100.00 | ||||
pwrmgr_rstmgr_sva_if | 100.00 | 100.00 | 100.00 | 100.00 | |||
rstmgr_attrs_sva_if | 100.00 | 100.00 | |||||
rstmgr_cascading_sva_if | 100.00 | 100.00 | 100.00 | 100.00 | |||
rstmgr_csr_assert | 100.00 | 100.00 | |||||
rstmgr_rst_en_track_sva_if | 92.86 | 92.86 | |||||
rstmgr_sw_rst_sva_if | 100.00 | 100.00 | 100.00 | 100.00 | |||
tlul_assert_device | 100.00 | 100.00 | 100.00 | 100.00 | |||
u_alert_info | 100.00 | 100.00 | 100.00 | 100.00 | |||
u_cpu_info | 100.00 | 100.00 | 100.00 | 100.00 | |||
u_ctrl_scanmode_sync | 100.00 | 100.00 | 100.00 | ||||
u_d0_i2c0 | 99.29 | 100.00 | 96.43 | 100.00 | 100.00 | 100.00 | |
u_d0_i2c1 | 99.29 | 100.00 | 96.43 | 100.00 | 100.00 | 100.00 | |
u_d0_i2c2 | 99.29 | 100.00 | 96.43 | 100.00 | 100.00 | 100.00 | |
u_d0_lc | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | |
u_d0_lc_io | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | |
u_d0_lc_io_div2 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | |
u_d0_lc_io_div4 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | ||
u_d0_lc_io_div4_shadowed | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | ||
u_d0_lc_shadowed | 96.47 | 100.00 | 100.00 | 82.35 | 100.00 | 100.00 | |
u_d0_lc_usb | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | |
u_d0_spi_device | 99.29 | 100.00 | 96.43 | 100.00 | 100.00 | 100.00 | |
u_d0_spi_host0 | 99.29 | 100.00 | 96.43 | 100.00 | 100.00 | 100.00 | |
u_d0_spi_host1 | 99.29 | 100.00 | 96.43 | 100.00 | 100.00 | 100.00 | |
u_d0_sys | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | |
u_d0_usb | 99.29 | 100.00 | 96.43 | 100.00 | 100.00 | 100.00 | |
u_d0_usb_aon | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | |
u_daon_lc | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | |
u_daon_lc_aon | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | |
u_daon_lc_io | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | |
u_daon_lc_io_div2 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | |
u_daon_lc_io_div4 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | ||
u_daon_lc_io_div4_shadowed | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | ||
u_daon_lc_shadowed | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | |
u_daon_lc_usb | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | |
u_daon_por | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | |
u_daon_por_io | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | |
u_daon_por_io_div2 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | |
u_daon_por_io_div4 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | |
u_daon_por_usb | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | |
u_daon_sys_io_div4 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | |
u_lc_src | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | ||
u_por_clk_buf | 100.00 | 100.00 | |||||
u_por_rst_buf | 100.00 | 100.00 | |||||
u_reg | 99.65 | 98.40 | 99.85 | 100.00 | 100.00 | 100.00 | |
u_sys_src | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 23 | 23 | 100.00 | |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 202 | 1 | 1 | 100.00 |
CONT_ASSIGN | 204 | 1 | 1 | 100.00 |
CONT_ASSIGN | 207 | 1 | 1 | 100.00 |
CONT_ASSIGN | 214 | 1 | 1 | 100.00 |
CONT_ASSIGN | 217 | 1 | 1 | 100.00 |
CONT_ASSIGN | 219 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 286 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1195 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1199 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1203 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1208 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1214 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1218 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1220 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1227 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1260 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1262 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
148 | 1 | 1 | |
202 | 1 | 1 | |
204 | 1 | 1 | |
207 | 1 | 1 | |
214 | 1 | 1 | |
217 | 1 | 1 | |
219 | 1 | 1 | |
285 | 1 | 1 | |
286 | 1 | 1 | |
1188 | 1 | 1 | |
1193 | 1 | 1 | |
1195 | 1 | 1 | |
1199 | 1 | 1 | |
1203 | 1 | 1 | |
1208 | 1 | 1 | |
1212 | 1 | 1 | |
1214 | 1 | 1 | |
1218 | 1 | 1 | |
1220 | 1 | 1 | |
1227 | 1 | 1 | |
1231 | 1 | 1 | |
1260 | 1 | 1 | |
1262 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 56 | 55 | 98.21 |
Logical | 56 | 55 | 98.21 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 37 SUB-EXPRESSION (rst_en_o.i2c2[1] == MuBi4True) ---------------1---------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 37 SUB-EXPRESSION (rst_en_o.i2c1[1] == MuBi4True) ---------------1---------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 37 SUB-EXPRESSION (rst_en_o.i2c0[1] == MuBi4True) ---------------1---------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 37 SUB-EXPRESSION (rst_en_o.usb_aon[1] == MuBi4True) -----------------1----------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 37 SUB-EXPRESSION (rst_en_o.usb[1] == MuBi4True) ---------------1--------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 37 SUB-EXPRESSION (rst_en_o.spi_host1[1] == MuBi4True) ------------------1-----------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 37 SUB-EXPRESSION (rst_en_o.spi_host0[1] == MuBi4True) ------------------1-----------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 37 SUB-EXPRESSION (rst_en_o.spi_device[1] == MuBi4True) ------------------1------------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 120 EXPRESSION (rst_por_aon_n[rstmgr_pkg::DomainAonSel] & por_n_i[1]) -------------------1------------------- -----2----
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 204 EXPRESSION (((|cnsty_chk_errs)) || ((|shadow_cnsty_chk_errs))) ---------1--------- -------------2------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T9 |
1 | 0 | Covered | T1,T3,T9 |
LINE 207 EXPRESSION (((|fsm_errs)) || ((|shadow_fsm_errs))) ------1------ ----------2---------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T65,T66,T67 |
1 | 0 | Covered | T65,T66,T67 |
LINE 214 EXPRESSION (reg2hw.err_code.reg_intg_err.q | ((|reg2hw.err_code.fsm_err.q))) ---------------1-------------- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T65,T66,T67 |
1 | 0 | Covered | T65,T66,T67 |
LINE 219 SUB-EXPRESSION (reg2hw.alert_test.fatal_cnsty_fault.q & reg2hw.alert_test.fatal_cnsty_fault.qe) ------------------1------------------ -------------------2------------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T4,T10,T68 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T10,T68 |
LINE 219 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault.q & reg2hw.alert_test.fatal_fault.qe) ---------------1--------------- ----------------2---------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T4,T10,T68 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T4,T10,T68 |
LINE 1188 EXPRESSION (((|pwr_i.rst_lc_req)) || ((|pwr_i.rst_sys_req))) ----------1---------- -----------2----------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered |
LINE 1193 EXPRESSION (pwrmgr_rst_req & (pwr_i.reset_cause == HwReq)) -------1------ --------------2-------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T6 |
LINE 1193 SUB-EXPRESSION (pwr_i.reset_cause == HwReq) --------------1-------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T6 |
LINE 1195 EXPRESSION (pwrmgr_rst_req & (pwr_i.reset_cause == LowPwrEntry)) -------1------ -----------------2----------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T3,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T7 |
LINE 1195 SUB-EXPRESSION (pwr_i.reset_cause == LowPwrEntry) -----------------1----------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
LINE 1227 EXPRESSION (rst_hw_req | rst_low_power) -----1---- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T7 |
1 | 0 | Covered | T1,T3,T6 |
LINE 1235 EXPRESSION (dump_capture & reg2hw.alert_info_ctrl.en.q) ------1----- -------------2-------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 1247 EXPRESSION (dump_capture & reg2hw.cpu_info_ctrl.en.q) ------1----- ------------2------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
Total | Covered | Percent | |
---|---|---|---|
Totals | 84 | 68 | 80.95 |
Total Bits | 1482 | 1450 | 97.84 |
Total Bits 0->1 | 741 | 725 | 97.84 |
Total Bits 1->0 | 741 | 725 | 97.84 |
Ports | 84 | 68 | 80.95 |
Port Bits | 1482 | 1450 | 97.84 |
Port Bits 0->1 | 741 | 725 | 97.84 |
Port Bits 1->0 | 741 | 725 | 97.84 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
clk_aon_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
clk_io_div4_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
clk_main_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
clk_io_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
clk_io_div2_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
clk_usb_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
clk_por_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_por_ni | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
por_n_i[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
tl_i.d_ready | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
tl_i.a_user.data_intg[6:0] | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | INPUT |
tl_i.a_user.cmd_intg[6:0] | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | INPUT |
tl_i.a_user.instr_type[3:0] | Yes | Yes | T7,T8,T10 | Yes | T7,T8,T10 | INPUT |
tl_i.a_user.rsvd[4:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
tl_i.a_data[31:0] | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | INPUT |
tl_i.a_mask[3:0] | Yes | Yes | T1,T3,T6 | Yes | T1,T3,T6 | INPUT |
tl_i.a_address[31:0] | Yes | Yes | T1,T3,T6 | Yes | T1,T3,T6 | INPUT |
tl_i.a_source[7:0] | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | INPUT |
tl_i.a_size[1:0] | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | INPUT |
tl_i.a_param[2:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
tl_i.a_opcode[2:0] | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | INPUT |
tl_i.a_valid | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
tl_o.a_ready | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
tl_o.d_error | Yes | Yes | T57,T60,T61 | Yes | T57,T60,T61 | OUTPUT |
tl_o.d_user.data_intg[6:0] | Yes | Yes | T1,T3,T6 | Yes | T1,T2,T3 | OUTPUT |
tl_o.d_user.rsp_intg[5:0] | Yes | Yes | *T1,*T3,*T4 | Yes | T1,T3,T4 | OUTPUT |
tl_o.d_user.rsp_intg[6] | Unreachable | Unreachable | Unreachable | OUTPUT | ||
tl_o.d_data[31:0] | Yes | Yes | T1,T3,T6 | Yes | T1,T2,T3 | OUTPUT |
tl_o.d_sink | Unreachable | Unreachable | Unreachable | OUTPUT | ||
tl_o.d_source[7:0] | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | OUTPUT |
tl_o.d_size[1:0] | Yes | Yes | T1,T3,T4 | Yes | T1,T2,T3 | OUTPUT |
tl_o.d_param[2:0] | Unreachable | Unreachable | Unreachable | OUTPUT | ||
tl_o.d_opcode[0] | Yes | Yes | *T1,*T3,*T6 | Yes | T1,T2,T3 | OUTPUT |
tl_o.d_opcode[2:1] | Unreachable | Unreachable | Unreachable | OUTPUT | ||
tl_o.d_valid | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_rx_i[0].ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_rx_i[0].ack_p | Yes | Yes | T4,T10,T68 | Yes | T4,T10,T68 | INPUT |
alert_rx_i[0].ping_n | Unreachable | Unreachable | Unreachable | INPUT | ||
alert_rx_i[0].ping_p | Unreachable | Unreachable | Unreachable | INPUT | ||
alert_rx_i[1].ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_rx_i[1].ack_p | Yes | Yes | T1,T4,T10 | Yes | T1,T4,T10 | INPUT |
alert_rx_i[1].ping_n | Unreachable | Unreachable | Unreachable | INPUT | ||
alert_rx_i[1].ping_p | Unreachable | Unreachable | Unreachable | INPUT | ||
alert_tx_o[0].alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_tx_o[0].alert_p | Yes | Yes | T4,T10,T68 | Yes | T4,T10,T68 | OUTPUT |
alert_tx_o[1].alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_tx_o[1].alert_p | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | OUTPUT |
pwr_i.reset_cause[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
pwr_i.rstreqs[4:0] | Yes | Yes | T1,T3,T6 | Yes | T1,T3,T6 | INPUT |
pwr_i.rst_sys_req[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
pwr_i.rst_lc_req[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
pwr_o.rst_sys_src_n[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
pwr_o.rst_lc_src_n[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
sw_rst_req_o[3:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | OUTPUT |
alert_dump_i.class_esc_cnt[0][12:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.class_esc_cnt[0][13] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.class_esc_cnt[0][24:14] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.class_esc_cnt[0][25] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.class_esc_cnt[0][31:26] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.class_esc_cnt[1][7:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.class_esc_cnt[1][8] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.class_esc_cnt[1][24:9] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.class_esc_cnt[1][25] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.class_esc_cnt[1][27:26] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.class_esc_cnt[1][28] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.class_esc_cnt[1][31:29] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.class_esc_cnt[2][0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.class_esc_cnt[2][2:1] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.class_esc_cnt[2][3] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.class_esc_cnt[2][22:4] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.class_esc_cnt[2][23] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.class_esc_cnt[2][31:24] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.class_esc_cnt[3][6:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.class_esc_cnt[3][7] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.class_esc_cnt[3][31:8] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.class_accum_cnt[0][15:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.class_accum_cnt[1][0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.class_accum_cnt[1][15:1] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.class_accum_cnt[2][6:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.class_accum_cnt[2][7] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.class_accum_cnt[2][15:8] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.class_accum_cnt[3][1:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.class_accum_cnt[3][2] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.class_accum_cnt[3][15:3] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.loc_alert_cause[6:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
alert_dump_i.alert_cause[64:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
cpu_dump_i.current.exception_addr[31:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
cpu_dump_i.current.exception_pc[31:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
cpu_dump_i.current.last_data_addr[31:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
cpu_dump_i.current.next_pc[31:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
cpu_dump_i.current.current_pc[31:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
cpu_dump_i.prev_exception_addr[31:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
cpu_dump_i.prev_exception_pc[31:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
cpu_dump_i.prev_valid | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT |
scan_rst_ni | Yes | Yes | T7,T8,T11 | Yes | T7,T8,T11 | INPUT |
scanmode_i[3:0] | Yes | Yes | T7,T8,T11 | Yes | T7,T8,T11 | INPUT |
resets_o.rst_i2c2_n[0] | No | No | No | OUTPUT | ||
resets_o.rst_i2c2_n[1] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
resets_o.rst_i2c1_n[0] | No | No | No | OUTPUT | ||
resets_o.rst_i2c1_n[1] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
resets_o.rst_i2c0_n[0] | No | No | No | OUTPUT | ||
resets_o.rst_i2c0_n[1] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
resets_o.rst_usb_aon_n[0] | No | No | No | OUTPUT | ||
resets_o.rst_usb_aon_n[1] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
resets_o.rst_usb_n[0] | No | No | No | OUTPUT | ||
resets_o.rst_usb_n[1] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
resets_o.rst_spi_host1_n[0] | No | No | No | OUTPUT | ||
resets_o.rst_spi_host1_n[1] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
resets_o.rst_spi_host0_n[0] | No | No | No | OUTPUT | ||
resets_o.rst_spi_host0_n[1] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
resets_o.rst_spi_device_n[0] | No | No | No | OUTPUT | ||
resets_o.rst_spi_device_n[1] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
resets_o.rst_sys_io_div4_n[0] | Yes | Yes | *T1,*T2,*T3 | Yes | T1,T2,T3 | OUTPUT |
resets_o.rst_sys_io_div4_n[1] | No | No | No | OUTPUT | ||
resets_o.rst_sys_n[0] | No | No | No | OUTPUT | ||
resets_o.rst_sys_n[1] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
resets_o.rst_lc_usb_n[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
resets_o.rst_lc_io_div4_n[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
resets_o.rst_lc_io_div4_shadowed_n[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
resets_o.rst_lc_io_div2_n[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
resets_o.rst_lc_io_n[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
resets_o.rst_lc_aon_n[0] | Yes | Yes | *T1,*T2,*T3 | Yes | T1,T2,T3 | OUTPUT |
resets_o.rst_lc_aon_n[1] | No | No | No | OUTPUT | ||
resets_o.rst_lc_n[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
resets_o.rst_lc_shadowed_n[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
resets_o.rst_por_usb_n[0] | Yes | Yes | *T1,*T2,*T3 | Yes | T1,T2,T3 | OUTPUT |
resets_o.rst_por_usb_n[1] | No | No | No | OUTPUT | ||
resets_o.rst_por_io_div4_n[0] | Yes | Yes | *T1,*T2,*T3 | Yes | T1,T2,T3 | OUTPUT |
resets_o.rst_por_io_div4_n[1] | No | No | No | OUTPUT | ||
resets_o.rst_por_io_div2_n[0] | Yes | Yes | *T1,*T2,*T3 | Yes | T1,T2,T3 | OUTPUT |
resets_o.rst_por_io_div2_n[1] | No | No | No | OUTPUT | ||
resets_o.rst_por_io_n[0] | Yes | Yes | *T1,*T2,*T3 | Yes | T1,T2,T3 | OUTPUT |
resets_o.rst_por_io_n[1] | No | No | No | OUTPUT | ||
resets_o.rst_por_n[0] | Yes | Yes | *T1,*T2,*T3 | Yes | T1,T2,T3 | OUTPUT |
resets_o.rst_por_n[1] | No | No | No | OUTPUT | ||
resets_o.rst_por_aon_n[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 34 | 34 | 100.00 | 34 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 34 | 34 | 100.00 | 34 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 6019286 | 0 | 0 |
T1 | 42294 | 24728 | 0 | 0 |
T2 | 2988 | 971 | 0 | 0 |
T3 | 26095 | 8628 | 0 | 0 |
T4 | 2096 | 1476 | 0 | 0 |
T5 | 2968 | 786 | 0 | 0 |
T6 | 5515 | 4599 | 0 | 0 |
T7 | 29770 | 20361 | 0 | 0 |
T8 | 4772 | 3749 | 0 | 0 |
T9 | 53166 | 35624 | 0 | 0 |
T10 | 1489 | 870 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 6019286 | 0 | 0 |
T1 | 42294 | 24728 | 0 | 0 |
T2 | 2988 | 971 | 0 | 0 |
T3 | 26095 | 8628 | 0 | 0 |
T4 | 2096 | 1476 | 0 | 0 |
T5 | 2968 | 786 | 0 | 0 |
T6 | 5515 | 4599 | 0 | 0 |
T7 | 29770 | 20361 | 0 | 0 |
T8 | 4772 | 3749 | 0 | 0 |
T9 | 53166 | 35624 | 0 | 0 |
T10 | 1489 | 870 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 6019286 | 0 | 0 |
T1 | 42294 | 24728 | 0 | 0 |
T2 | 2988 | 971 | 0 | 0 |
T3 | 26095 | 8628 | 0 | 0 |
T4 | 2096 | 1476 | 0 | 0 |
T5 | 2968 | 786 | 0 | 0 |
T6 | 5515 | 4599 | 0 | 0 |
T7 | 29770 | 20361 | 0 | 0 |
T8 | 4772 | 3749 | 0 | 0 |
T9 | 53166 | 35624 | 0 | 0 |
T10 | 1489 | 870 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 6019286 | 0 | 0 |
T1 | 42294 | 24728 | 0 | 0 |
T2 | 2988 | 971 | 0 | 0 |
T3 | 26095 | 8628 | 0 | 0 |
T4 | 2096 | 1476 | 0 | 0 |
T5 | 2968 | 786 | 0 | 0 |
T6 | 5515 | 4599 | 0 | 0 |
T7 | 29770 | 20361 | 0 | 0 |
T8 | 4772 | 3749 | 0 | 0 |
T9 | 53166 | 35624 | 0 | 0 |
T10 | 1489 | 870 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 6019286 | 0 | 0 |
T1 | 42294 | 24728 | 0 | 0 |
T2 | 2988 | 971 | 0 | 0 |
T3 | 26095 | 8628 | 0 | 0 |
T4 | 2096 | 1476 | 0 | 0 |
T5 | 2968 | 786 | 0 | 0 |
T6 | 5515 | 4599 | 0 | 0 |
T7 | 29770 | 20361 | 0 | 0 |
T8 | 4772 | 3749 | 0 | 0 |
T9 | 53166 | 35624 | 0 | 0 |
T10 | 1489 | 870 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 6019286 | 0 | 0 |
T1 | 42294 | 24728 | 0 | 0 |
T2 | 2988 | 971 | 0 | 0 |
T3 | 26095 | 8628 | 0 | 0 |
T4 | 2096 | 1476 | 0 | 0 |
T5 | 2968 | 786 | 0 | 0 |
T6 | 5515 | 4599 | 0 | 0 |
T7 | 29770 | 20361 | 0 | 0 |
T8 | 4772 | 3749 | 0 | 0 |
T9 | 53166 | 35624 | 0 | 0 |
T10 | 1489 | 870 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 23 | 23 | 100.00 | |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 202 | 1 | 1 | 100.00 |
CONT_ASSIGN | 204 | 1 | 1 | 100.00 |
CONT_ASSIGN | 207 | 1 | 1 | 100.00 |
CONT_ASSIGN | 214 | 1 | 1 | 100.00 |
CONT_ASSIGN | 217 | 1 | 1 | 100.00 |
CONT_ASSIGN | 219 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 286 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1195 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1199 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1203 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1208 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1214 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1218 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1220 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1227 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1260 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1262 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
148 | 1 | 1 | |
202 | 1 | 1 | |
204 | 1 | 1 | |
207 | 1 | 1 | |
214 | 1 | 1 | |
217 | 1 | 1 | |
219 | 1 | 1 | |
285 | 1 | 1 | |
286 | 1 | 1 | |
1188 | 1 | 1 | |
1193 | 1 | 1 | |
1195 | 1 | 1 | |
1199 | 1 | 1 | |
1203 | 1 | 1 | |
1208 | 1 | 1 | |
1212 | 1 | 1 | |
1214 | 1 | 1 | |
1218 | 1 | 1 | |
1220 | 1 | 1 | |
1227 | 1 | 1 | |
1231 | 1 | 1 | |
1260 | 1 | 1 | |
1262 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 56 | 55 | 98.21 |
Logical | 56 | 55 | 98.21 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 37 SUB-EXPRESSION (rst_en_o.i2c2[1] == MuBi4True) ---------------1---------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 37 SUB-EXPRESSION (rst_en_o.i2c1[1] == MuBi4True) ---------------1---------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 37 SUB-EXPRESSION (rst_en_o.i2c0[1] == MuBi4True) ---------------1---------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 37 SUB-EXPRESSION (rst_en_o.usb_aon[1] == MuBi4True) -----------------1----------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 37 SUB-EXPRESSION (rst_en_o.usb[1] == MuBi4True) ---------------1--------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 37 SUB-EXPRESSION (rst_en_o.spi_host1[1] == MuBi4True) ------------------1-----------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 37 SUB-EXPRESSION (rst_en_o.spi_host0[1] == MuBi4True) ------------------1-----------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 37 SUB-EXPRESSION (rst_en_o.spi_device[1] == MuBi4True) ------------------1------------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 120 EXPRESSION (rst_por_aon_n[rstmgr_pkg::DomainAonSel] & por_n_i[1]) -------------------1------------------- -----2----
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 204 EXPRESSION (((|cnsty_chk_errs)) || ((|shadow_cnsty_chk_errs))) ---------1--------- -------------2------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T9 |
1 | 0 | Covered | T1,T3,T9 |
LINE 207 EXPRESSION (((|fsm_errs)) || ((|shadow_fsm_errs))) ------1------ ----------2---------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T65,T66,T67 |
1 | 0 | Covered | T65,T66,T67 |
LINE 214 EXPRESSION (reg2hw.err_code.reg_intg_err.q | ((|reg2hw.err_code.fsm_err.q))) ---------------1-------------- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T65,T66,T67 |
1 | 0 | Covered | T65,T66,T67 |
LINE 219 SUB-EXPRESSION (reg2hw.alert_test.fatal_cnsty_fault.q & reg2hw.alert_test.fatal_cnsty_fault.qe) ------------------1------------------ -------------------2------------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T4,T10,T68 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T10,T68 |
LINE 219 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault.q & reg2hw.alert_test.fatal_fault.qe) ---------------1--------------- ----------------2---------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T4,T10,T68 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T4,T10,T68 |
LINE 1188 EXPRESSION (((|pwr_i.rst_lc_req)) || ((|pwr_i.rst_sys_req))) ----------1---------- -----------2----------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered |
LINE 1193 EXPRESSION (pwrmgr_rst_req & (pwr_i.reset_cause == HwReq)) -------1------ --------------2-------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T6 |
LINE 1193 SUB-EXPRESSION (pwr_i.reset_cause == HwReq) --------------1-------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T6 |
LINE 1195 EXPRESSION (pwrmgr_rst_req & (pwr_i.reset_cause == LowPwrEntry)) -------1------ -----------------2----------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T3,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T7 |
LINE 1195 SUB-EXPRESSION (pwr_i.reset_cause == LowPwrEntry) -----------------1----------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
LINE 1227 EXPRESSION (rst_hw_req | rst_low_power) -----1---- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T7 |
1 | 0 | Covered | T1,T3,T6 |
LINE 1235 EXPRESSION (dump_capture & reg2hw.alert_info_ctrl.en.q) ------1----- -------------2-------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 1247 EXPRESSION (dump_capture & reg2hw.cpu_info_ctrl.en.q) ------1----- ------------2------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
Total | Covered | Percent | |
---|---|---|---|
Totals | 84 | 84 | 100.00 |
Total Bits | 1450 | 1450 | 100.00 |
Total Bits 0->1 | 725 | 725 | 100.00 |
Total Bits 1->0 | 725 | 725 | 100.00 |
Ports | 84 | 84 | 100.00 |
Port Bits | 1450 | 1450 | 100.00 |
Port Bits 0->1 | 725 | 725 | 100.00 |
Port Bits 1->0 | 725 | 725 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction | Exclude Annotation |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT | |
rst_ni | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT | |
clk_aon_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT | |
clk_io_div4_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT | |
clk_main_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT | |
clk_io_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT | |
clk_io_div2_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT | |
clk_usb_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT | |
clk_por_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT | |
rst_por_ni | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT | |
por_n_i[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT | |
tl_i.d_ready | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT | |
tl_i.a_user.data_intg[6:0] | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | INPUT | |
tl_i.a_user.cmd_intg[6:0] | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | INPUT | |
tl_i.a_user.instr_type[3:0] | Yes | Yes | T7,T8,T10 | Yes | T7,T8,T10 | INPUT | |
tl_i.a_user.rsvd[4:0] | Unreachable | Unreachable | Unreachable | INPUT | |||
tl_i.a_data[31:0] | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | INPUT | |
tl_i.a_mask[3:0] | Yes | Yes | T1,T3,T6 | Yes | T1,T3,T6 | INPUT | |
tl_i.a_address[31:0] | Yes | Yes | T1,T3,T6 | Yes | T1,T3,T6 | INPUT | |
tl_i.a_source[7:0] | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | INPUT | |
tl_i.a_size[1:0] | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | INPUT | |
tl_i.a_param[2:0] | Unreachable | Unreachable | Unreachable | INPUT | |||
tl_i.a_opcode[2:0] | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | INPUT | |
tl_i.a_valid | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT | |
tl_o.a_ready | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT | |
tl_o.d_error | Yes | Yes | T57,T60,T61 | Yes | T57,T60,T61 | OUTPUT | |
tl_o.d_user.data_intg[6:0] | Yes | Yes | T1,T3,T6 | Yes | T1,T2,T3 | OUTPUT | |
tl_o.d_user.rsp_intg[5:0] | Yes | Yes | *T1,*T3,*T4 | Yes | T1,T3,T4 | OUTPUT | |
tl_o.d_user.rsp_intg[6] | Unreachable | Unreachable | Unreachable | OUTPUT | |||
tl_o.d_data[31:0] | Yes | Yes | T1,T3,T6 | Yes | T1,T2,T3 | OUTPUT | |
tl_o.d_sink | Unreachable | Unreachable | Unreachable | OUTPUT | |||
tl_o.d_source[7:0] | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | OUTPUT | |
tl_o.d_size[1:0] | Yes | Yes | T1,T3,T4 | Yes | T1,T2,T3 | OUTPUT | |
tl_o.d_param[2:0] | Unreachable | Unreachable | Unreachable | OUTPUT | |||
tl_o.d_opcode[0] | Yes | Yes | *T1,*T3,*T6 | Yes | T1,T2,T3 | OUTPUT | |
tl_o.d_opcode[2:1] | Unreachable | Unreachable | Unreachable | OUTPUT | |||
tl_o.d_valid | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT | |
alert_rx_i[0].ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT | |
alert_rx_i[0].ack_p | Yes | Yes | T4,T10,T68 | Yes | T4,T10,T68 | INPUT | |
alert_rx_i[0].ping_n | Unreachable | Unreachable | Unreachable | INPUT | |||
alert_rx_i[0].ping_p | Unreachable | Unreachable | Unreachable | INPUT | |||
alert_rx_i[1].ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT | |
alert_rx_i[1].ack_p | Yes | Yes | T1,T4,T10 | Yes | T1,T4,T10 | INPUT | |
alert_rx_i[1].ping_n | Unreachable | Unreachable | Unreachable | INPUT | |||
alert_rx_i[1].ping_p | Unreachable | Unreachable | Unreachable | INPUT | |||
alert_tx_o[0].alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT | |
alert_tx_o[0].alert_p | Yes | Yes | T4,T10,T68 | Yes | T4,T10,T68 | OUTPUT | |
alert_tx_o[1].alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT | |
alert_tx_o[1].alert_p | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | OUTPUT | |
pwr_i.reset_cause[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT | |
pwr_i.rstreqs[4:0] | Yes | Yes | T1,T3,T6 | Yes | T1,T3,T6 | INPUT | |
pwr_i.rst_sys_req[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT | |
pwr_i.rst_lc_req[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT | |
pwr_o.rst_sys_src_n[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT | |
pwr_o.rst_lc_src_n[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT | |
sw_rst_req_o[3:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | OUTPUT | |
alert_dump_i.class_esc_cnt[0][12:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.class_esc_cnt[0][13] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.class_esc_cnt[0][24:14] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.class_esc_cnt[0][25] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.class_esc_cnt[0][31:26] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.class_esc_cnt[1][7:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.class_esc_cnt[1][8] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.class_esc_cnt[1][24:9] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.class_esc_cnt[1][25] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.class_esc_cnt[1][27:26] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.class_esc_cnt[1][28] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.class_esc_cnt[1][31:29] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.class_esc_cnt[2][0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.class_esc_cnt[2][2:1] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.class_esc_cnt[2][3] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.class_esc_cnt[2][22:4] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.class_esc_cnt[2][23] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.class_esc_cnt[2][31:24] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.class_esc_cnt[3][6:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.class_esc_cnt[3][7] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.class_esc_cnt[3][31:8] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.class_accum_cnt[0][15:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.class_accum_cnt[1][0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.class_accum_cnt[1][15:1] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.class_accum_cnt[2][6:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.class_accum_cnt[2][7] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.class_accum_cnt[2][15:8] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.class_accum_cnt[3][1:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.class_accum_cnt[3][2] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.class_accum_cnt[3][15:3] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.loc_alert_cause[6:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
alert_dump_i.alert_cause[64:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
cpu_dump_i.current.exception_addr[31:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
cpu_dump_i.current.exception_pc[31:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
cpu_dump_i.current.last_data_addr[31:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
cpu_dump_i.current.next_pc[31:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
cpu_dump_i.current.current_pc[31:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
cpu_dump_i.prev_exception_addr[31:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
cpu_dump_i.prev_exception_pc[31:0] | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
cpu_dump_i.prev_valid | Yes | Yes | T1,T3,T7 | Yes | T1,T3,T7 | INPUT | |
scan_rst_ni | Yes | Yes | T7,T8,T11 | Yes | T7,T8,T11 | INPUT | |
scanmode_i[3:0] | Yes | Yes | T7,T8,T11 | Yes | T7,T8,T11 | INPUT | |
resets_o.rst_i2c2_n[0] | Excluded | Excluded | Excluded | OUTPUT | 0->1:VC_COV_UNR / 1->0:VC_COV_UNR | ||
resets_o.rst_i2c2_n[1] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT | |
resets_o.rst_i2c1_n[0] | Excluded | Excluded | Excluded | OUTPUT | 0->1:VC_COV_UNR / 1->0:VC_COV_UNR | ||
resets_o.rst_i2c1_n[1] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT | |
resets_o.rst_i2c0_n[0] | Excluded | Excluded | Excluded | OUTPUT | 0->1:VC_COV_UNR / 1->0:VC_COV_UNR | ||
resets_o.rst_i2c0_n[1] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT | |
resets_o.rst_usb_aon_n[0] | Excluded | Excluded | Excluded | OUTPUT | 0->1:VC_COV_UNR / 1->0:VC_COV_UNR | ||
resets_o.rst_usb_aon_n[1] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT | |
resets_o.rst_usb_n[0] | Excluded | Excluded | Excluded | OUTPUT | 0->1:VC_COV_UNR / 1->0:VC_COV_UNR | ||
resets_o.rst_usb_n[1] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT | |
resets_o.rst_spi_host1_n[0] | Excluded | Excluded | Excluded | OUTPUT | 0->1:VC_COV_UNR / 1->0:VC_COV_UNR | ||
resets_o.rst_spi_host1_n[1] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT | |
resets_o.rst_spi_host0_n[0] | Excluded | Excluded | Excluded | OUTPUT | 0->1:VC_COV_UNR / 1->0:VC_COV_UNR | ||
resets_o.rst_spi_host0_n[1] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT | |
resets_o.rst_spi_device_n[0] | Excluded | Excluded | Excluded | OUTPUT | 0->1:VC_COV_UNR / 1->0:VC_COV_UNR | ||
resets_o.rst_spi_device_n[1] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT | |
resets_o.rst_sys_io_div4_n[0] | Yes | Yes | *T1,*T2,*T3 | Yes | T1,T2,T3 | OUTPUT | |
resets_o.rst_sys_io_div4_n[1] | Excluded | Excluded | Excluded | OUTPUT | 0->1:VC_COV_UNR / 1->0:VC_COV_UNR | ||
resets_o.rst_sys_n[0] | Excluded | Excluded | Excluded | OUTPUT | 0->1:VC_COV_UNR / 1->0:VC_COV_UNR | ||
resets_o.rst_sys_n[1] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT | |
resets_o.rst_lc_usb_n[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT | |
resets_o.rst_lc_io_div4_n[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT | |
resets_o.rst_lc_io_div4_shadowed_n[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT | |
resets_o.rst_lc_io_div2_n[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT | |
resets_o.rst_lc_io_n[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT | |
resets_o.rst_lc_aon_n[0] | Yes | Yes | *T1,*T2,*T3 | Yes | T1,T2,T3 | OUTPUT | |
resets_o.rst_lc_aon_n[1] | Excluded | Excluded | Excluded | OUTPUT | 0->1:VC_COV_UNR / 1->0:VC_COV_UNR | ||
resets_o.rst_lc_n[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT | |
resets_o.rst_lc_shadowed_n[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT | |
resets_o.rst_por_usb_n[0] | Yes | Yes | *T1,*T2,*T3 | Yes | T1,T2,T3 | OUTPUT | |
resets_o.rst_por_usb_n[1] | Excluded | Excluded | Excluded | OUTPUT | 0->1:VC_COV_UNR / 1->0:VC_COV_UNR | ||
resets_o.rst_por_io_div4_n[0] | Yes | Yes | *T1,*T2,*T3 | Yes | T1,T2,T3 | OUTPUT | |
resets_o.rst_por_io_div4_n[1] | Excluded | Excluded | Excluded | OUTPUT | 0->1:VC_COV_UNR / 1->0:VC_COV_UNR | ||
resets_o.rst_por_io_div2_n[0] | Yes | Yes | *T1,*T2,*T3 | Yes | T1,T2,T3 | OUTPUT | |
resets_o.rst_por_io_div2_n[1] | Excluded | Excluded | Excluded | OUTPUT | 0->1:VC_COV_UNR / 1->0:VC_COV_UNR | ||
resets_o.rst_por_io_n[0] | Yes | Yes | *T1,*T2,*T3 | Yes | T1,T2,T3 | OUTPUT | |
resets_o.rst_por_io_n[1] | Excluded | Excluded | Excluded | OUTPUT | 0->1:VC_COV_UNR / 1->0:VC_COV_UNR | ||
resets_o.rst_por_n[0] | Yes | Yes | *T1,*T2,*T3 | Yes | T1,T2,T3 | OUTPUT | |
resets_o.rst_por_n[1] | Excluded | Excluded | Excluded | OUTPUT | 0->1:VC_COV_UNR / 1->0:VC_COV_UNR | ||
resets_o.rst_por_aon_n[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 34 | 34 | 100.00 | 34 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 34 | 34 | 100.00 | 34 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 6019286 | 0 | 0 |
T1 | 42294 | 24728 | 0 | 0 |
T2 | 2988 | 971 | 0 | 0 |
T3 | 26095 | 8628 | 0 | 0 |
T4 | 2096 | 1476 | 0 | 0 |
T5 | 2968 | 786 | 0 | 0 |
T6 | 5515 | 4599 | 0 | 0 |
T7 | 29770 | 20361 | 0 | 0 |
T8 | 4772 | 3749 | 0 | 0 |
T9 | 53166 | 35624 | 0 | 0 |
T10 | 1489 | 870 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 6019286 | 0 | 0 |
T1 | 42294 | 24728 | 0 | 0 |
T2 | 2988 | 971 | 0 | 0 |
T3 | 26095 | 8628 | 0 | 0 |
T4 | 2096 | 1476 | 0 | 0 |
T5 | 2968 | 786 | 0 | 0 |
T6 | 5515 | 4599 | 0 | 0 |
T7 | 29770 | 20361 | 0 | 0 |
T8 | 4772 | 3749 | 0 | 0 |
T9 | 53166 | 35624 | 0 | 0 |
T10 | 1489 | 870 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 6019286 | 0 | 0 |
T1 | 42294 | 24728 | 0 | 0 |
T2 | 2988 | 971 | 0 | 0 |
T3 | 26095 | 8628 | 0 | 0 |
T4 | 2096 | 1476 | 0 | 0 |
T5 | 2968 | 786 | 0 | 0 |
T6 | 5515 | 4599 | 0 | 0 |
T7 | 29770 | 20361 | 0 | 0 |
T8 | 4772 | 3749 | 0 | 0 |
T9 | 53166 | 35624 | 0 | 0 |
T10 | 1489 | 870 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 6019286 | 0 | 0 |
T1 | 42294 | 24728 | 0 | 0 |
T2 | 2988 | 971 | 0 | 0 |
T3 | 26095 | 8628 | 0 | 0 |
T4 | 2096 | 1476 | 0 | 0 |
T5 | 2968 | 786 | 0 | 0 |
T6 | 5515 | 4599 | 0 | 0 |
T7 | 29770 | 20361 | 0 | 0 |
T8 | 4772 | 3749 | 0 | 0 |
T9 | 53166 | 35624 | 0 | 0 |
T10 | 1489 | 870 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 6019286 | 0 | 0 |
T1 | 42294 | 24728 | 0 | 0 |
T2 | 2988 | 971 | 0 | 0 |
T3 | 26095 | 8628 | 0 | 0 |
T4 | 2096 | 1476 | 0 | 0 |
T5 | 2968 | 786 | 0 | 0 |
T6 | 5515 | 4599 | 0 | 0 |
T7 | 29770 | 20361 | 0 | 0 |
T8 | 4772 | 3749 | 0 | 0 |
T9 | 53166 | 35624 | 0 | 0 |
T10 | 1489 | 870 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 6019286 | 0 | 0 |
T1 | 42294 | 24728 | 0 | 0 |
T2 | 2988 | 971 | 0 | 0 |
T3 | 26095 | 8628 | 0 | 0 |
T4 | 2096 | 1476 | 0 | 0 |
T5 | 2968 | 786 | 0 | 0 |
T6 | 5515 | 4599 | 0 | 0 |
T7 | 29770 | 20361 | 0 | 0 |
T8 | 4772 | 3749 | 0 | 0 |
T9 | 53166 | 35624 | 0 | 0 |
T10 | 1489 | 870 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10593466 | 70 | 0 | 0 |
T30 | 42004 | 0 | 0 | 0 |
T65 | 344763 | 20 | 0 | 0 |
T66 | 370596 | 20 | 0 | 0 |
T67 | 0 | 10 | 0 | 0 |
T69 | 0 | 10 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T71 | 5464 | 0 | 0 | 0 |
T72 | 64106 | 0 | 0 | 0 |
T73 | 2339 | 0 | 0 | 0 |
T74 | 5299 | 0 | 0 | 0 |
T75 | 8841 | 0 | 0 | 0 |
T76 | 3269 | 0 | 0 | 0 |
T77 | 25940 | 0 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |