Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11350370	9075	0	0
alert_regwen_rd_A	11350370	3905	0	0
cpu_regwen_rd_A	11350370	4084	0	0
sw_rst_ctrl_n_0_rd_A	11350370	7775	0	0
sw_rst_ctrl_n_1_rd_A	11350370	7965	0	0
sw_rst_ctrl_n_2_rd_A	11350370	7715	0	0
sw_rst_ctrl_n_3_rd_A	11350370	7916	0	0
sw_rst_ctrl_n_4_rd_A	11350370	7680	0	0
sw_rst_ctrl_n_5_rd_A	11350370	7810	0	0
sw_rst_ctrl_n_6_rd_A	11350370	7737	0	0
sw_rst_ctrl_n_7_rd_A	11350370	7685	0	0
sw_rst_regwen_0_rd_A	11350370	4471	0	0
sw_rst_regwen_1_rd_A	11350370	4494	0	0
sw_rst_regwen_2_rd_A	11350370	4337	0	0
sw_rst_regwen_3_rd_A	11350370	4431	0	0
sw_rst_regwen_4_rd_A	11350370	4320	0	0
sw_rst_regwen_5_rd_A	11350370	4532	0	0
sw_rst_regwen_6_rd_A	11350370	4319	0	0
sw_rst_regwen_7_rd_A	11350370	4477	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11350370	9075	0	0
T57	10699	1	0	0
T60	3984	6	0	0
T61	4205	13	0	0
T63	18793	1	0	0
T64	3970	382	0	0
T85	18079	3	0	0
T91	2697	210	0	0
T92	10625	809	0	0
T93	4635	684	0	0
T98	6104	0	0	0
T99	0	2	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11350370	3905	0	0
T18	3760	0	0	0
T43	284542	371	0	0
T44	3263	0	0	0
T56	0	5	0	0
T61	0	9	0	0
T89	10790	0	0	0
T98	0	25	0	0
T101	35589	59	0	0
T102	12615	0	0	0
T103	48271	0	0	0
T107	1679	0	0	0
T108	5689	0	0	0
T109	76098	42	0	0
T110	0	98	0	0
T123	0	64	0	0
T132	0	3	0	0
T133	0	26	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11350370	4084	0	0
T18	3760	0	0	0
T43	284542	400	0	0
T44	3263	0	0	0
T56	0	7	0	0
T61	0	9	0	0
T89	10790	0	0	0
T98	0	43	0	0
T101	35589	52	0	0
T102	12615	0	0	0
T103	48271	0	0	0
T107	1679	0	0	0
T108	5689	0	0	0
T109	76098	41	0	0
T110	0	103	0	0
T123	0	30	0	0
T133	0	8	0	0
T134	0	17	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11350370	7775	0	0
T6	5515	60	0	0
T7	29770	0	0	0
T8	4772	0	0	0
T9	53166	0	0	0
T10	1489	0	0	0
T11	4426	0	0	0
T12	3257	0	0	0
T13	1679	0	0	0
T40	0	137	0	0
T43	0	599	0	0
T45	1639	0	0	0
T52	0	261	0	0
T68	1799	0	0	0
T89	0	178	0	0
T90	0	13	0	0
T101	0	71	0	0
T135	0	7	0	0
T136	0	23	0	0
T137	0	15	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11350370	7965	0	0
T6	5515	75	0	0
T7	29770	0	0	0
T8	4772	0	0	0
T9	53166	0	0	0
T10	1489	0	0	0
T11	4426	0	0	0
T12	3257	0	0	0
T13	1679	0	0	0
T40	0	125	0	0
T43	0	604	0	0
T45	1639	0	0	0
T52	0	227	0	0
T68	1799	0	0	0
T89	0	178	0	0
T90	0	15	0	0
T101	0	58	0	0
T135	0	17	0	0
T136	0	30	0	0
T137	0	12	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11350370	7715	0	0
T6	5515	69	0	0
T7	29770	0	0	0
T8	4772	0	0	0
T9	53166	0	0	0
T10	1489	0	0	0
T11	4426	0	0	0
T12	3257	0	0	0
T13	1679	0	0	0
T40	0	150	0	0
T43	0	615	0	0
T45	1639	0	0	0
T52	0	211	0	0
T68	1799	0	0	0
T89	0	170	0	0
T90	0	11	0	0
T101	0	63	0	0
T135	0	10	0	0
T136	0	22	0	0
T137	0	14	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11350370	7916	0	0
T6	5515	67	0	0
T7	29770	0	0	0
T8	4772	0	0	0
T9	53166	0	0	0
T10	1489	0	0	0
T11	4426	0	0	0
T12	3257	0	0	0
T13	1679	0	0	0
T40	0	157	0	0
T43	0	612	0	0
T45	1639	0	0	0
T52	0	218	0	0
T68	1799	0	0	0
T89	0	196	0	0
T90	0	14	0	0
T101	0	68	0	0
T135	0	22	0	0
T136	0	9	0	0
T137	0	19	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11350370	7680	0	0
T6	5515	73	0	0
T7	29770	0	0	0
T8	4772	0	0	0
T9	53166	0	0	0
T10	1489	0	0	0
T11	4426	0	0	0
T12	3257	0	0	0
T13	1679	0	0	0
T40	0	162	0	0
T43	0	692	0	0
T45	1639	0	0	0
T52	0	229	0	0
T68	1799	0	0	0
T89	0	169	0	0
T90	0	23	0	0
T101	0	57	0	0
T135	0	11	0	0
T136	0	24	0	0
T137	0	13	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11350370	7810	0	0
T6	5515	75	0	0
T7	29770	0	0	0
T8	4772	0	0	0
T9	53166	0	0	0
T10	1489	0	0	0
T11	4426	0	0	0
T12	3257	0	0	0
T13	1679	0	0	0
T40	0	156	0	0
T43	0	642	0	0
T45	1639	0	0	0
T52	0	229	0	0
T68	1799	0	0	0
T89	0	173	0	0
T90	0	14	0	0
T101	0	48	0	0
T135	0	11	0	0
T136	0	26	0	0
T137	0	16	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11350370	7737	0	0
T6	5515	41	0	0
T7	29770	0	0	0
T8	4772	0	0	0
T9	53166	0	0	0
T10	1489	0	0	0
T11	4426	0	0	0
T12	3257	0	0	0
T13	1679	0	0	0
T40	0	149	0	0
T43	0	674	0	0
T45	1639	0	0	0
T52	0	196	0	0
T68	1799	0	0	0
T89	0	141	0	0
T90	0	10	0	0
T101	0	53	0	0
T135	0	18	0	0
T136	0	33	0	0
T137	0	6	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11350370	7685	0	0
T6	5515	76	0	0
T7	29770	0	0	0
T8	4772	0	0	0
T9	53166	0	0	0
T10	1489	0	0	0
T11	4426	0	0	0
T12	3257	0	0	0
T13	1679	0	0	0
T40	0	105	0	0
T43	0	648	0	0
T45	1639	0	0	0
T52	0	270	0	0
T68	1799	0	0	0
T89	0	168	0	0
T90	0	5	0	0
T101	0	58	0	0
T135	0	11	0	0
T136	0	21	0	0
T137	0	7	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11350370	4471	0	0
T17	4493	0	0	0
T40	9370	36	0	0
T43	0	406	0	0
T52	13210	28	0	0
T84	5484	0	0	0
T87	3535	0	0	0
T89	0	37	0	0
T90	5884	4	0	0
T101	0	61	0	0
T109	0	58	0	0
T124	28815	0	0	0
T135	0	6	0	0
T137	0	2	0	0
T138	0	15	0	0
T139	1444	0	0	0
T140	2373	0	0	0
T141	2376	0	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11350370	4494	0	0
T17	4493	0	0	0
T40	9370	34	0	0
T43	0	338	0	0
T52	13210	30	0	0
T84	5484	0	0	0
T87	3535	0	0	0
T89	0	44	0	0
T90	5884	6	0	0
T101	0	73	0	0
T109	0	54	0	0
T124	28815	0	0	0
T135	0	6	0	0
T137	0	11	0	0
T138	0	12	0	0
T139	1444	0	0	0
T140	2373	0	0	0
T141	2376	0	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11350370	4337	0	0
T17	4493	0	0	0
T40	9370	44	0	0
T43	0	418	0	0
T52	13210	26	0	0
T84	5484	0	0	0
T87	3535	0	0	0
T89	0	40	0	0
T90	5884	7	0	0
T101	0	64	0	0
T109	0	55	0	0
T124	28815	0	0	0
T135	0	1	0	0
T137	0	5	0	0
T138	0	11	0	0
T139	1444	0	0	0
T140	2373	0	0	0
T141	2376	0	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11350370	4431	0	0
T17	4493	0	0	0
T40	9370	30	0	0
T43	0	432	0	0
T52	13210	26	0	0
T84	5484	0	0	0
T87	3535	0	0	0
T89	0	44	0	0
T90	5884	8	0	0
T101	0	58	0	0
T109	0	74	0	0
T124	28815	0	0	0
T135	0	10	0	0
T137	0	7	0	0
T138	0	2	0	0
T139	1444	0	0	0
T140	2373	0	0	0
T141	2376	0	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11350370	4320	0	0
T17	4493	0	0	0
T40	9370	40	0	0
T43	0	394	0	0
T52	13210	34	0	0
T84	5484	0	0	0
T87	3535	0	0	0
T89	0	45	0	0
T90	5884	16	0	0
T101	0	50	0	0
T109	0	34	0	0
T124	28815	0	0	0
T135	0	5	0	0
T137	0	10	0	0
T138	0	29	0	0
T139	1444	0	0	0
T140	2373	0	0	0
T141	2376	0	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11350370	4532	0	0
T17	4493	0	0	0
T40	9370	22	0	0
T43	0	436	0	0
T52	13210	28	0	0
T84	5484	0	0	0
T87	3535	0	0	0
T89	0	53	0	0
T90	5884	4	0	0
T101	0	67	0	0
T109	0	74	0	0
T124	28815	0	0	0
T135	0	10	0	0
T137	0	7	0	0
T138	0	7	0	0
T139	1444	0	0	0
T140	2373	0	0	0
T141	2376	0	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11350370	4319	0	0
T17	4493	0	0	0
T40	9370	19	0	0
T43	0	412	0	0
T52	13210	30	0	0
T84	5484	0	0	0
T87	3535	0	0	0
T89	0	32	0	0
T90	5884	10	0	0
T101	0	57	0	0
T109	0	57	0	0
T124	28815	0	0	0
T135	0	5	0	0
T137	0	6	0	0
T138	0	15	0	0
T139	1444	0	0	0
T140	2373	0	0	0
T141	2376	0	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11350370	4477	0	0
T17	4493	0	0	0
T40	9370	48	0	0
T43	0	440	0	0
T52	13210	35	0	0
T84	5484	0	0	0
T87	3535	0	0	0
T89	0	41	0	0
T90	5884	2	0	0
T101	0	47	0	0
T109	0	75	0	0
T124	28815	0	0	0
T135	0	10	0	0
T137	0	1	0	0
T138	0	11	0	0
T139	1444	0	0	0
T140	2373	0	0	0
T141	2376	0	0	0