Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	10593466	12514	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	10593466	115275	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	10593466	6057128	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	10593466	184505	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	10593466	12514	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	10593466	115275	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	10593466	6057128	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	10593466	184505	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10593466	12514	0	0
T1	42294	75	0	0
T2	2988	0	0	0
T3	26095	75	0	0
T4	2096	0	0	0
T5	2968	0	0	0
T6	5515	19	0	0
T7	29770	33	0	0
T8	4772	4	0	0
T9	53166	75	0	0
T10	1489	0	0	0
T11	0	4	0	0
T21	0	75	0	0
T22	0	4	0	0
T23	0	75	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10593466	115275	0	0
T1	42294	713	0	0
T2	2988	0	0	0
T3	26095	721	0	0
T4	2096	0	0	0
T5	2968	0	0	0
T6	5515	171	0	0
T7	29770	298	0	0
T8	4772	37	0	0
T9	53166	701	0	0
T10	1489	0	0	0
T11	0	38	0	0
T21	0	701	0	0
T22	0	38	0	0
T23	0	701	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10593466	6057128	0	0
T1	42294	24829	0	0
T2	2988	977	0	0
T3	26095	8705	0	0
T4	2096	1479	0	0
T5	2968	792	0	0
T6	5515	4621	0	0
T7	29770	20472	0	0
T8	4772	3753	0	0
T9	53166	35749	0	0
T10	1489	874	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10593466	184505	0	0
T1	42294	1148	0	0
T2	2988	0	0	0
T3	26095	1172	0	0
T4	2096	0	0	0
T5	2968	0	0	0
T6	5515	271	0	0
T7	29770	461	0	0
T8	4772	65	0	0
T9	53166	1133	0	0
T10	1489	0	0	0
T11	0	64	0	0
T21	0	1100	0	0
T22	0	60	0	0
T23	0	1101	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10593466	12514	0	0
T1	42294	75	0	0
T2	2988	0	0	0
T3	26095	75	0	0
T4	2096	0	0	0
T5	2968	0	0	0
T6	5515	19	0	0
T7	29770	33	0	0
T8	4772	4	0	0
T9	53166	75	0	0
T10	1489	0	0	0
T11	0	4	0	0
T21	0	75	0	0
T22	0	4	0	0
T23	0	75	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10593466	115275	0	0
T1	42294	713	0	0
T2	2988	0	0	0
T3	26095	721	0	0
T4	2096	0	0	0
T5	2968	0	0	0
T6	5515	171	0	0
T7	29770	298	0	0
T8	4772	37	0	0
T9	53166	701	0	0
T10	1489	0	0	0
T11	0	38	0	0
T21	0	701	0	0
T22	0	38	0	0
T23	0	701	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10593466	6057128	0	0
T1	42294	24829	0	0
T2	2988	977	0	0
T3	26095	8705	0	0
T4	2096	1479	0	0
T5	2968	792	0	0
T6	5515	4621	0	0
T7	29770	20472	0	0
T8	4772	3753	0	0
T9	53166	35749	0	0
T10	1489	874	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10593466	184505	0	0
T1	42294	1148	0	0
T2	2988	0	0	0
T3	26095	1172	0	0
T4	2096	0	0	0
T5	2968	0	0	0
T6	5515	271	0	0
T7	29770	461	0	0
T8	4772	65	0	0
T9	53166	1133	0	0
T10	1489	0	0	0
T11	0	64	0	0
T21	0	1100	0	0
T22	0	60	0	0
T23	0	1101	0	0