Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T11
0	1	Covered	T7,T8,T11
1	0	Covered	T7,T78,T79

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T11
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	50101001	8403	0	0
CascadeEffAonToRstPorAboveRise_A	50101001	8403	0	0
CascadeEffAonToRstPorIoAboveFall_A	48095554	8403	0	0
CascadeEffAonToRstPorIoAboveRise_A	48095554	8403	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	24048534	8403	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	24048534	8403	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12024033	8403	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12024033	8403	0	0
CascadeEffAonToRstPorUcbAboveFall_A	24048569	8403	0	0
CascadeEffAonToRstPorUcbAboveRise_A	24048569	8403	0	0
CascadeLcToLcAboveFall_A	50101001	20917	0	0
CascadeLcToLcAboveRise_A	50101001	20917	0	0
CascadeLcToLcAonAboveFall_A	1518377	20917	0	0
CascadeLcToLcAonAboveRise_A	1518377	20917	0	0
CascadeLcToLcShadowedAboveFall_A	50101001	20917	0	0
CascadeLcToLcShadowedAboveRise_A	50101001	20917	0	0
CascadePorToAonAboveFall_A	1518377	6721	0	0
CascadeSysToSysAboveFall_A	50101001	20917	0	0
CascadeSysToSysAboveRise_A	50101001	20917	0	0
ScanRstToAonRise_A	1518377	241	0	0
StablePorToAonRise_A	1518377	8403	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	10593466	20917	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	10593466	20917	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	10593466	20917	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	10593466	20917	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12024033	20917	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12024033	20917	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	10593466	20917	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	10593466	20917	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	10593466	20917	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	10593466	20917	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50101001	8403	0	0
T1	189399	27	0	0
T2	12632	2	0	0
T3	123125	27	0	0
T4	8914	1	0	0
T5	13048	2	0	0
T6	28289	1	0	0
T7	147045	20	0	0
T8	20884	2	0	0
T9	232977	27	0	0
T10	6385	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50101001	8403	0	0
T1	189399	27	0	0
T2	12632	2	0	0
T3	123125	27	0	0
T4	8914	1	0	0
T5	13048	2	0	0
T6	28289	1	0	0
T7	147045	20	0	0
T8	20884	2	0	0
T9	232977	27	0	0
T10	6385	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48095554	8403	0	0
T1	181825	27	0	0
T2	12127	2	0	0
T3	118137	27	0	0
T4	8556	1	0	0
T5	12525	2	0	0
T6	27156	1	0	0
T7	141163	20	0	0
T8	20040	2	0	0
T9	223654	27	0	0
T10	6129	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48095554	8403	0	0
T1	181825	27	0	0
T2	12127	2	0	0
T3	118137	27	0	0
T4	8556	1	0	0
T5	12525	2	0	0
T6	27156	1	0	0
T7	141163	20	0	0
T8	20040	2	0	0
T9	223654	27	0	0
T10	6129	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24048534	8403	0	0
T1	90904	27	0	0
T2	6064	2	0	0
T3	59083	27	0	0
T4	4278	1	0	0
T5	6261	2	0	0
T6	13578	1	0	0
T7	70577	20	0	0
T8	10023	2	0	0
T9	111825	27	0	0
T10	3064	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24048534	8403	0	0
T1	90904	27	0	0
T2	6064	2	0	0
T3	59083	27	0	0
T4	4278	1	0	0
T5	6261	2	0	0
T6	13578	1	0	0
T7	70577	20	0	0
T8	10023	2	0	0
T9	111825	27	0	0
T10	3064	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12024033	8403	0	0
T1	45453	27	0	0
T2	3030	2	0	0
T3	29544	27	0	0
T4	2139	1	0	0
T5	3131	2	0	0
T6	6789	1	0	0
T7	35289	20	0	0
T8	5010	2	0	0
T9	55916	27	0	0
T10	1531	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12024033	8403	0	0
T1	45453	27	0	0
T2	3030	2	0	0
T3	29544	27	0	0
T4	2139	1	0	0
T5	3131	2	0	0
T6	6789	1	0	0
T7	35289	20	0	0
T8	5010	2	0	0
T9	55916	27	0	0
T10	1531	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24048569	8403	0	0
T1	90918	27	0	0
T2	6064	2	0	0
T3	59093	27	0	0
T4	4278	1	0	0
T5	6262	2	0	0
T6	13578	1	0	0
T7	70573	20	0	0
T8	10024	2	0	0
T9	111834	27	0	0
T10	3063	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24048569	8403	0	0
T1	90918	27	0	0
T2	6064	2	0	0
T3	59093	27	0	0
T4	4278	1	0	0
T5	6262	2	0	0
T6	13578	1	0	0
T7	70573	20	0	0
T8	10024	2	0	0
T9	111834	27	0	0
T10	3063	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50101001	20917	0	0
T1	189399	102	0	0
T2	12632	2	0	0
T3	123125	102	0	0
T4	8914	1	0	0
T5	13048	2	0	0
T6	28289	20	0	0
T7	147045	53	0	0
T8	20884	6	0	0
T9	232977	102	0	0
T10	6385	1	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50101001	20917	0	0
T1	189399	102	0	0
T2	12632	2	0	0
T3	123125	102	0	0
T4	8914	1	0	0
T5	13048	2	0	0
T6	28289	20	0	0
T7	147045	53	0	0
T8	20884	6	0	0
T9	232977	102	0	0
T10	6385	1	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1518377	20917	0	0
T1	5696	102	0	0
T2	378	2	0	0
T3	3708	102	0	0
T4	266	1	0	0
T5	390	2	0	0
T6	847	20	0	0
T7	4471	53	0	0
T8	624	6	0	0
T9	7004	102	0	0
T10	191	1	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1518377	20917	0	0
T1	5696	102	0	0
T2	378	2	0	0
T3	3708	102	0	0
T4	266	1	0	0
T5	390	2	0	0
T6	847	20	0	0
T7	4471	53	0	0
T8	624	6	0	0
T9	7004	102	0	0
T10	191	1	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50101001	20917	0	0
T1	189399	102	0	0
T2	12632	2	0	0
T3	123125	102	0	0
T4	8914	1	0	0
T5	13048	2	0	0
T6	28289	20	0	0
T7	147045	53	0	0
T8	20884	6	0	0
T9	232977	102	0	0
T10	6385	1	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50101001	20917	0	0
T1	189399	102	0	0
T2	12632	2	0	0
T3	123125	102	0	0
T4	8914	1	0	0
T5	13048	2	0	0
T6	28289	20	0	0
T7	147045	53	0	0
T8	20884	6	0	0
T9	232977	102	0	0
T10	6385	1	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1518377	6721	0	0
T1	5696	27	0	0
T2	378	8	0	0
T3	3708	27	0	0
T4	266	1	0	0
T5	390	10	0	0
T6	847	1	0	0
T7	4471	13	0	0
T8	624	1	0	0
T9	7004	27	0	0
T10	191	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50101001	20917	0	0
T1	189399	102	0	0
T2	12632	2	0	0
T3	123125	102	0	0
T4	8914	1	0	0
T5	13048	2	0	0
T6	28289	20	0	0
T7	147045	53	0	0
T8	20884	6	0	0
T9	232977	102	0	0
T10	6385	1	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50101001	20917	0	0
T1	189399	102	0	0
T2	12632	2	0	0
T3	123125	102	0	0
T4	8914	1	0	0
T5	13048	2	0	0
T6	28289	20	0	0
T7	147045	53	0	0
T8	20884	6	0	0
T9	232977	102	0	0
T10	6385	1	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1518377	241	0	0
T7	4471	1	0	0
T8	624	0	0	0
T9	7004	0	0	0
T10	191	0	0	0
T11	600	0	0	0
T12	417	0	0	0
T13	219	0	0	0
T43	0	10	0	0
T44	0	1	0	0
T45	213	0	0	0
T46	0	1	0	0
T68	227	0	0	0
T78	0	2	0	0
T82	0	1	0	0
T83	170	0	0	0
T101	0	2	0	0
T104	0	3	0	0
T106	0	6	0	0
T124	0	2	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1518377	8403	0	0
T1	5696	27	0	0
T2	378	2	0	0
T3	3708	27	0	0
T4	266	1	0	0
T5	390	2	0	0
T6	847	1	0	0
T7	4471	20	0	0
T8	624	2	0	0
T9	7004	27	0	0
T10	191	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10593466	20917	0	0
T1	42294	102	0	0
T2	2988	2	0	0
T3	26095	102	0	0
T4	2096	1	0	0
T5	2968	2	0	0
T6	5515	20	0	0
T7	29770	53	0	0
T8	4772	6	0	0
T9	53166	102	0	0
T10	1489	1	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10593466	20917	0	0
T1	42294	102	0	0
T2	2988	2	0	0
T3	26095	102	0	0
T4	2096	1	0	0
T5	2968	2	0	0
T6	5515	20	0	0
T7	29770	53	0	0
T8	4772	6	0	0
T9	53166	102	0	0
T10	1489	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10593466	20917	0	0
T1	42294	102	0	0
T2	2988	2	0	0
T3	26095	102	0	0
T4	2096	1	0	0
T5	2968	2	0	0
T6	5515	20	0	0
T7	29770	53	0	0
T8	4772	6	0	0
T9	53166	102	0	0
T10	1489	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10593466	20917	0	0
T1	42294	102	0	0
T2	2988	2	0	0
T3	26095	102	0	0
T4	2096	1	0	0
T5	2968	2	0	0
T6	5515	20	0	0
T7	29770	53	0	0
T8	4772	6	0	0
T9	53166	102	0	0
T10	1489	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12024033	20917	0	0
T1	45453	102	0	0
T2	3030	2	0	0
T3	29544	102	0	0
T4	2139	1	0	0
T5	3131	2	0	0
T6	6789	20	0	0
T7	35289	53	0	0
T8	5010	6	0	0
T9	55916	102	0	0
T10	1531	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12024033	20917	0	0
T1	45453	102	0	0
T2	3030	2	0	0
T3	29544	102	0	0
T4	2139	1	0	0
T5	3131	2	0	0
T6	6789	20	0	0
T7	35289	53	0	0
T8	5010	6	0	0
T9	55916	102	0	0
T10	1531	1	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10593466	20917	0	0
T1	42294	102	0	0
T2	2988	2	0	0
T3	26095	102	0	0
T4	2096	1	0	0
T5	2968	2	0	0
T6	5515	20	0	0
T7	29770	53	0	0
T8	4772	6	0	0
T9	53166	102	0	0
T10	1489	1	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10593466	20917	0	0
T1	42294	102	0	0
T2	2988	2	0	0
T3	26095	102	0	0
T4	2096	1	0	0
T5	2968	2	0	0
T6	5515	20	0	0
T7	29770	53	0	0
T8	4772	6	0	0
T9	53166	102	0	0
T10	1489	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10593466	20917	0	0
T1	42294	102	0	0
T2	2988	2	0	0
T3	26095	102	0	0
T4	2096	1	0	0
T5	2968	2	0	0
T6	5515	20	0	0
T7	29770	53	0	0
T8	4772	6	0	0
T9	53166	102	0	0
T10	1489	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10593466	20917	0	0
T1	42294	102	0	0
T2	2988	2	0	0
T3	26095	102	0	0
T4	2096	1	0	0
T5	2968	2	0	0
T6	5515	20	0	0
T7	29770	53	0	0
T8	4772	6	0	0
T9	53166	102	0	0
T10	1489	1	0	0