Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8400

1

T2

38

T3

7

T7

25

auto[1]

11541

1

T1

4

T2

25

T3

1

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6081	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6822	1			T1	2		T2	18		T3	1
reset_info_cp[2]	3071	1			T1	1		T2	11		T7	6
reset_info_cp[4]	4021	1			T1	1		T2	18		T7	14
reset_info_cp[8]	106	1			T2	2		T3	1		T12	1
reset_info_cp[16]	123	1			T2	1		T8	1		T12	1
reset_info_cp[32]	104	1			T8	2		T12	2		T25	1
reset_info_cp[64]	118	1			T73	4		T129	1		T82	1
reset_info_cp[128]	113	1			T3	1		T7	1		T8	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3263	1			T2	6		T7	8		T8	17
reset_info_cp[1]	auto[1]	2941	1			T1	1		T2	11		T7	11
reset_info_cp[2]	auto[0]	965	1			T2	9		T7	2		T22	5
reset_info_cp[2]	auto[1]	2106	1			T1	1		T2	2		T7	4
reset_info_cp[4]	auto[0]	1418	1			T2	11		T7	6		T22	4
reset_info_cp[4]	auto[1]	2603	1			T1	1		T2	7		T7	8
reset_info_cp[8]	auto[0]	45	1			T2	1		T3	1		T12	1
reset_info_cp[8]	auto[1]	61	1			T2	1		T25	1		T85	1
reset_info_cp[16]	auto[0]	46	1			T12	1		T24	1		T48	1
reset_info_cp[16]	auto[1]	77	1			T2	1		T8	1		T25	1
reset_info_cp[32]	auto[0]	33	1			T12	1		T72	1		T73	1
reset_info_cp[32]	auto[1]	71	1			T8	2		T12	1		T25	1
reset_info_cp[64]	auto[0]	44	1			T73	3		T129	1		T82	1
reset_info_cp[64]	auto[1]	74	1			T73	1		T131	2		T137	1
reset_info_cp[128]	auto[0]	53	1			T3	1		T7	1		T12	1
reset_info_cp[128]	auto[1]	60	1			T8	1		T25	2		T73	1