ASSERT | PROPERTIES | SEQUENCES | |
Total | 733 | 0 | 10 |
Category 0 | 733 | 0 | 10 |
ASSERT | PROPERTIES | SEQUENCES | |
Total | 733 | 0 | 10 |
Severity 0 | 733 | 0 | 10 |
NUMBER | PERCENT | |
Total Number | 733 | 100.00 |
Uncovered | 4 | 0.55 |
Success | 729 | 99.45 |
Failure | 0 | 0.00 |
Incomplete | 0 | 0.00 |
Without Attempts | 0 | 0.00 |
NUMBER | PERCENT | |
Total Number | 10 | 100.00 |
Uncovered | 0 | 0.00 |
All Matches | 10 | 100.00 |
First Matches | 10 | 100.00 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorAonEnTracksRstPorAonActive_A | 0 | 0 | 1670472 | 0 | 0 | 0 | |
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorEnTracksRstPorInactive_A | 0 | 0 | 55104885 | 0 | 0 | 0 | |
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv4EnTracksRstPorIoDiv4Active_A | 0 | 0 | 13224784 | 0 | 0 | 0 | |
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoEnTracksRstPorIoInactive_A | 0 | 0 | 52899386 | 0 | 0 | 0 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 12384178 | 6542 | 6542 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 12384178 | 2667 | 2667 | 1 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 12384178 | 2670 | 2670 | 1 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 12384178 | 1878 | 1878 | 1 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 12384178 | 91 | 91 | 1 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 12384178 | 1412 | 1412 | 1 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 12384178 | 1001 | 1001 | 1 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 12384178 | 3728 | 3728 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 12384178 | 57362 | 57362 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 12384178 | 507871 | 507871 | 452 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 12384178 | 6542 | 6542 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 12384178 | 2667 | 2667 | 1 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 12384178 | 2670 | 2670 | 1 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 12384178 | 1878 | 1878 | 1 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 12384178 | 91 | 91 | 1 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 12384178 | 1412 | 1412 | 1 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 12384178 | 1001 | 1001 | 1 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 12384178 | 3728 | 3728 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 12384178 | 57362 | 57362 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 12384178 | 507871 | 507871 | 452 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |