| | | | | | | |
rstmgr_por |
90.74 |
91.67 |
91.67 |
|
|
88.89 |
|
tlul_rsp_intg_gen |
91.67 |
83.33 |
|
|
|
|
100.00 |
tlul_rsp_intg_gen |
100.00 |
|
|
|
|
|
100.00 |
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 ) |
66.67 |
66.67 |
|
|
|
|
|
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 ) |
100.00 |
100.00 |
|
|
|
|
|
rstmgr_rst_en_track_sva_if |
92.86 |
|
|
|
|
|
92.86 |
prim_subreg_arb |
95.83 |
87.50 |
100.00 |
|
|
100.00 |
|
prim_subreg_arb |
100.00 |
|
|
|
|
100.00 |
|
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 ) |
50.00 |
50.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 + DW=5,SwAccess=3,Mubi=0 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 ) |
100.00 |
100.00 |
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=4,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=4,SwAccess=0,Mubi=0 + DW=1,SwAccess=0,Mubi=0 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=5,SwAccess=3,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
tlul_adapter_reg |
98.91 |
100.00 |
95.65 |
|
|
100.00 |
100.00 |
rstmgr |
99.01 |
100.00 |
98.21 |
97.84 |
|
|
100.00 |
prim_generic_clock_mux2 |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
tlul_data_integ_dec |
100.00 |
100.00 |
|
|
|
|
|
pwrmgr_rstmgr_sva_if |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
tlul_cmd_intg_chk |
100.00 |
100.00 |
|
|
|
|
100.00 |
prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
rstmgr_sw_rst_sva_if |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
|
100.00 |
rstmgr_leaf_rst |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
rstmgr_leaf_rst |
100.00 |
|
|
|
|
100.00 |
|
rstmgr_leaf_rst ( parameter SecCheck=0,SecMaxSyncDelay=2,SwRstReq=0 ) |
|
|
|
|
|
|
|
rstmgr_leaf_rst ( parameter SecCheck=1,SecMaxSyncDelay=2,SwRstReq=0 ) |
100.00 |
|
100.00 |
|
|
|
|
rstmgr_leaf_rst ( parameter SecCheck=1,SecMaxSyncDelay=2,SwRstReq=1 ) |
100.00 |
100.00 |
100.00 |
|
|
|
|
tlul_assert |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
prim_onehot_check |
100.00 |
|
|
100.00 |
|
|
|
prim_subreg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
prim_subreg |
100.00 |
100.00 |
|
|
|
100.00 |
|
prim_subreg ( parameter DW=1,SwAccess=3,RESVAL,Mubi=0 + DW=1,SwAccess=5,RESVAL=1,Mubi=0 + DW=1,SwAccess=0,RESVAL,Mubi=0 + DW=1,SwAccess=1,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=4,SwAccess=0,RESVAL,Mubi ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=5,SwAccess=3,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_secded_inv_39_32_dec |
100.00 |
|
|
100.00 |
|
|
|
prim_generic_buf |
100.00 |
100.00 |
|
|
|
|
|
rstmgr_ctrl |
100.00 |
100.00 |
100.00 |
|
|
|
|
rstmgr_attrs_sva_if |
100.00 |
|
|
|
|
|
100.00 |
rstmgr_reg_top |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
prim_subreg_ext |
100.00 |
100.00 |
|
|
|
|
|
rstmgr_csr_assert_fpv |
100.00 |
|
|
|
|
|
100.00 |
rstmgr_cnsty_chk |
100.00 |
|
|
100.00 |
|
|
|
prim_secded_inv_39_32_enc |
100.00 |
100.00 |
|
|
|
|
|
prim_rst_sync |
100.00 |
100.00 |
|
|
|
|
|
tlul_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
prim_secded_inv_64_57_enc |
100.00 |
100.00 |
|
|
|
|
|
prim_secded_inv_64_57_dec |
100.00 |
|
|
100.00 |
|
|
|
rstmgr_crash_info |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
rstmgr_crash_info |
100.00 |
|
|
|
|
100.00 |
100.00 |
rstmgr_crash_info ( parameter CrashDumpWidth=225,CrashStoreSlot=8,SlotCntWidth=3,TotalWidth=256 ) |
100.00 |
100.00 |
|
|
|
|
|
rstmgr_crash_info ( parameter CrashDumpWidth=276,CrashStoreSlot=9,SlotCntWidth=4,TotalWidth=288 ) |
100.00 |
100.00 |
|
|
|
|
|
rstmgr_cascading_sva_if |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
prim_generic_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
prim_mubi4_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
prim_generic_clock_buf |
100.00 |
100.00 |
|
|
|
|
|
prim_clock_buf |
|
|
|
|
|
|
|
tlul_data_integ_enc |
|
|
|
|
|
|
|
prim_reg_we_check |
|
|
|
|
|
|
|
prim_clock_mux2 |
|
|
|
|
|
|
|
prim_buf |
|
|
|
|
|
|
|
prim_flop |
|
|
|
|
|
|
|
prim_flop_2sync |
|
|
|
|
|
|
|
tb |
|
|
|
|
|
|
|