Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_access_cg
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Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_access_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv



Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_access_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00


Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_access_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
index_cp 9 0 9 100.00 100 1 1 0


Summary for Variable index_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 9 0 9 100.00


User Defined Bins for index_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
others 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid[0] 35242 1 T1 14 T2 122 T7 104
valid[1] 35242 1 T1 14 T2 122 T7 104
valid[2] 35242 1 T1 14 T2 122 T7 104
valid[3] 35242 1 T1 14 T2 122 T7 104
valid[4] 35242 1 T1 14 T2 122 T7 104
valid[5] 35242 1 T1 14 T2 122 T7 104
valid[6] 35242 1 T1 14 T2 122 T7 104
valid[7] 35242 1 T1 14 T2 122 T7 104
valid[8] 43044 1 T1 14 T2 154 T7 140

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%