Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8482 |
1 |
|
|
T2 |
27 |
|
T3 |
7 |
|
T7 |
31 |
auto[1] |
11459 |
1 |
|
|
T1 |
4 |
|
T2 |
36 |
|
T3 |
1 |
Summary for Variable reset_info_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for reset_info_cp
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
6081 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
reset_info_cp[1] |
6822 |
1 |
|
|
T1 |
2 |
|
T2 |
18 |
|
T3 |
1 |
reset_info_cp[2] |
3071 |
1 |
|
|
T1 |
1 |
|
T2 |
11 |
|
T7 |
6 |
reset_info_cp[4] |
4021 |
1 |
|
|
T1 |
1 |
|
T2 |
18 |
|
T7 |
14 |
reset_info_cp[8] |
106 |
1 |
|
|
T2 |
2 |
|
T3 |
1 |
|
T12 |
1 |
reset_info_cp[16] |
123 |
1 |
|
|
T2 |
1 |
|
T8 |
1 |
|
T12 |
1 |
reset_info_cp[32] |
104 |
1 |
|
|
T8 |
2 |
|
T12 |
2 |
|
T25 |
1 |
reset_info_cp[64] |
118 |
1 |
|
|
T73 |
4 |
|
T129 |
1 |
|
T82 |
1 |
reset_info_cp[128] |
113 |
1 |
|
|
T3 |
1 |
|
T7 |
1 |
|
T8 |
1 |
Summary for Cross capture_cross
Samples crossed: reset_info_cp enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for capture_cross
Bins
reset_info_cp | enable_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
reset_info_cp[1] |
auto[0] |
3252 |
1 |
|
|
T2 |
5 |
|
T7 |
11 |
|
T8 |
17 |
reset_info_cp[1] |
auto[1] |
2952 |
1 |
|
|
T1 |
1 |
|
T2 |
12 |
|
T7 |
8 |
reset_info_cp[2] |
auto[0] |
987 |
1 |
|
|
T2 |
5 |
|
T7 |
3 |
|
T22 |
7 |
reset_info_cp[2] |
auto[1] |
2084 |
1 |
|
|
T1 |
1 |
|
T2 |
6 |
|
T7 |
3 |
reset_info_cp[4] |
auto[0] |
1450 |
1 |
|
|
T2 |
6 |
|
T7 |
8 |
|
T22 |
8 |
reset_info_cp[4] |
auto[1] |
2571 |
1 |
|
|
T1 |
1 |
|
T2 |
12 |
|
T7 |
6 |
reset_info_cp[8] |
auto[0] |
39 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T12 |
1 |
reset_info_cp[8] |
auto[1] |
67 |
1 |
|
|
T2 |
1 |
|
T25 |
1 |
|
T73 |
1 |
reset_info_cp[16] |
auto[0] |
52 |
1 |
|
|
T2 |
1 |
|
T12 |
1 |
|
T24 |
1 |
reset_info_cp[16] |
auto[1] |
71 |
1 |
|
|
T8 |
1 |
|
T25 |
1 |
|
T52 |
1 |
reset_info_cp[32] |
auto[0] |
36 |
1 |
|
|
T12 |
1 |
|
T72 |
1 |
|
T73 |
2 |
reset_info_cp[32] |
auto[1] |
68 |
1 |
|
|
T8 |
2 |
|
T12 |
1 |
|
T25 |
1 |
reset_info_cp[64] |
auto[0] |
50 |
1 |
|
|
T129 |
1 |
|
T135 |
1 |
|
T136 |
1 |
reset_info_cp[64] |
auto[1] |
68 |
1 |
|
|
T73 |
4 |
|
T82 |
1 |
|
T131 |
2 |
reset_info_cp[128] |
auto[0] |
50 |
1 |
|
|
T3 |
1 |
|
T12 |
1 |
|
T73 |
1 |
reset_info_cp[128] |
auto[1] |
63 |
1 |
|
|
T7 |
1 |
|
T8 |
1 |
|
T25 |
2 |