Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg
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Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv



Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 16 0 16 100.00


Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable_cp 2 0 2 100.00 100 1 1 2
reset_info_cp 8 0 8 100.00 100 1 1 0


Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
capture_cross 16 0 16 100.00 100 1 1 0


Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8482 1 T2 27 T3 7 T7 31
auto[1] 11459 1 T1 4 T2 36 T3 1



Summary for Variable reset_info_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for reset_info_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
others 6081 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
reset_info_cp[1] 6822 1 T1 2 T2 18 T3 1
reset_info_cp[2] 3071 1 T1 1 T2 11 T7 6
reset_info_cp[4] 4021 1 T1 1 T2 18 T7 14
reset_info_cp[8] 106 1 T2 2 T3 1 T12 1
reset_info_cp[16] 123 1 T2 1 T8 1 T12 1
reset_info_cp[32] 104 1 T8 2 T12 2 T25 1
reset_info_cp[64] 118 1 T73 4 T129 1 T82 1
reset_info_cp[128] 113 1 T3 1 T7 1 T8 1



Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for capture_cross

Bins
reset_info_cpenable_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
reset_info_cp[1] auto[0] 3252 1 T2 5 T7 11 T8 17
reset_info_cp[1] auto[1] 2952 1 T1 1 T2 12 T7 8
reset_info_cp[2] auto[0] 987 1 T2 5 T7 3 T22 7
reset_info_cp[2] auto[1] 2084 1 T1 1 T2 6 T7 3
reset_info_cp[4] auto[0] 1450 1 T2 6 T7 8 T22 8
reset_info_cp[4] auto[1] 2571 1 T1 1 T2 12 T7 6
reset_info_cp[8] auto[0] 39 1 T2 1 T3 1 T12 1
reset_info_cp[8] auto[1] 67 1 T2 1 T25 1 T73 1
reset_info_cp[16] auto[0] 52 1 T2 1 T12 1 T24 1
reset_info_cp[16] auto[1] 71 1 T8 1 T25 1 T52 1
reset_info_cp[32] auto[0] 36 1 T12 1 T72 1 T73 2
reset_info_cp[32] auto[1] 68 1 T8 2 T12 1 T25 1
reset_info_cp[64] auto[0] 50 1 T129 1 T135 1 T136 1
reset_info_cp[64] auto[1] 68 1 T73 4 T82 1 T131 2
reset_info_cp[128] auto[0] 50 1 T3 1 T12 1 T73 1
reset_info_cp[128] auto[1] 63 1 T7 1 T8 1 T25 2

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