Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_access_cg
Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_access_cg
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
8 |
0 |
8 |
100.00 |
Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_access_cg
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
index_cp |
8 |
0 |
8 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable index_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for index_cp
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid[0] |
43090 |
1 |
|
|
T1 |
14 |
|
T2 |
154 |
|
T7 |
140 |
valid[1] |
35242 |
1 |
|
|
T1 |
14 |
|
T2 |
122 |
|
T7 |
104 |
valid[2] |
35242 |
1 |
|
|
T1 |
14 |
|
T2 |
122 |
|
T7 |
104 |
valid[3] |
35242 |
1 |
|
|
T1 |
14 |
|
T2 |
122 |
|
T7 |
104 |
valid[4] |
35242 |
1 |
|
|
T1 |
14 |
|
T2 |
122 |
|
T7 |
104 |
valid[5] |
35242 |
1 |
|
|
T1 |
14 |
|
T2 |
122 |
|
T7 |
104 |
valid[6] |
35242 |
1 |
|
|
T1 |
14 |
|
T2 |
122 |
|
T7 |
104 |
valid[7] |
35242 |
1 |
|
|
T1 |
14 |
|
T2 |
122 |
|
T7 |
104 |
0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |