| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.44 | 99.40 | 99.31 | 99.88 | 99.83 | 99.46 | 98.77 |
| T503 | /workspace/coverage/default/1.rstmgr_sw_rst.1291566959 | Jan 24 01:04:09 PM PST 24 | Jan 24 01:04:56 PM PST 24 | 317405554 ps | ||
| T504 | /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3571313308 | Jan 24 01:04:09 PM PST 24 | Jan 24 01:05:01 PM PST 24 | 2346510977 ps | ||
| T505 | /workspace/coverage/default/24.rstmgr_smoke.2518882400 | Jan 24 01:06:20 PM PST 24 | Jan 24 01:07:16 PM PST 24 | 112489921 ps | ||
| T506 | /workspace/coverage/default/30.rstmgr_reset.1500959659 | Jan 24 01:06:53 PM PST 24 | Jan 24 01:07:55 PM PST 24 | 786193953 ps | ||
| T507 | /workspace/coverage/default/35.rstmgr_smoke.713064233 | Jan 24 01:07:49 PM PST 24 | Jan 24 01:08:40 PM PST 24 | 241160027 ps | ||
| T508 | /workspace/coverage/default/3.rstmgr_smoke.2215125979 | Jan 24 01:04:12 PM PST 24 | Jan 24 01:04:58 PM PST 24 | 122367511 ps | ||
| T509 | /workspace/coverage/default/46.rstmgr_smoke.2316811176 | Jan 24 01:08:57 PM PST 24 | Jan 24 01:09:32 PM PST 24 | 249989941 ps | ||
| T510 | /workspace/coverage/default/27.rstmgr_reset.4226300167 | Jan 24 01:06:40 PM PST 24 | Jan 24 01:07:44 PM PST 24 | 1355455655 ps | ||
| T69 | /workspace/coverage/default/0.rstmgr_sec_cm.1434988571 | Jan 24 01:04:02 PM PST 24 | Jan 24 01:05:12 PM PST 24 | 17053453797 ps | ||
| T511 | /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.3844914657 | Jan 24 01:07:00 PM PST 24 | Jan 24 01:08:04 PM PST 24 | 1221576784 ps | ||
| T512 | /workspace/coverage/default/8.rstmgr_reset.204761660 | Jan 24 01:05:05 PM PST 24 | Jan 24 01:05:55 PM PST 24 | 1316582728 ps | ||
| T513 | /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.952084267 | Jan 24 01:09:16 PM PST 24 | Jan 24 01:09:55 PM PST 24 | 101328625 ps | ||
| T514 | /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.2493510437 | Jan 24 01:06:20 PM PST 24 | Jan 24 01:07:16 PM PST 24 | 178287657 ps | ||
| T515 | /workspace/coverage/default/29.rstmgr_smoke.1738725900 | Jan 24 01:07:05 PM PST 24 | Jan 24 01:08:03 PM PST 24 | 255292315 ps | ||
| T516 | /workspace/coverage/default/1.rstmgr_por_stretcher.236189136 | Jan 24 01:04:16 PM PST 24 | Jan 24 01:05:01 PM PST 24 | 200955810 ps | ||
| T517 | /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.113931798 | Jan 24 01:04:46 PM PST 24 | Jan 24 01:05:28 PM PST 24 | 244248227 ps | ||
| T518 | /workspace/coverage/default/34.rstmgr_alert_test.1812225948 | Jan 24 01:07:49 PM PST 24 | Jan 24 01:08:39 PM PST 24 | 63616064 ps | ||
| T519 | /workspace/coverage/default/34.rstmgr_por_stretcher.2885329071 | Jan 24 01:07:28 PM PST 24 | Jan 24 01:08:27 PM PST 24 | 104105695 ps | ||
| T520 | /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3073975425 | Jan 24 01:04:46 PM PST 24 | Jan 24 01:05:28 PM PST 24 | 76525688 ps | ||
| T521 | /workspace/coverage/default/33.rstmgr_stress_all.283139858 | Jan 24 01:07:29 PM PST 24 | Jan 24 01:08:32 PM PST 24 | 1386497906 ps | ||
| T522 | /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.357192936 | Jan 24 01:06:56 PM PST 24 | Jan 24 01:07:58 PM PST 24 | 98706103 ps | ||
| T523 | /workspace/coverage/default/27.rstmgr_por_stretcher.3543278954 | Jan 24 01:06:40 PM PST 24 | Jan 24 01:07:40 PM PST 24 | 161233389 ps | ||
| T524 | /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3313411877 | Jan 24 01:05:28 PM PST 24 | Jan 24 01:06:24 PM PST 24 | 1230423825 ps | ||
| T525 | /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3812203854 | Jan 24 01:04:12 PM PST 24 | Jan 24 01:04:57 PM PST 24 | 156163285 ps | ||
| T526 | /workspace/coverage/default/32.rstmgr_reset.3509968350 | Jan 24 01:07:17 PM PST 24 | Jan 24 01:08:19 PM PST 24 | 1401207262 ps | ||
| T527 | /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2325385771 | Jan 24 01:04:18 PM PST 24 | Jan 24 01:05:09 PM PST 24 | 2176623980 ps | ||
| T528 | /workspace/coverage/default/33.rstmgr_alert_test.3652552078 | Jan 24 01:07:29 PM PST 24 | Jan 24 01:08:27 PM PST 24 | 68870266 ps | ||
| T529 | /workspace/coverage/default/49.rstmgr_reset.802440147 | Jan 24 01:09:15 PM PST 24 | Jan 24 01:09:59 PM PST 24 | 989742928 ps | ||
| T530 | /workspace/coverage/default/36.rstmgr_alert_test.1488606019 | Jan 24 01:08:10 PM PST 24 | Jan 24 01:08:50 PM PST 24 | 86204093 ps | ||
| T531 | /workspace/coverage/default/38.rstmgr_sw_rst.3843020259 | Jan 24 01:56:28 PM PST 24 | Jan 24 01:56:36 PM PST 24 | 510741177 ps | ||
| T532 | /workspace/coverage/default/5.rstmgr_smoke.190242546 | Jan 24 01:04:33 PM PST 24 | Jan 24 01:05:14 PM PST 24 | 122147250 ps | ||
| T533 | /workspace/coverage/default/17.rstmgr_sw_rst.895441566 | Jan 24 01:05:55 PM PST 24 | Jan 24 01:06:49 PM PST 24 | 376448640 ps | ||
| T534 | /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.4242076253 | Jan 24 01:06:24 PM PST 24 | Jan 24 01:07:27 PM PST 24 | 2186541103 ps | ||
| T535 | /workspace/coverage/default/25.rstmgr_alert_test.2173541925 | Jan 24 01:06:35 PM PST 24 | Jan 24 01:07:34 PM PST 24 | 76415659 ps | ||
| T536 | /workspace/coverage/default/23.rstmgr_stress_all.189868358 | Jan 24 01:06:28 PM PST 24 | Jan 24 01:07:26 PM PST 24 | 80904982 ps | ||
| T537 | /workspace/coverage/default/24.rstmgr_alert_test.379677378 | Jan 24 01:06:34 PM PST 24 | Jan 24 01:07:34 PM PST 24 | 66369198 ps | ||
| T538 | /workspace/coverage/default/33.rstmgr_smoke.2704855898 | Jan 24 01:07:15 PM PST 24 | Jan 24 01:08:15 PM PST 24 | 251439843 ps | ||
| T539 | /workspace/coverage/default/27.rstmgr_sw_rst.2421007646 | Jan 24 01:06:51 PM PST 24 | Jan 24 01:07:53 PM PST 24 | 396702867 ps | ||
| T540 | /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.4263086301 | Jan 24 01:08:02 PM PST 24 | Jan 24 01:08:45 PM PST 24 | 175691992 ps | ||
| T541 | /workspace/coverage/default/47.rstmgr_smoke.865465857 | Jan 24 01:08:58 PM PST 24 | Jan 24 01:09:33 PM PST 24 | 193855961 ps | ||
| T542 | /workspace/coverage/default/21.rstmgr_alert_test.2227172680 | Jan 24 01:19:32 PM PST 24 | Jan 24 01:20:34 PM PST 24 | 71654974 ps | ||
| T543 | /workspace/coverage/default/40.rstmgr_smoke.1057530733 | Jan 24 01:08:17 PM PST 24 | Jan 24 01:08:57 PM PST 24 | 107445770 ps | ||
| T544 | /workspace/coverage/default/22.rstmgr_sw_rst.874548870 | Jan 24 01:06:14 PM PST 24 | Jan 24 01:07:11 PM PST 24 | 469793099 ps | ||
| T545 | /workspace/coverage/default/1.rstmgr_stress_all.3185166558 | Jan 24 01:04:07 PM PST 24 | Jan 24 01:04:53 PM PST 24 | 219065214 ps | ||
| T546 | /workspace/coverage/default/40.rstmgr_sw_rst.1293730694 | Jan 24 01:08:17 PM PST 24 | Jan 24 01:08:57 PM PST 24 | 147706129 ps | ||
| T547 | /workspace/coverage/default/46.rstmgr_alert_test.777929796 | Jan 24 01:09:04 PM PST 24 | Jan 24 01:09:39 PM PST 24 | 69489562 ps | ||
| T548 | /workspace/coverage/default/40.rstmgr_reset.1878096310 | Jan 24 01:42:50 PM PST 24 | Jan 24 01:43:34 PM PST 24 | 1049285701 ps | ||
| T549 | /workspace/coverage/default/10.rstmgr_por_stretcher.3856747348 | Jan 24 01:05:10 PM PST 24 | Jan 24 01:05:58 PM PST 24 | 128863834 ps | ||
| T550 | /workspace/coverage/default/43.rstmgr_stress_all.2393705600 | Jan 24 01:08:44 PM PST 24 | Jan 24 01:09:45 PM PST 24 | 5051697648 ps | ||
| T551 | /workspace/coverage/default/45.rstmgr_stress_all.121901919 | Jan 24 01:08:59 PM PST 24 | Jan 24 01:10:08 PM PST 24 | 8506933758 ps | ||
| T552 | /workspace/coverage/default/11.rstmgr_reset.316326648 | Jan 24 01:05:06 PM PST 24 | Jan 24 01:05:55 PM PST 24 | 847462345 ps | ||
| T553 | /workspace/coverage/default/12.rstmgr_stress_all.638630634 | Jan 24 01:05:29 PM PST 24 | Jan 24 01:06:37 PM PST 24 | 4143236416 ps | ||
| T554 | /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.1471703498 | Jan 24 01:23:32 PM PST 24 | Jan 24 01:24:18 PM PST 24 | 66574623 ps | ||
| T555 | /workspace/coverage/default/47.rstmgr_sw_rst.1094510944 | Jan 24 01:08:58 PM PST 24 | Jan 24 01:09:34 PM PST 24 | 333958453 ps | ||
| T556 | /workspace/coverage/default/14.rstmgr_stress_all.382259585 | Jan 24 01:09:53 PM PST 24 | Jan 24 01:10:44 PM PST 24 | 3314691088 ps | ||
| T557 | /workspace/coverage/default/19.rstmgr_stress_all.1637621920 | Jan 24 02:54:58 PM PST 24 | Jan 24 02:55:26 PM PST 24 | 3802894013 ps | ||
| T558 | /workspace/coverage/default/25.rstmgr_smoke.3374814784 | Jan 24 01:06:31 PM PST 24 | Jan 24 01:07:31 PM PST 24 | 236442167 ps | ||
| T559 | /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2918404802 | Jan 24 02:03:30 PM PST 24 | Jan 24 02:04:37 PM PST 24 | 244650259 ps | ||
| T560 | /workspace/coverage/default/9.rstmgr_stress_all.4168694272 | Jan 24 01:05:07 PM PST 24 | Jan 24 01:06:23 PM PST 24 | 8077090568 ps | ||
| T561 | /workspace/coverage/default/48.rstmgr_reset.3886289502 | Jan 24 01:09:16 PM PST 24 | Jan 24 01:10:01 PM PST 24 | 1638052208 ps | ||
| T562 | /workspace/coverage/default/49.rstmgr_sw_rst.1680019373 | Jan 24 01:09:20 PM PST 24 | Jan 24 01:10:00 PM PST 24 | 124947695 ps | ||
| T563 | /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2662632666 | Jan 24 01:07:59 PM PST 24 | Jan 24 01:08:43 PM PST 24 | 158540170 ps | ||
| T564 | /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2630096488 | Jan 24 01:04:18 PM PST 24 | Jan 24 01:05:02 PM PST 24 | 244781434 ps | ||
| T565 | /workspace/coverage/default/46.rstmgr_por_stretcher.1771210652 | Jan 24 01:08:56 PM PST 24 | Jan 24 01:09:30 PM PST 24 | 191987419 ps | ||
| T566 | /workspace/coverage/default/5.rstmgr_alert_test.2175952940 | Jan 24 01:04:41 PM PST 24 | Jan 24 01:05:19 PM PST 24 | 54868604 ps | ||
| T567 | /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2600771112 | Jan 24 01:04:30 PM PST 24 | Jan 24 01:05:11 PM PST 24 | 243790887 ps | ||
| T568 | /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1310570827 | Jan 24 01:09:17 PM PST 24 | Jan 24 01:09:57 PM PST 24 | 244986284 ps | ||
| T569 | /workspace/coverage/default/35.rstmgr_por_stretcher.271883165 | Jan 24 01:07:44 PM PST 24 | Jan 24 01:08:36 PM PST 24 | 227406011 ps | ||
| T570 | /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.242075603 | Jan 24 01:06:33 PM PST 24 | Jan 24 01:07:33 PM PST 24 | 245108581 ps | ||
| T571 | /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.268110108 | Jan 24 01:41:42 PM PST 24 | Jan 24 01:41:47 PM PST 24 | 106580963 ps | ||
| T572 | /workspace/coverage/default/48.rstmgr_stress_all.1819079256 | Jan 24 01:09:17 PM PST 24 | Jan 24 01:10:40 PM PST 24 | 13203300098 ps | ||
| T573 | /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2507493742 | Jan 24 01:06:14 PM PST 24 | Jan 24 01:07:09 PM PST 24 | 146109052 ps | ||
| T70 | /workspace/coverage/default/2.rstmgr_sec_cm.2319505462 | Jan 24 01:04:14 PM PST 24 | Jan 24 01:05:14 PM PST 24 | 8646602944 ps | ||
| T574 | /workspace/coverage/default/15.rstmgr_smoke.3292467393 | Jan 24 01:28:59 PM PST 24 | Jan 24 01:29:17 PM PST 24 | 203869784 ps | ||
| T575 | /workspace/coverage/default/4.rstmgr_sw_rst.579649815 | Jan 24 01:04:25 PM PST 24 | Jan 24 01:05:10 PM PST 24 | 367376788 ps | ||
| T576 | /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.344365178 | Jan 24 01:04:44 PM PST 24 | Jan 24 01:05:29 PM PST 24 | 1222865614 ps | ||
| T577 | /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3605990438 | Jan 24 01:06:37 PM PST 24 | Jan 24 01:07:37 PM PST 24 | 244872226 ps | ||
| T578 | /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.4050488492 | Jan 24 01:04:12 PM PST 24 | Jan 24 01:04:57 PM PST 24 | 119869144 ps | ||
| T579 | /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3498142843 | Jan 24 01:06:26 PM PST 24 | Jan 24 01:07:24 PM PST 24 | 244946079 ps | ||
| T580 | /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1728777463 | Jan 24 01:09:15 PM PST 24 | Jan 24 01:09:56 PM PST 24 | 266205850 ps | ||
| T581 | /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.307310404 | Jan 24 01:08:40 PM PST 24 | Jan 24 01:09:24 PM PST 24 | 1217247186 ps | ||
| T582 | /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.863265117 | Jan 24 01:08:43 PM PST 24 | Jan 24 01:09:22 PM PST 24 | 247077755 ps | ||
| T583 | /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1315248389 | Jan 24 01:07:28 PM PST 24 | Jan 24 01:08:27 PM PST 24 | 178405066 ps | ||
| T584 | /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.1877429623 | Jan 24 01:08:56 PM PST 24 | Jan 24 01:09:31 PM PST 24 | 267648636 ps | ||
| T585 | /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2992714004 | Jan 24 01:07:00 PM PST 24 | Jan 24 01:07:59 PM PST 24 | 145116194 ps | ||
| T586 | /workspace/coverage/default/24.rstmgr_stress_all.241166879 | Jan 24 01:06:33 PM PST 24 | Jan 24 01:07:33 PM PST 24 | 105910395 ps | ||
| T587 | /workspace/coverage/default/46.rstmgr_sw_rst.1010196454 | Jan 24 01:08:58 PM PST 24 | Jan 24 01:09:34 PM PST 24 | 466903281 ps | ||
| T588 | /workspace/coverage/default/16.rstmgr_reset.14475167 | Jan 24 01:05:47 PM PST 24 | Jan 24 01:06:45 PM PST 24 | 1565798830 ps | ||
| T589 | /workspace/coverage/default/21.rstmgr_stress_all.966460764 | Jan 24 01:06:18 PM PST 24 | Jan 24 01:07:29 PM PST 24 | 3133840465 ps | ||
| T590 | /workspace/coverage/default/11.rstmgr_alert_test.2060640040 | Jan 24 01:05:08 PM PST 24 | Jan 24 01:05:56 PM PST 24 | 69158762 ps | ||
| T591 | /workspace/coverage/default/19.rstmgr_por_stretcher.4206449780 | Jan 24 01:05:59 PM PST 24 | Jan 24 01:06:52 PM PST 24 | 232453031 ps | ||
| T592 | /workspace/coverage/default/37.rstmgr_sw_rst.1246652733 | Jan 24 01:08:05 PM PST 24 | Jan 24 01:08:48 PM PST 24 | 350367340 ps | ||
| T593 | /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3024796556 | Jan 24 01:08:02 PM PST 24 | Jan 24 01:08:45 PM PST 24 | 244413803 ps | ||
| T594 | /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3057179496 | Jan 24 01:07:44 PM PST 24 | Jan 24 01:08:37 PM PST 24 | 97155442 ps | ||
| T595 | /workspace/coverage/default/20.rstmgr_smoke.2482239280 | Jan 24 01:14:34 PM PST 24 | Jan 24 01:15:01 PM PST 24 | 258333243 ps | ||
| T596 | /workspace/coverage/default/32.rstmgr_sw_rst.1107693379 | Jan 24 01:07:17 PM PST 24 | Jan 24 01:08:15 PM PST 24 | 132582122 ps | ||
| T597 | /workspace/coverage/default/42.rstmgr_por_stretcher.1879118731 | Jan 24 01:08:31 PM PST 24 | Jan 24 01:09:05 PM PST 24 | 82945465 ps | ||
| T598 | /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2863534062 | Jan 24 01:05:59 PM PST 24 | Jan 24 01:06:52 PM PST 24 | 88908733 ps | ||
| T599 | /workspace/coverage/default/5.rstmgr_stress_all.516406524 | Jan 24 01:04:39 PM PST 24 | Jan 24 01:06:01 PM PST 24 | 13901356268 ps | ||
| T600 | /workspace/coverage/default/34.rstmgr_smoke.3647382656 | Jan 24 01:07:29 PM PST 24 | Jan 24 01:08:28 PM PST 24 | 115250036 ps | ||
| T601 | /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1748412128 | Jan 24 01:07:32 PM PST 24 | Jan 24 01:08:30 PM PST 24 | 109576610 ps | ||
| T602 | /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2363848428 | Jan 24 01:32:25 PM PST 24 | Jan 24 01:33:06 PM PST 24 | 245366290 ps | ||
| T603 | /workspace/coverage/default/36.rstmgr_stress_all.1453470433 | Jan 24 01:08:01 PM PST 24 | Jan 24 01:09:25 PM PST 24 | 12186416686 ps | ||
| T604 | /workspace/coverage/default/30.rstmgr_por_stretcher.2447051110 | Jan 24 02:41:11 PM PST 24 | Jan 24 02:41:26 PM PST 24 | 144291134 ps | ||
| T605 | /workspace/coverage/default/27.rstmgr_smoke.828998216 | Jan 24 01:06:48 PM PST 24 | Jan 24 01:07:48 PM PST 24 | 265816637 ps | ||
| T606 | /workspace/coverage/default/20.rstmgr_stress_all.2012215988 | Jan 24 01:18:26 PM PST 24 | Jan 24 01:19:11 PM PST 24 | 852623460 ps | ||
| T607 | /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1625057180 | Jan 24 01:07:00 PM PST 24 | Jan 24 01:08:00 PM PST 24 | 111439987 ps | ||
| T608 | /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.2389310081 | Jan 24 01:35:42 PM PST 24 | Jan 24 01:36:11 PM PST 24 | 154110690 ps | ||
| T609 | /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.884212749 | Jan 24 01:08:22 PM PST 24 | Jan 24 01:09:05 PM PST 24 | 1884671381 ps | ||
| T610 | /workspace/coverage/default/22.rstmgr_smoke.1204447354 | Jan 24 01:21:47 PM PST 24 | Jan 24 01:22:46 PM PST 24 | 199705990 ps | ||
| T611 | /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.2520274336 | Jan 24 01:08:24 PM PST 24 | Jan 24 01:09:05 PM PST 24 | 1230244134 ps | ||
| T612 | /workspace/coverage/default/48.rstmgr_sw_rst.28651270 | Jan 24 01:09:12 PM PST 24 | Jan 24 01:09:51 PM PST 24 | 121872887 ps | ||
| T613 | /workspace/coverage/default/13.rstmgr_reset.1965608027 | Jan 24 01:05:31 PM PST 24 | Jan 24 01:06:27 PM PST 24 | 1729163819 ps | ||
| T614 | /workspace/coverage/default/46.rstmgr_stress_all.918909460 | Jan 24 01:08:58 PM PST 24 | Jan 24 01:10:17 PM PST 24 | 12010006351 ps | ||
| T615 | /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1870893646 | Jan 24 01:06:14 PM PST 24 | Jan 24 01:07:14 PM PST 24 | 1222036327 ps | ||
| T616 | /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1057621910 | Jan 24 01:28:41 PM PST 24 | Jan 24 01:29:12 PM PST 24 | 2165384573 ps | ||
| T617 | /workspace/coverage/default/13.rstmgr_sw_rst.309462956 | Jan 24 01:05:20 PM PST 24 | Jan 24 01:06:10 PM PST 24 | 116745152 ps | ||
| T618 | /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3526994098 | Jan 24 01:07:46 PM PST 24 | Jan 24 01:08:38 PM PST 24 | 245040916 ps |
| Test location | /workspace/coverage/default/10.rstmgr_reset.2939050006 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1699961702 ps |
| CPU time | 6.2 seconds |
| Started | Jan 24 01:05:07 PM PST 24 |
| Finished | Jan 24 01:06:00 PM PST 24 |
| Peak memory | 199320 kb |
| Host | smart-dda920fd-bdc0-48f4-a877-63bd9b4e2565 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2939050006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2939050006 |
| Directory | /workspace/10.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/19.rstmgr_sw_rst.1693948750 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 153958342 ps |
| CPU time | 1.78 seconds |
| Started | Jan 24 01:06:14 PM PST 24 |
| Finished | Jan 24 01:07:10 PM PST 24 |
| Peak memory | 199660 kb |
| Host | smart-994222c8-b20a-4b08-a80f-2e2a7118dcda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1693948750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.1693948750 |
| Directory | /workspace/19.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2095042824 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 787784649 ps |
| CPU time | 2.77 seconds |
| Started | Jan 24 12:57:40 PM PST 24 |
| Finished | Jan 24 12:58:07 PM PST 24 |
| Peak memory | 199524 kb |
| Host | smart-85be4e59-bcf7-4cbd-a8c0-7d58942afff8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095042824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er r.2095042824 |
| Directory | /workspace/19.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/default/1.rstmgr_sec_cm.231927293 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 16866832485 ps |
| CPU time | 24.67 seconds |
| Started | Jan 24 01:04:14 PM PST 24 |
| Finished | Jan 24 01:05:23 PM PST 24 |
| Peak memory | 217560 kb |
| Host | smart-92624e96-69e0-4897-a39b-4dc1c54d7c08 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231927293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.231927293 |
| Directory | /workspace/1.rstmgr_sec_cm/latest |
| Test location | /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.1439465806 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1218711752 ps |
| CPU time | 5.56 seconds |
| Started | Jan 24 01:05:59 PM PST 24 |
| Finished | Jan 24 01:06:56 PM PST 24 |
| Peak memory | 216872 kb |
| Host | smart-003f2f05-9ec6-4863-8025-f33277bba62e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1439465806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.1439465806 |
| Directory | /workspace/19.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1778796380 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 185565683 ps |
| CPU time | 2.64 seconds |
| Started | Jan 24 12:57:12 PM PST 24 |
| Finished | Jan 24 12:57:40 PM PST 24 |
| Peak memory | 215492 kb |
| Host | smart-57330ebd-7c46-4c7f-969e-88a1551b0d8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778796380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1778796380 |
| Directory | /workspace/11.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/default/22.rstmgr_stress_all.3845073980 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 6681794150 ps |
| CPU time | 27 seconds |
| Started | Jan 24 01:06:11 PM PST 24 |
| Finished | Jan 24 01:07:34 PM PST 24 |
| Peak memory | 199636 kb |
| Host | smart-3fbe8858-e3c6-425f-ae0e-e03e2d8328e5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845073980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.3845073980 |
| Directory | /workspace/22.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/15.rstmgr_alert_test.615050872 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 62606619 ps |
| CPU time | 0.77 seconds |
| Started | Jan 24 01:44:20 PM PST 24 |
| Finished | Jan 24 01:44:38 PM PST 24 |
| Peak memory | 199516 kb |
| Host | smart-887efc86-24b2-49f6-88eb-807a9ccca8cc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615050872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.615050872 |
| Directory | /workspace/15.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.257032957 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 152450658 ps |
| CPU time | 1.1 seconds |
| Started | Jan 24 01:05:07 PM PST 24 |
| Finished | Jan 24 01:05:55 PM PST 24 |
| Peak memory | 199168 kb |
| Host | smart-82343a2d-0971-4104-93fb-305e50719260 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=257032957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.257032957 |
| Directory | /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3623310193 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 284870142 ps |
| CPU time | 1.44 seconds |
| Started | Jan 24 01:05:29 PM PST 24 |
| Finished | Jan 24 01:06:21 PM PST 24 |
| Peak memory | 199588 kb |
| Host | smart-4ffd9a7e-7630-40fc-b6fe-15efa913d198 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3623310193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3623310193 |
| Directory | /workspace/12.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1255231677 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 2160505391 ps |
| CPU time | 8.5 seconds |
| Started | Jan 24 01:06:57 PM PST 24 |
| Finished | Jan 24 01:08:06 PM PST 24 |
| Peak memory | 221788 kb |
| Host | smart-146e7757-2c84-41e2-8db6-e4fa23b0c93a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1255231677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1255231677 |
| Directory | /workspace/29.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3644322237 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 910500364 ps |
| CPU time | 3.04 seconds |
| Started | Jan 24 12:57:17 PM PST 24 |
| Finished | Jan 24 12:57:46 PM PST 24 |
| Peak memory | 199668 kb |
| Host | smart-38643176-1757-4c4d-8d8a-e3d2ea5733da |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644322237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er r.3644322237 |
| Directory | /workspace/12.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.804779199 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 423199541 ps |
| CPU time | 1.76 seconds |
| Started | Jan 24 12:57:38 PM PST 24 |
| Finished | Jan 24 12:58:02 PM PST 24 |
| Peak memory | 199680 kb |
| Host | smart-fa940c76-2965-4ba2-b734-472047d27467 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804779199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err .804779199 |
| Directory | /workspace/18.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.4236537367 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 2355096204 ps |
| CPU time | 8.27 seconds |
| Started | Jan 24 01:07:29 PM PST 24 |
| Finished | Jan 24 01:08:35 PM PST 24 |
| Peak memory | 218344 kb |
| Host | smart-453f675f-b6e9-4931-a392-2fad2d5f46da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4236537367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.4236537367 |
| Directory | /workspace/34.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2953800386 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 891743252 ps |
| CPU time | 2.82 seconds |
| Started | Jan 24 12:56:46 PM PST 24 |
| Finished | Jan 24 12:57:16 PM PST 24 |
| Peak memory | 198096 kb |
| Host | smart-a4e93058-eef3-4765-8f2b-40b309b5698c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953800386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err .2953800386 |
| Directory | /workspace/5.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3188795442 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 231158023 ps |
| CPU time | 1.66 seconds |
| Started | Jan 24 01:58:48 PM PST 24 |
| Finished | Jan 24 01:58:54 PM PST 24 |
| Peak memory | 199756 kb |
| Host | smart-f5ee3edd-7066-4da8-838c-75891d11a4a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188795442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.3 188795442 |
| Directory | /workspace/0.rstmgr_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2851020039 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 71873015 ps |
| CPU time | 0.87 seconds |
| Started | Jan 24 01:23:25 PM PST 24 |
| Finished | Jan 24 01:24:13 PM PST 24 |
| Peak memory | 199632 kb |
| Host | smart-ef471be9-06f1-4cbc-a601-412fa7297286 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851020039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa me_csr_outstanding.2851020039 |
| Directory | /workspace/0.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/12.rstmgr_por_stretcher.221526798 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 212289550 ps |
| CPU time | 0.87 seconds |
| Started | Jan 24 01:05:23 PM PST 24 |
| Finished | Jan 24 01:06:13 PM PST 24 |
| Peak memory | 199408 kb |
| Host | smart-8e0a5436-77c9-457b-b44b-4adae42f8f8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=221526798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.221526798 |
| Directory | /workspace/12.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2632912442 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 269820661 ps |
| CPU time | 3.38 seconds |
| Started | Jan 24 12:56:32 PM PST 24 |
| Finished | Jan 24 12:57:05 PM PST 24 |
| Peak memory | 199796 kb |
| Host | smart-33813247-1b2e-4734-9665-bd1babf42a8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632912442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.2 632912442 |
| Directory | /workspace/0.rstmgr_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2472540451 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 141283693 ps |
| CPU time | 0.96 seconds |
| Started | Jan 24 01:03:11 PM PST 24 |
| Finished | Jan 24 01:03:34 PM PST 24 |
| Peak memory | 199448 kb |
| Host | smart-6e282526-fca9-4e20-821a-28cd580fa901 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472540451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2 472540451 |
| Directory | /workspace/0.rstmgr_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2690440771 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 128526776 ps |
| CPU time | 1.04 seconds |
| Started | Jan 24 12:56:29 PM PST 24 |
| Finished | Jan 24 12:57:00 PM PST 24 |
| Peak memory | 199464 kb |
| Host | smart-a8d95166-6641-4fc1-94c4-425401472335 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690440771 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2690440771 |
| Directory | /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3569718500 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 76607893 ps |
| CPU time | 0.9 seconds |
| Started | Jan 24 12:56:31 PM PST 24 |
| Finished | Jan 24 12:57:01 PM PST 24 |
| Peak memory | 199516 kb |
| Host | smart-bc4563e2-b35f-41eb-97e3-b2e85623e3c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569718500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.3569718500 |
| Directory | /workspace/0.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3643236824 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 177945695 ps |
| CPU time | 2.43 seconds |
| Started | Jan 24 01:15:22 PM PST 24 |
| Finished | Jan 24 01:16:09 PM PST 24 |
| Peak memory | 199836 kb |
| Host | smart-f616b7c5-8b5b-46a5-a392-ef658d5915d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643236824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.3643236824 |
| Directory | /workspace/0.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3602226446 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 475996172 ps |
| CPU time | 1.92 seconds |
| Started | Jan 24 12:56:32 PM PST 24 |
| Finished | Jan 24 12:57:03 PM PST 24 |
| Peak memory | 199760 kb |
| Host | smart-8c09a4c7-67c4-40fc-bed1-35dbfd6bf97b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602226446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err .3602226446 |
| Directory | /workspace/0.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1061032345 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 100570943 ps |
| CPU time | 1.36 seconds |
| Started | Jan 24 12:56:38 PM PST 24 |
| Finished | Jan 24 12:57:09 PM PST 24 |
| Peak memory | 199700 kb |
| Host | smart-45f99eba-9ee4-4686-81d6-968a6e9f9620 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061032345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.1 061032345 |
| Directory | /workspace/1.rstmgr_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.154393527 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 483877196 ps |
| CPU time | 6.03 seconds |
| Started | Jan 24 12:56:41 PM PST 24 |
| Finished | Jan 24 12:57:15 PM PST 24 |
| Peak memory | 199620 kb |
| Host | smart-bae61d5f-5582-4c6e-a4f2-d7205d6dd35a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154393527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.154393527 |
| Directory | /workspace/1.rstmgr_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4182819563 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 135748490 ps |
| CPU time | 0.95 seconds |
| Started | Jan 24 12:56:40 PM PST 24 |
| Finished | Jan 24 12:57:10 PM PST 24 |
| Peak memory | 199508 kb |
| Host | smart-7174da79-1c72-4074-823c-cb5e1ceb1048 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182819563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.4 182819563 |
| Directory | /workspace/1.rstmgr_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1065582287 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 116490928 ps |
| CPU time | 1.18 seconds |
| Started | Jan 24 12:56:48 PM PST 24 |
| Finished | Jan 24 12:57:16 PM PST 24 |
| Peak memory | 199572 kb |
| Host | smart-0b1125b4-4f1d-4c53-ac94-330bb461af3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065582287 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.1065582287 |
| Directory | /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2968700395 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 66281460 ps |
| CPU time | 0.8 seconds |
| Started | Jan 24 01:23:12 PM PST 24 |
| Finished | Jan 24 01:24:04 PM PST 24 |
| Peak memory | 199628 kb |
| Host | smart-d6e96bb5-0dab-4fe0-af77-354e8f5f24a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968700395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2968700395 |
| Directory | /workspace/1.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2970657196 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 286037786 ps |
| CPU time | 1.61 seconds |
| Started | Jan 24 01:19:04 PM PST 24 |
| Finished | Jan 24 01:20:06 PM PST 24 |
| Peak memory | 199784 kb |
| Host | smart-aa8306eb-f7fc-4ac6-a866-686dde0f3dc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970657196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa me_csr_outstanding.2970657196 |
| Directory | /workspace/1.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2271380450 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 105826951 ps |
| CPU time | 1.39 seconds |
| Started | Jan 24 01:38:29 PM PST 24 |
| Finished | Jan 24 01:38:55 PM PST 24 |
| Peak memory | 199840 kb |
| Host | smart-6817e941-e2ba-4aae-8d67-db765ff37b3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271380450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2271380450 |
| Directory | /workspace/1.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1055577186 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 413817066 ps |
| CPU time | 1.76 seconds |
| Started | Jan 24 12:56:28 PM PST 24 |
| Finished | Jan 24 12:57:01 PM PST 24 |
| Peak memory | 199608 kb |
| Host | smart-aa64f63e-9c8e-4a2c-9ca9-23810e1aaba3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055577186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err .1055577186 |
| Directory | /workspace/1.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.4140164242 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 104983795 ps |
| CPU time | 0.94 seconds |
| Started | Jan 24 12:57:11 PM PST 24 |
| Finished | Jan 24 12:57:37 PM PST 24 |
| Peak memory | 199548 kb |
| Host | smart-9db6289e-2f43-403f-b4ca-1edf684d9ce2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140164242 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.4140164242 |
| Directory | /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2188248216 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 74744078 ps |
| CPU time | 0.85 seconds |
| Started | Jan 24 12:57:11 PM PST 24 |
| Finished | Jan 24 12:57:36 PM PST 24 |
| Peak memory | 199516 kb |
| Host | smart-1b53e1db-9b73-4936-be8a-b7f84feaa0c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188248216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2188248216 |
| Directory | /workspace/10.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.238064742 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 71193789 ps |
| CPU time | 0.9 seconds |
| Started | Jan 24 12:57:14 PM PST 24 |
| Finished | Jan 24 12:57:40 PM PST 24 |
| Peak memory | 199512 kb |
| Host | smart-74747421-2175-41a5-94e9-e5d15e5bd292 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238064742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa me_csr_outstanding.238064742 |
| Directory | /workspace/10.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3342130393 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 166912930 ps |
| CPU time | 2.48 seconds |
| Started | Jan 24 12:57:07 PM PST 24 |
| Finished | Jan 24 12:57:32 PM PST 24 |
| Peak memory | 207972 kb |
| Host | smart-cfe21c4a-8e3c-4abc-ab1f-e226ee49cb5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342130393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3342130393 |
| Directory | /workspace/10.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1841054317 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 908700541 ps |
| CPU time | 3.12 seconds |
| Started | Jan 24 12:57:09 PM PST 24 |
| Finished | Jan 24 12:57:35 PM PST 24 |
| Peak memory | 199716 kb |
| Host | smart-127a08df-2660-40df-b99d-f9c7074eb203 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841054317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er r.1841054317 |
| Directory | /workspace/10.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.507135128 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 192832631 ps |
| CPU time | 1.99 seconds |
| Started | Jan 24 12:57:16 PM PST 24 |
| Finished | Jan 24 12:57:43 PM PST 24 |
| Peak memory | 215332 kb |
| Host | smart-edfb539b-3241-4cf3-a9c1-6496168fc3cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507135128 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.507135128 |
| Directory | /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2218689304 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 80108982 ps |
| CPU time | 0.84 seconds |
| Started | Jan 24 12:57:17 PM PST 24 |
| Finished | Jan 24 12:57:43 PM PST 24 |
| Peak memory | 199488 kb |
| Host | smart-d2a2765b-cbdf-4f0a-8568-171afa48bb01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218689304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.2218689304 |
| Directory | /workspace/11.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2179445757 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 76523316 ps |
| CPU time | 0.97 seconds |
| Started | Jan 24 12:57:11 PM PST 24 |
| Finished | Jan 24 12:57:36 PM PST 24 |
| Peak memory | 199500 kb |
| Host | smart-a7eb5c74-5aeb-4056-854e-77b1d6e74214 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179445757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s ame_csr_outstanding.2179445757 |
| Directory | /workspace/11.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2357324592 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 469734851 ps |
| CPU time | 1.71 seconds |
| Started | Jan 24 12:57:16 PM PST 24 |
| Finished | Jan 24 12:57:43 PM PST 24 |
| Peak memory | 199620 kb |
| Host | smart-f864bc0b-4d1b-4020-8599-f124c7d3a854 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357324592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er r.2357324592 |
| Directory | /workspace/11.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.4060445327 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 140416844 ps |
| CPU time | 1.08 seconds |
| Started | Jan 24 12:57:14 PM PST 24 |
| Finished | Jan 24 12:57:40 PM PST 24 |
| Peak memory | 199620 kb |
| Host | smart-5860b736-5bc5-4ff7-83b3-a2b5854e48e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060445327 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.4060445327 |
| Directory | /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.850825275 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 81369009 ps |
| CPU time | 0.88 seconds |
| Started | Jan 24 12:57:14 PM PST 24 |
| Finished | Jan 24 12:57:40 PM PST 24 |
| Peak memory | 199432 kb |
| Host | smart-60c7c27d-4565-4700-b79c-e7895d083b17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850825275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.850825275 |
| Directory | /workspace/12.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3118339337 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 140322016 ps |
| CPU time | 1.28 seconds |
| Started | Jan 24 12:57:14 PM PST 24 |
| Finished | Jan 24 12:57:40 PM PST 24 |
| Peak memory | 199696 kb |
| Host | smart-a4e4ec8d-9ae9-4333-bc6f-9a74ba2d0d4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118339337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s ame_csr_outstanding.3118339337 |
| Directory | /workspace/12.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2571081825 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 258241607 ps |
| CPU time | 2.01 seconds |
| Started | Jan 24 12:57:12 PM PST 24 |
| Finished | Jan 24 12:57:39 PM PST 24 |
| Peak memory | 199832 kb |
| Host | smart-56158b65-b12f-483f-a159-b270575715fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571081825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.2571081825 |
| Directory | /workspace/12.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1614908675 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 159444623 ps |
| CPU time | 1.02 seconds |
| Started | Jan 24 12:57:16 PM PST 24 |
| Finished | Jan 24 12:57:42 PM PST 24 |
| Peak memory | 199472 kb |
| Host | smart-689b37f8-e942-4313-9559-d670fbd1f9dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614908675 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.1614908675 |
| Directory | /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2886111881 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 61410610 ps |
| CPU time | 0.81 seconds |
| Started | Jan 24 12:57:16 PM PST 24 |
| Finished | Jan 24 12:57:42 PM PST 24 |
| Peak memory | 199360 kb |
| Host | smart-21fa1960-35f7-4e60-9b37-50c410cb8fe1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886111881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2886111881 |
| Directory | /workspace/13.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1366003163 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 88397694 ps |
| CPU time | 0.98 seconds |
| Started | Jan 24 12:57:16 PM PST 24 |
| Finished | Jan 24 12:57:42 PM PST 24 |
| Peak memory | 199560 kb |
| Host | smart-f1f3b0bf-4d5a-4591-90f9-7a059aba7b7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366003163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s ame_csr_outstanding.1366003163 |
| Directory | /workspace/13.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2664003631 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 213192892 ps |
| CPU time | 2.93 seconds |
| Started | Jan 24 12:57:18 PM PST 24 |
| Finished | Jan 24 12:57:46 PM PST 24 |
| Peak memory | 215452 kb |
| Host | smart-bb8c4c2e-1be4-469f-a399-b2beee89054a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664003631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2664003631 |
| Directory | /workspace/13.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3977743412 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 1259783921 ps |
| CPU time | 3.58 seconds |
| Started | Jan 24 12:57:14 PM PST 24 |
| Finished | Jan 24 12:57:42 PM PST 24 |
| Peak memory | 199672 kb |
| Host | smart-915686ee-2b47-41c7-8545-d74f7e5b6bc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977743412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er r.3977743412 |
| Directory | /workspace/13.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1276093798 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 180702950 ps |
| CPU time | 1.18 seconds |
| Started | Jan 24 12:57:15 PM PST 24 |
| Finished | Jan 24 12:57:41 PM PST 24 |
| Peak memory | 199608 kb |
| Host | smart-de4718ee-353e-43c9-ab60-d3b0acb387e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276093798 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.1276093798 |
| Directory | /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2691277755 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 95330419 ps |
| CPU time | 0.89 seconds |
| Started | Jan 24 12:57:13 PM PST 24 |
| Finished | Jan 24 12:57:39 PM PST 24 |
| Peak memory | 198972 kb |
| Host | smart-8bbf686f-d475-481c-b495-dc7a54141bb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691277755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.2691277755 |
| Directory | /workspace/14.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1738328511 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 121657995 ps |
| CPU time | 1.04 seconds |
| Started | Jan 24 12:57:16 PM PST 24 |
| Finished | Jan 24 12:57:42 PM PST 24 |
| Peak memory | 199320 kb |
| Host | smart-0bcbb8d4-542a-407c-99e5-585059c4d6f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738328511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s ame_csr_outstanding.1738328511 |
| Directory | /workspace/14.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1623736561 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 327107706 ps |
| CPU time | 2.61 seconds |
| Started | Jan 24 12:57:15 PM PST 24 |
| Finished | Jan 24 12:57:43 PM PST 24 |
| Peak memory | 199788 kb |
| Host | smart-2b27b93e-8ced-4953-a483-6aa1e6b73c31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623736561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.1623736561 |
| Directory | /workspace/14.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.246300392 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 487165314 ps |
| CPU time | 2.06 seconds |
| Started | Jan 24 12:57:13 PM PST 24 |
| Finished | Jan 24 12:57:40 PM PST 24 |
| Peak memory | 199148 kb |
| Host | smart-69252406-6f22-482d-bfa2-6cde138168f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246300392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err .246300392 |
| Directory | /workspace/14.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1105351177 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 116206413 ps |
| CPU time | 1.24 seconds |
| Started | Jan 24 12:57:38 PM PST 24 |
| Finished | Jan 24 12:58:02 PM PST 24 |
| Peak memory | 207744 kb |
| Host | smart-efe7f75a-972a-4fce-93cf-27b11b8eaba1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105351177 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.1105351177 |
| Directory | /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1368783204 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 60730167 ps |
| CPU time | 0.79 seconds |
| Started | Jan 24 12:57:36 PM PST 24 |
| Finished | Jan 24 12:57:59 PM PST 24 |
| Peak memory | 199432 kb |
| Host | smart-44f0960f-20a3-41de-a9c6-a1196f675c99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368783204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.1368783204 |
| Directory | /workspace/15.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2991546740 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 79819846 ps |
| CPU time | 0.89 seconds |
| Started | Jan 24 12:57:36 PM PST 24 |
| Finished | Jan 24 12:58:00 PM PST 24 |
| Peak memory | 199436 kb |
| Host | smart-19c1dfdd-8e22-43cf-ae83-67e61e877ecb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991546740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s ame_csr_outstanding.2991546740 |
| Directory | /workspace/15.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2182426384 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 364998593 ps |
| CPU time | 2.57 seconds |
| Started | Jan 24 12:57:33 PM PST 24 |
| Finished | Jan 24 12:57:58 PM PST 24 |
| Peak memory | 199732 kb |
| Host | smart-4535d6d5-fd02-4393-9c89-900d4ebc8fde |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182426384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2182426384 |
| Directory | /workspace/15.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.4085717360 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 433414881 ps |
| CPU time | 1.8 seconds |
| Started | Jan 24 12:57:33 PM PST 24 |
| Finished | Jan 24 12:57:58 PM PST 24 |
| Peak memory | 199656 kb |
| Host | smart-9c73a823-9dbe-46ed-a347-9fcffcef6d52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085717360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er r.4085717360 |
| Directory | /workspace/15.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.4217676930 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 119565043 ps |
| CPU time | 0.93 seconds |
| Started | Jan 24 12:57:32 PM PST 24 |
| Finished | Jan 24 12:57:56 PM PST 24 |
| Peak memory | 199548 kb |
| Host | smart-d83d3830-205e-4feb-a9b4-53baab6fad96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217676930 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.4217676930 |
| Directory | /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1184809883 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 67075634 ps |
| CPU time | 0.8 seconds |
| Started | Jan 24 12:57:33 PM PST 24 |
| Finished | Jan 24 12:57:56 PM PST 24 |
| Peak memory | 199560 kb |
| Host | smart-1a93f69b-4633-40bd-86a1-06f3de7f9a8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184809883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.1184809883 |
| Directory | /workspace/16.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2942554094 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 259663523 ps |
| CPU time | 1.6 seconds |
| Started | Jan 24 12:57:32 PM PST 24 |
| Finished | Jan 24 12:57:57 PM PST 24 |
| Peak memory | 199676 kb |
| Host | smart-10fa173e-cceb-49a2-8c29-d61692f5c618 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942554094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s ame_csr_outstanding.2942554094 |
| Directory | /workspace/16.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3009837799 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 287167897 ps |
| CPU time | 2.12 seconds |
| Started | Jan 24 12:57:31 PM PST 24 |
| Finished | Jan 24 12:57:56 PM PST 24 |
| Peak memory | 199672 kb |
| Host | smart-554fd196-0edc-4cd7-8ebc-49ebdb225de3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009837799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3009837799 |
| Directory | /workspace/16.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1536513621 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 474324523 ps |
| CPU time | 1.86 seconds |
| Started | Jan 24 12:57:38 PM PST 24 |
| Finished | Jan 24 12:58:03 PM PST 24 |
| Peak memory | 199720 kb |
| Host | smart-121ad5a9-3709-4dfb-97b3-f5c9ea8005c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536513621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er r.1536513621 |
| Directory | /workspace/16.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3527968712 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 131070069 ps |
| CPU time | 1.02 seconds |
| Started | Jan 24 12:57:36 PM PST 24 |
| Finished | Jan 24 12:58:00 PM PST 24 |
| Peak memory | 199480 kb |
| Host | smart-97083ba8-3455-46c0-8eb7-7a046a36a884 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527968712 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3527968712 |
| Directory | /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.235241567 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 82857231 ps |
| CPU time | 0.86 seconds |
| Started | Jan 24 12:57:33 PM PST 24 |
| Finished | Jan 24 12:57:57 PM PST 24 |
| Peak memory | 199488 kb |
| Host | smart-986fe2c6-72c3-45ce-aa8b-9d7a6723f943 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235241567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.235241567 |
| Directory | /workspace/17.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.337585645 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 239459030 ps |
| CPU time | 1.48 seconds |
| Started | Jan 24 12:57:31 PM PST 24 |
| Finished | Jan 24 12:57:55 PM PST 24 |
| Peak memory | 199688 kb |
| Host | smart-617e7ea0-ae2e-4402-a681-fdcdeb146315 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337585645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa me_csr_outstanding.337585645 |
| Directory | /workspace/17.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.398441151 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 443450613 ps |
| CPU time | 3.29 seconds |
| Started | Jan 24 12:57:32 PM PST 24 |
| Finished | Jan 24 12:57:58 PM PST 24 |
| Peak memory | 199760 kb |
| Host | smart-ef02a362-b70a-4fb4-92b4-e5b33971f551 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398441151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.398441151 |
| Directory | /workspace/17.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2044400686 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 506787311 ps |
| CPU time | 2 seconds |
| Started | Jan 24 12:57:40 PM PST 24 |
| Finished | Jan 24 12:58:06 PM PST 24 |
| Peak memory | 199556 kb |
| Host | smart-8dc5c8b3-db05-4e96-b301-5e5056a7c638 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044400686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er r.2044400686 |
| Directory | /workspace/17.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1657648848 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 106773869 ps |
| CPU time | 1.04 seconds |
| Started | Jan 24 12:57:36 PM PST 24 |
| Finished | Jan 24 12:58:00 PM PST 24 |
| Peak memory | 199168 kb |
| Host | smart-b9b60c1d-9a0b-41be-9cb3-7017aa28fae0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657648848 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1657648848 |
| Directory | /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3565938380 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 72200702 ps |
| CPU time | 0.83 seconds |
| Started | Jan 24 12:57:36 PM PST 24 |
| Finished | Jan 24 12:58:00 PM PST 24 |
| Peak memory | 199032 kb |
| Host | smart-3cc881c3-dbef-4f6f-be0e-85c0a8df9f2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565938380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3565938380 |
| Directory | /workspace/18.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.884514948 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 86529812 ps |
| CPU time | 0.98 seconds |
| Started | Jan 24 12:57:36 PM PST 24 |
| Finished | Jan 24 12:58:00 PM PST 24 |
| Peak memory | 199520 kb |
| Host | smart-a1b435ca-463f-44ee-85a5-d63ca4190e21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884514948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_sa me_csr_outstanding.884514948 |
| Directory | /workspace/18.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2890973574 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 210483715 ps |
| CPU time | 1.46 seconds |
| Started | Jan 24 12:57:36 PM PST 24 |
| Finished | Jan 24 12:58:00 PM PST 24 |
| Peak memory | 199700 kb |
| Host | smart-18ff6e4b-463a-42b5-b6de-30533ce3c1ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890973574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.2890973574 |
| Directory | /workspace/18.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.269129962 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 168617014 ps |
| CPU time | 1.66 seconds |
| Started | Jan 24 12:57:36 PM PST 24 |
| Finished | Jan 24 12:58:01 PM PST 24 |
| Peak memory | 207932 kb |
| Host | smart-26449a42-ddeb-4f77-9c85-f159d9186a88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269129962 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.269129962 |
| Directory | /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2297515904 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 74539272 ps |
| CPU time | 0.8 seconds |
| Started | Jan 24 12:57:35 PM PST 24 |
| Finished | Jan 24 12:57:59 PM PST 24 |
| Peak memory | 199428 kb |
| Host | smart-b820790c-1940-4c38-a0ce-6280bad34f0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297515904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2297515904 |
| Directory | /workspace/19.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.749094422 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 105999731 ps |
| CPU time | 1.27 seconds |
| Started | Jan 24 12:57:36 PM PST 24 |
| Finished | Jan 24 12:58:01 PM PST 24 |
| Peak memory | 199656 kb |
| Host | smart-207eb6b2-ff69-4552-bbf3-1c25748086d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749094422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sa me_csr_outstanding.749094422 |
| Directory | /workspace/19.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.203012764 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 220320405 ps |
| CPU time | 1.56 seconds |
| Started | Jan 24 12:57:36 PM PST 24 |
| Finished | Jan 24 12:58:01 PM PST 24 |
| Peak memory | 199756 kb |
| Host | smart-805e91c5-2fd0-4eda-ad7a-90a16d7ae365 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203012764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.203012764 |
| Directory | /workspace/19.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2916321205 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 212947169 ps |
| CPU time | 1.56 seconds |
| Started | Jan 24 12:56:48 PM PST 24 |
| Finished | Jan 24 12:57:16 PM PST 24 |
| Peak memory | 199696 kb |
| Host | smart-239cf3c9-6cd0-4c1f-a322-453582a54e5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916321205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.2 916321205 |
| Directory | /workspace/2.rstmgr_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1249172730 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 1171379578 ps |
| CPU time | 5.12 seconds |
| Started | Jan 24 12:56:38 PM PST 24 |
| Finished | Jan 24 12:57:13 PM PST 24 |
| Peak memory | 199808 kb |
| Host | smart-c488e248-60ef-45d7-90d7-2f07d8c78e7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249172730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.1 249172730 |
| Directory | /workspace/2.rstmgr_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2573497056 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 101316852 ps |
| CPU time | 0.8 seconds |
| Started | Jan 24 01:19:47 PM PST 24 |
| Finished | Jan 24 01:20:49 PM PST 24 |
| Peak memory | 199660 kb |
| Host | smart-9c5a8198-f86c-42b0-bdcf-e8454588d928 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573497056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2 573497056 |
| Directory | /workspace/2.rstmgr_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1535929825 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 144484613 ps |
| CPU time | 1.1 seconds |
| Started | Jan 24 01:02:02 PM PST 24 |
| Finished | Jan 24 01:02:09 PM PST 24 |
| Peak memory | 199548 kb |
| Host | smart-440f0e4e-19c1-4a1d-9285-c649aedb349f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535929825 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1535929825 |
| Directory | /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2270206169 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 93865986 ps |
| CPU time | 0.86 seconds |
| Started | Jan 24 12:56:40 PM PST 24 |
| Finished | Jan 24 12:57:09 PM PST 24 |
| Peak memory | 199488 kb |
| Host | smart-784f5383-43cf-44df-a308-0424116aa299 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270206169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.2270206169 |
| Directory | /workspace/2.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1421343471 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 146867056 ps |
| CPU time | 1.08 seconds |
| Started | Jan 24 12:56:39 PM PST 24 |
| Finished | Jan 24 12:57:09 PM PST 24 |
| Peak memory | 199620 kb |
| Host | smart-4da7d9c9-1cab-4f2b-bf80-a401b1efaf62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421343471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa me_csr_outstanding.1421343471 |
| Directory | /workspace/2.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1897645284 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 177908722 ps |
| CPU time | 2.6 seconds |
| Started | Jan 24 12:56:40 PM PST 24 |
| Finished | Jan 24 12:57:11 PM PST 24 |
| Peak memory | 199716 kb |
| Host | smart-556f8015-4e64-408e-b578-c612162fcb3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897645284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.1897645284 |
| Directory | /workspace/2.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3356666201 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 492876703 ps |
| CPU time | 1.91 seconds |
| Started | Jan 24 12:56:38 PM PST 24 |
| Finished | Jan 24 12:57:09 PM PST 24 |
| Peak memory | 199736 kb |
| Host | smart-c93a35b5-84b8-453e-b563-197444e6a4e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356666201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err .3356666201 |
| Directory | /workspace/2.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.963147481 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 205990413 ps |
| CPU time | 1.5 seconds |
| Started | Jan 24 12:56:49 PM PST 24 |
| Finished | Jan 24 12:57:18 PM PST 24 |
| Peak memory | 199616 kb |
| Host | smart-4d17c098-cbee-4d9b-b158-1f1ce5c764be |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963147481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.963147481 |
| Directory | /workspace/3.rstmgr_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3346495994 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 1180992648 ps |
| CPU time | 5.62 seconds |
| Started | Jan 24 12:56:48 PM PST 24 |
| Finished | Jan 24 12:57:21 PM PST 24 |
| Peak memory | 199740 kb |
| Host | smart-7204b94b-7420-4c0e-b900-100808c058bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346495994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.3 346495994 |
| Directory | /workspace/3.rstmgr_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.4023401265 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 120105428 ps |
| CPU time | 0.84 seconds |
| Started | Jan 24 12:56:54 PM PST 24 |
| Finished | Jan 24 12:57:21 PM PST 24 |
| Peak memory | 199620 kb |
| Host | smart-2dfee542-2fee-4021-84d1-a73d969cb8d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023401265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.4 023401265 |
| Directory | /workspace/3.rstmgr_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.772144932 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 133707416 ps |
| CPU time | 1.42 seconds |
| Started | Jan 24 12:56:50 PM PST 24 |
| Finished | Jan 24 12:57:18 PM PST 24 |
| Peak memory | 207880 kb |
| Host | smart-6dc790f0-6f32-4e5d-a05f-fda659de6885 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772144932 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.772144932 |
| Directory | /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.4248314008 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 76700287 ps |
| CPU time | 0.75 seconds |
| Started | Jan 24 12:56:47 PM PST 24 |
| Finished | Jan 24 12:57:15 PM PST 24 |
| Peak memory | 199548 kb |
| Host | smart-c6003609-9d28-4401-8bf3-43bec0162e0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248314008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.4248314008 |
| Directory | /workspace/3.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3549187718 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 132371966 ps |
| CPU time | 1.03 seconds |
| Started | Jan 24 12:56:48 PM PST 24 |
| Finished | Jan 24 12:57:16 PM PST 24 |
| Peak memory | 199436 kb |
| Host | smart-5b822438-94c0-4c15-8839-c41dfa19de51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549187718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa me_csr_outstanding.3549187718 |
| Directory | /workspace/3.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3281065902 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 128115850 ps |
| CPU time | 1.82 seconds |
| Started | Jan 24 12:56:36 PM PST 24 |
| Finished | Jan 24 12:57:08 PM PST 24 |
| Peak memory | 199808 kb |
| Host | smart-d7da383a-3974-4f18-a87b-01854bcdfed4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281065902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.3281065902 |
| Directory | /workspace/3.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.913437251 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 465816591 ps |
| CPU time | 1.83 seconds |
| Started | Jan 24 12:56:48 PM PST 24 |
| Finished | Jan 24 12:57:17 PM PST 24 |
| Peak memory | 199708 kb |
| Host | smart-6d371e3d-89cf-44fa-83c8-b90cab115846 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913437251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err. 913437251 |
| Directory | /workspace/3.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1535955955 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 102115303 ps |
| CPU time | 1.29 seconds |
| Started | Jan 24 12:56:49 PM PST 24 |
| Finished | Jan 24 12:57:17 PM PST 24 |
| Peak memory | 199720 kb |
| Host | smart-b5b6df67-8545-4628-9ae8-4704431170fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535955955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.1 535955955 |
| Directory | /workspace/4.rstmgr_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.631444153 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 488917730 ps |
| CPU time | 5.52 seconds |
| Started | Jan 24 12:56:46 PM PST 24 |
| Finished | Jan 24 12:57:19 PM PST 24 |
| Peak memory | 199552 kb |
| Host | smart-9a743fd1-8358-4af2-811d-533750f0db78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631444153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.631444153 |
| Directory | /workspace/4.rstmgr_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.282002659 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 137749349 ps |
| CPU time | 0.93 seconds |
| Started | Jan 24 12:56:46 PM PST 24 |
| Finished | Jan 24 12:57:14 PM PST 24 |
| Peak memory | 197748 kb |
| Host | smart-765583de-120a-42ed-a86b-a0a4c980c851 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282002659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.282002659 |
| Directory | /workspace/4.rstmgr_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2384778418 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 137373245 ps |
| CPU time | 1.22 seconds |
| Started | Jan 24 12:56:49 PM PST 24 |
| Finished | Jan 24 12:57:17 PM PST 24 |
| Peak memory | 199536 kb |
| Host | smart-bba1fdda-70d2-4d16-b488-ce15cf50f54e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384778418 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2384778418 |
| Directory | /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1989616427 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 57746426 ps |
| CPU time | 0.73 seconds |
| Started | Jan 24 12:56:49 PM PST 24 |
| Finished | Jan 24 12:57:17 PM PST 24 |
| Peak memory | 199488 kb |
| Host | smart-d08c9a65-6fd0-437d-a4b1-4014eb886720 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989616427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1989616427 |
| Directory | /workspace/4.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1224388332 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 102656097 ps |
| CPU time | 1.13 seconds |
| Started | Jan 24 12:56:46 PM PST 24 |
| Finished | Jan 24 12:57:15 PM PST 24 |
| Peak memory | 197852 kb |
| Host | smart-c65d2a1c-fc05-441e-a704-4f681b025f56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224388332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa me_csr_outstanding.1224388332 |
| Directory | /workspace/4.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3530187230 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 441411321 ps |
| CPU time | 3.2 seconds |
| Started | Jan 24 12:56:49 PM PST 24 |
| Finished | Jan 24 12:57:19 PM PST 24 |
| Peak memory | 207936 kb |
| Host | smart-24a87898-1f20-48c2-8a79-e441947a5b70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530187230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3530187230 |
| Directory | /workspace/4.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1173064190 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 425608219 ps |
| CPU time | 1.77 seconds |
| Started | Jan 24 12:56:46 PM PST 24 |
| Finished | Jan 24 12:57:15 PM PST 24 |
| Peak memory | 199588 kb |
| Host | smart-501e4b36-3822-4d57-93ca-1bf3f8e2ece8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173064190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err .1173064190 |
| Directory | /workspace/4.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1287112407 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 176939018 ps |
| CPU time | 1.24 seconds |
| Started | Jan 24 12:56:55 PM PST 24 |
| Finished | Jan 24 12:57:23 PM PST 24 |
| Peak memory | 199660 kb |
| Host | smart-1b7a36f0-a310-4a04-abcd-85ae8a89fe96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287112407 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.1287112407 |
| Directory | /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.983686856 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 68995477 ps |
| CPU time | 0.75 seconds |
| Started | Jan 24 01:19:03 PM PST 24 |
| Finished | Jan 24 01:20:04 PM PST 24 |
| Peak memory | 199672 kb |
| Host | smart-f00483a1-947e-4229-a475-2426c89ce22e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983686856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.983686856 |
| Directory | /workspace/5.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1680548033 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 129658818 ps |
| CPU time | 1.02 seconds |
| Started | Jan 24 12:56:56 PM PST 24 |
| Finished | Jan 24 12:57:23 PM PST 24 |
| Peak memory | 199512 kb |
| Host | smart-4d317d2a-9bf3-4d5d-87f6-725d150581bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680548033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa me_csr_outstanding.1680548033 |
| Directory | /workspace/5.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1617350742 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 186776124 ps |
| CPU time | 2.71 seconds |
| Started | Jan 24 12:56:54 PM PST 24 |
| Finished | Jan 24 12:57:23 PM PST 24 |
| Peak memory | 199804 kb |
| Host | smart-f88b9d42-613d-48d3-9cc2-5f1efad0161a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617350742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1617350742 |
| Directory | /workspace/5.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.501686847 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 126617318 ps |
| CPU time | 0.99 seconds |
| Started | Jan 24 12:56:58 PM PST 24 |
| Finished | Jan 24 12:57:24 PM PST 24 |
| Peak memory | 199544 kb |
| Host | smart-13268b1d-20d5-44ee-8ad3-9a51ef831e3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501686847 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.501686847 |
| Directory | /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3993593166 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 75407319 ps |
| CPU time | 0.8 seconds |
| Started | Jan 24 12:56:58 PM PST 24 |
| Finished | Jan 24 12:57:25 PM PST 24 |
| Peak memory | 199556 kb |
| Host | smart-938eae6a-38d8-4ad2-b4df-efb8babe6dc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993593166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.3993593166 |
| Directory | /workspace/6.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2181368384 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 223121859 ps |
| CPU time | 1.47 seconds |
| Started | Jan 24 12:56:53 PM PST 24 |
| Finished | Jan 24 12:57:21 PM PST 24 |
| Peak memory | 199748 kb |
| Host | smart-c843a8c3-7b58-4535-b25d-471b293e2eb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181368384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa me_csr_outstanding.2181368384 |
| Directory | /workspace/6.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1410229071 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 480742968 ps |
| CPU time | 3.43 seconds |
| Started | Jan 24 01:10:22 PM PST 24 |
| Finished | Jan 24 01:11:05 PM PST 24 |
| Peak memory | 199848 kb |
| Host | smart-6b4d66eb-ea21-412c-9f46-f558d8821cde |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410229071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.1410229071 |
| Directory | /workspace/6.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.4224073567 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 773540126 ps |
| CPU time | 2.9 seconds |
| Started | Jan 24 01:11:18 PM PST 24 |
| Finished | Jan 24 01:11:55 PM PST 24 |
| Peak memory | 199804 kb |
| Host | smart-cd72d3dc-97dd-405b-bb6a-6a2d5e664c0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224073567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err .4224073567 |
| Directory | /workspace/6.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3961348662 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 124412835 ps |
| CPU time | 1.27 seconds |
| Started | Jan 24 01:15:16 PM PST 24 |
| Finished | Jan 24 01:15:58 PM PST 24 |
| Peak memory | 207864 kb |
| Host | smart-3500d3ba-5411-460e-bef0-292cd7566a1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961348662 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.3961348662 |
| Directory | /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2684329851 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 70111053 ps |
| CPU time | 0.75 seconds |
| Started | Jan 24 02:24:03 PM PST 24 |
| Finished | Jan 24 02:24:16 PM PST 24 |
| Peak memory | 199624 kb |
| Host | smart-bf418b43-a7e9-4708-8e1a-e70e64c36d63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684329851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2684329851 |
| Directory | /workspace/7.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2879513003 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 80064436 ps |
| CPU time | 0.91 seconds |
| Started | Jan 24 12:56:54 PM PST 24 |
| Finished | Jan 24 12:57:22 PM PST 24 |
| Peak memory | 199476 kb |
| Host | smart-6d5a814f-0ade-4f08-80d3-ba8ccceb80a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879513003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa me_csr_outstanding.2879513003 |
| Directory | /workspace/7.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2041824332 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 227243466 ps |
| CPU time | 1.74 seconds |
| Started | Jan 24 01:12:35 PM PST 24 |
| Finished | Jan 24 01:13:30 PM PST 24 |
| Peak memory | 199880 kb |
| Host | smart-75d135be-3af6-408a-8672-a3769f5971ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041824332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2041824332 |
| Directory | /workspace/7.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2586780361 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 779653967 ps |
| CPU time | 2.7 seconds |
| Started | Jan 24 01:10:29 PM PST 24 |
| Finished | Jan 24 01:11:12 PM PST 24 |
| Peak memory | 199772 kb |
| Host | smart-a18d893a-5ff0-46c8-8bc0-43ce09bd0e17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586780361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err .2586780361 |
| Directory | /workspace/7.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.4165281179 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 111234822 ps |
| CPU time | 1.2 seconds |
| Started | Jan 24 12:57:09 PM PST 24 |
| Finished | Jan 24 12:57:34 PM PST 24 |
| Peak memory | 199592 kb |
| Host | smart-d818df85-df79-4ced-9ff4-9f43d7ed413a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165281179 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.4165281179 |
| Directory | /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1558021482 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 73081854 ps |
| CPU time | 0.81 seconds |
| Started | Jan 24 12:56:54 PM PST 24 |
| Finished | Jan 24 12:57:22 PM PST 24 |
| Peak memory | 199556 kb |
| Host | smart-d2277f0b-f450-43a4-8dbd-84c7ba7f1bd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558021482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1558021482 |
| Directory | /workspace/8.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2567661464 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 136454705 ps |
| CPU time | 1.35 seconds |
| Started | Jan 24 12:56:53 PM PST 24 |
| Finished | Jan 24 12:57:21 PM PST 24 |
| Peak memory | 199684 kb |
| Host | smart-d115d600-0773-4136-9cd3-c9b3d496ed4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567661464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa me_csr_outstanding.2567661464 |
| Directory | /workspace/8.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.4091056046 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 105649745 ps |
| CPU time | 1.38 seconds |
| Started | Jan 24 12:56:53 PM PST 24 |
| Finished | Jan 24 12:57:20 PM PST 24 |
| Peak memory | 199632 kb |
| Host | smart-91ca592a-915b-4e4f-9407-b6724a66f26b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091056046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.4091056046 |
| Directory | /workspace/8.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3659693138 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 918160726 ps |
| CPU time | 2.95 seconds |
| Started | Jan 24 01:03:38 PM PST 24 |
| Finished | Jan 24 01:04:15 PM PST 24 |
| Peak memory | 199696 kb |
| Host | smart-bf008943-4251-443b-baed-426829189f98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659693138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err .3659693138 |
| Directory | /workspace/8.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.139527311 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 153733660 ps |
| CPU time | 1.59 seconds |
| Started | Jan 24 12:57:06 PM PST 24 |
| Finished | Jan 24 12:57:31 PM PST 24 |
| Peak memory | 207824 kb |
| Host | smart-90877cb0-83cb-4c62-9dfa-696f97cdef2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139527311 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.139527311 |
| Directory | /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1934941993 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 63522297 ps |
| CPU time | 0.78 seconds |
| Started | Jan 24 12:57:07 PM PST 24 |
| Finished | Jan 24 12:57:31 PM PST 24 |
| Peak memory | 199432 kb |
| Host | smart-57c1615c-3e4e-40b7-a757-9758024611f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934941993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1934941993 |
| Directory | /workspace/9.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2624757601 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 159204977 ps |
| CPU time | 1.12 seconds |
| Started | Jan 24 12:57:13 PM PST 24 |
| Finished | Jan 24 12:57:39 PM PST 24 |
| Peak memory | 199468 kb |
| Host | smart-81866f74-b467-4966-9551-d7ce9b86ee27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624757601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa me_csr_outstanding.2624757601 |
| Directory | /workspace/9.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2583255522 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 527538905 ps |
| CPU time | 3.43 seconds |
| Started | Jan 24 12:57:02 PM PST 24 |
| Finished | Jan 24 12:57:30 PM PST 24 |
| Peak memory | 199672 kb |
| Host | smart-402d688e-9470-4f3e-9a28-b4c23e400e2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583255522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2583255522 |
| Directory | /workspace/9.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.138172704 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 878627122 ps |
| CPU time | 3.22 seconds |
| Started | Jan 24 12:57:10 PM PST 24 |
| Finished | Jan 24 12:57:37 PM PST 24 |
| Peak memory | 199700 kb |
| Host | smart-f853a36c-1c5e-4fce-8d36-3bacfbbe1750 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138172704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err. 138172704 |
| Directory | /workspace/9.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.rstmgr_alert_test.1783039095 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 68159889 ps |
| CPU time | 0.72 seconds |
| Started | Jan 24 01:22:12 PM PST 24 |
| Finished | Jan 24 01:23:11 PM PST 24 |
| Peak memory | 199268 kb |
| Host | smart-1a24b68d-e97c-41bf-ad09-6854c4253970 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783039095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.1783039095 |
| Directory | /workspace/0.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.3203666494 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 1216459626 ps |
| CPU time | 5.39 seconds |
| Started | Jan 24 01:04:03 PM PST 24 |
| Finished | Jan 24 01:04:52 PM PST 24 |
| Peak memory | 217448 kb |
| Host | smart-256df449-ffac-4cc6-b89d-91bc8ef627c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3203666494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.3203666494 |
| Directory | /workspace/0.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.607965052 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 243697356 ps |
| CPU time | 1.07 seconds |
| Started | Jan 24 01:08:09 PM PST 24 |
| Finished | Jan 24 01:08:50 PM PST 24 |
| Peak memory | 216928 kb |
| Host | smart-58889248-4597-430a-8b3f-d5a24dc24d19 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=607965052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.607965052 |
| Directory | /workspace/0.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/0.rstmgr_por_stretcher.2486775404 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 124125036 ps |
| CPU time | 0.8 seconds |
| Started | Jan 24 01:32:15 PM PST 24 |
| Finished | Jan 24 01:32:58 PM PST 24 |
| Peak memory | 199400 kb |
| Host | smart-c7716050-b9e8-4861-af39-7c924e683204 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2486775404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.2486775404 |
| Directory | /workspace/0.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/0.rstmgr_reset.2959855853 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 1495909415 ps |
| CPU time | 5.75 seconds |
| Started | Jan 24 01:08:12 PM PST 24 |
| Finished | Jan 24 01:08:56 PM PST 24 |
| Peak memory | 199856 kb |
| Host | smart-cfb2f5c2-c33e-4f6e-a6cd-67dd37952e71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2959855853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.2959855853 |
| Directory | /workspace/0.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/0.rstmgr_sec_cm.1434988571 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 17053453797 ps |
| CPU time | 25.67 seconds |
| Started | Jan 24 01:04:02 PM PST 24 |
| Finished | Jan 24 01:05:12 PM PST 24 |
| Peak memory | 217596 kb |
| Host | smart-cab2befe-c7d8-4e02-81cf-7f33d657433e |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434988571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.1434988571 |
| Directory | /workspace/0.rstmgr_sec_cm/latest |
| Test location | /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2852497924 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 104496161 ps |
| CPU time | 0.95 seconds |
| Started | Jan 24 01:19:06 PM PST 24 |
| Finished | Jan 24 01:20:08 PM PST 24 |
| Peak memory | 199532 kb |
| Host | smart-6f8e55da-fe8f-49fa-b4b9-c115c927aac5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2852497924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2852497924 |
| Directory | /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/0.rstmgr_smoke.710358539 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 116782147 ps |
| CPU time | 1.14 seconds |
| Started | Jan 24 01:03:52 PM PST 24 |
| Finished | Jan 24 01:04:35 PM PST 24 |
| Peak memory | 199712 kb |
| Host | smart-6e3d1082-004d-406f-b939-019aabdcbc05 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=710358539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.710358539 |
| Directory | /workspace/0.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/0.rstmgr_stress_all.994495287 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 2365059078 ps |
| CPU time | 7.87 seconds |
| Started | Jan 24 01:15:22 PM PST 24 |
| Finished | Jan 24 01:16:14 PM PST 24 |
| Peak memory | 199860 kb |
| Host | smart-668f4376-26d5-4e93-9ba0-2fa5803f947e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994495287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.994495287 |
| Directory | /workspace/0.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/0.rstmgr_sw_rst.1354510607 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 265910804 ps |
| CPU time | 1.7 seconds |
| Started | Jan 24 01:04:03 PM PST 24 |
| Finished | Jan 24 01:04:48 PM PST 24 |
| Peak memory | 199540 kb |
| Host | smart-da0dadf2-5255-4d31-9c7e-9322548ada52 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1354510607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1354510607 |
| Directory | /workspace/0.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.2871528430 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 129956903 ps |
| CPU time | 0.96 seconds |
| Started | Jan 24 01:04:01 PM PST 24 |
| Finished | Jan 24 01:04:45 PM PST 24 |
| Peak memory | 199468 kb |
| Host | smart-75911d01-18ab-42c2-a000-ab7c36fba373 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2871528430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.2871528430 |
| Directory | /workspace/0.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/1.rstmgr_alert_test.241503308 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 95246456 ps |
| CPU time | 0.8 seconds |
| Started | Jan 24 01:04:13 PM PST 24 |
| Finished | Jan 24 01:04:58 PM PST 24 |
| Peak memory | 199488 kb |
| Host | smart-6fb3b1cb-87d6-4364-96f9-35bcbab6d646 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241503308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.241503308 |
| Directory | /workspace/1.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3571313308 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 2346510977 ps |
| CPU time | 8.09 seconds |
| Started | Jan 24 01:04:09 PM PST 24 |
| Finished | Jan 24 01:05:01 PM PST 24 |
| Peak memory | 217368 kb |
| Host | smart-0fd8ae89-d09d-46f5-8a53-eff1c97a132f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3571313308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3571313308 |
| Directory | /workspace/1.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2597912734 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 244694106 ps |
| CPU time | 1.12 seconds |
| Started | Jan 24 01:04:14 PM PST 24 |
| Finished | Jan 24 01:04:59 PM PST 24 |
| Peak memory | 216832 kb |
| Host | smart-655d3bc0-4fe6-4fd9-95b7-2d78d831c15f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2597912734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2597912734 |
| Directory | /workspace/1.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/1.rstmgr_por_stretcher.236189136 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 200955810 ps |
| CPU time | 0.9 seconds |
| Started | Jan 24 01:04:16 PM PST 24 |
| Finished | Jan 24 01:05:01 PM PST 24 |
| Peak memory | 199368 kb |
| Host | smart-6cfa74e1-d066-489c-af70-3442eac78b7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=236189136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.236189136 |
| Directory | /workspace/1.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/1.rstmgr_reset.150678691 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 1184504492 ps |
| CPU time | 4.79 seconds |
| Started | Jan 24 01:04:14 PM PST 24 |
| Finished | Jan 24 01:05:03 PM PST 24 |
| Peak memory | 199572 kb |
| Host | smart-294b947e-6d78-4bc2-a8dc-f405594483ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=150678691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.150678691 |
| Directory | /workspace/1.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1012748839 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 177065032 ps |
| CPU time | 1.16 seconds |
| Started | Jan 24 01:04:08 PM PST 24 |
| Finished | Jan 24 01:04:53 PM PST 24 |
| Peak memory | 199496 kb |
| Host | smart-52311fe1-b9cf-4618-9209-2281a34ed504 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1012748839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1012748839 |
| Directory | /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/1.rstmgr_smoke.1111811764 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 110362433 ps |
| CPU time | 1.13 seconds |
| Started | Jan 24 01:04:02 PM PST 24 |
| Finished | Jan 24 01:04:47 PM PST 24 |
| Peak memory | 199668 kb |
| Host | smart-36d699dd-93d1-43e9-96e7-e9325932782e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1111811764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1111811764 |
| Directory | /workspace/1.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/1.rstmgr_stress_all.3185166558 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 219065214 ps |
| CPU time | 1.26 seconds |
| Started | Jan 24 01:04:07 PM PST 24 |
| Finished | Jan 24 01:04:53 PM PST 24 |
| Peak memory | 199380 kb |
| Host | smart-26d5cc7f-9a86-47a1-8916-592dce0cdf77 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185166558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3185166558 |
| Directory | /workspace/1.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/1.rstmgr_sw_rst.1291566959 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 317405554 ps |
| CPU time | 2.14 seconds |
| Started | Jan 24 01:04:09 PM PST 24 |
| Finished | Jan 24 01:04:56 PM PST 24 |
| Peak memory | 199564 kb |
| Host | smart-36f967e6-25a5-4a7d-a426-1976da41a85f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1291566959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.1291566959 |
| Directory | /workspace/1.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3989934487 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 179528927 ps |
| CPU time | 1.12 seconds |
| Started | Jan 24 01:04:13 PM PST 24 |
| Finished | Jan 24 01:04:59 PM PST 24 |
| Peak memory | 199380 kb |
| Host | smart-23d673a8-4941-4391-bcd0-fe088125ae5d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3989934487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3989934487 |
| Directory | /workspace/1.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/10.rstmgr_alert_test.3583372924 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 73947507 ps |
| CPU time | 0.78 seconds |
| Started | Jan 24 01:05:13 PM PST 24 |
| Finished | Jan 24 01:06:02 PM PST 24 |
| Peak memory | 199500 kb |
| Host | smart-6ca09803-13ed-413d-88e7-ca8ddd680394 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583372924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3583372924 |
| Directory | /workspace/10.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.508227948 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1227075472 ps |
| CPU time | 5.48 seconds |
| Started | Jan 24 01:05:10 PM PST 24 |
| Finished | Jan 24 01:06:04 PM PST 24 |
| Peak memory | 221556 kb |
| Host | smart-dc63ffb2-9d13-43fd-8cb2-7655b2dccde9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=508227948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.508227948 |
| Directory | /workspace/10.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.3992852562 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 243985996 ps |
| CPU time | 1.11 seconds |
| Started | Jan 24 01:05:07 PM PST 24 |
| Finished | Jan 24 01:05:55 PM PST 24 |
| Peak memory | 216176 kb |
| Host | smart-62d58f84-74e9-4fbe-82c0-15efb9326835 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3992852562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.3992852562 |
| Directory | /workspace/10.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/10.rstmgr_por_stretcher.3856747348 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 128863834 ps |
| CPU time | 0.8 seconds |
| Started | Jan 24 01:05:10 PM PST 24 |
| Finished | Jan 24 01:05:58 PM PST 24 |
| Peak memory | 199364 kb |
| Host | smart-4d6ade9b-697f-4a19-af1b-d6c61c4a0f1d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3856747348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.3856747348 |
| Directory | /workspace/10.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/10.rstmgr_smoke.3033833504 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 247899621 ps |
| CPU time | 1.44 seconds |
| Started | Jan 24 01:05:07 PM PST 24 |
| Finished | Jan 24 01:05:55 PM PST 24 |
| Peak memory | 198976 kb |
| Host | smart-5d78a920-6a6c-41f1-89dd-4edcb9460664 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3033833504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.3033833504 |
| Directory | /workspace/10.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/10.rstmgr_stress_all.1999036507 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 3431140415 ps |
| CPU time | 17.58 seconds |
| Started | Jan 24 01:05:09 PM PST 24 |
| Finished | Jan 24 01:06:13 PM PST 24 |
| Peak memory | 199836 kb |
| Host | smart-0157721d-5245-4d45-bb59-efe4fbf1d4df |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999036507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1999036507 |
| Directory | /workspace/10.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/10.rstmgr_sw_rst.3595184685 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 119777215 ps |
| CPU time | 1.46 seconds |
| Started | Jan 24 01:05:09 PM PST 24 |
| Finished | Jan 24 01:05:57 PM PST 24 |
| Peak memory | 199620 kb |
| Host | smart-1a96c3f9-7b4d-4ede-b6ea-d051194e4b44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3595184685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3595184685 |
| Directory | /workspace/10.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.2664258086 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 115370142 ps |
| CPU time | 0.93 seconds |
| Started | Jan 24 01:05:09 PM PST 24 |
| Finished | Jan 24 01:05:57 PM PST 24 |
| Peak memory | 199564 kb |
| Host | smart-cddc86d7-c484-4902-be5a-20126fad8549 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2664258086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2664258086 |
| Directory | /workspace/10.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/11.rstmgr_alert_test.2060640040 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 69158762 ps |
| CPU time | 0.75 seconds |
| Started | Jan 24 01:05:08 PM PST 24 |
| Finished | Jan 24 01:05:56 PM PST 24 |
| Peak memory | 199500 kb |
| Host | smart-1acb2972-d860-4856-80d9-ea9bd3ef6991 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060640040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.2060640040 |
| Directory | /workspace/11.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.970838792 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 1898455659 ps |
| CPU time | 7.86 seconds |
| Started | Jan 24 01:05:14 PM PST 24 |
| Finished | Jan 24 01:06:10 PM PST 24 |
| Peak memory | 217848 kb |
| Host | smart-b4308c33-ae8d-4bbb-8207-b1485a7fda22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=970838792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.970838792 |
| Directory | /workspace/11.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.4221767375 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 244452507 ps |
| CPU time | 1.1 seconds |
| Started | Jan 24 01:05:07 PM PST 24 |
| Finished | Jan 24 01:05:55 PM PST 24 |
| Peak memory | 216876 kb |
| Host | smart-35d450ba-ece0-462c-b62d-f6a612228998 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4221767375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.4221767375 |
| Directory | /workspace/11.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/11.rstmgr_por_stretcher.4095188710 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 182575856 ps |
| CPU time | 0.8 seconds |
| Started | Jan 24 01:05:06 PM PST 24 |
| Finished | Jan 24 01:05:51 PM PST 24 |
| Peak memory | 199260 kb |
| Host | smart-4f328c2c-e011-4e1d-ae36-6708064799c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4095188710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.4095188710 |
| Directory | /workspace/11.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/11.rstmgr_reset.316326648 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 847462345 ps |
| CPU time | 4.21 seconds |
| Started | Jan 24 01:05:06 PM PST 24 |
| Finished | Jan 24 01:05:55 PM PST 24 |
| Peak memory | 199768 kb |
| Host | smart-117ecd37-d4f9-4489-8210-15caf1bbeebb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=316326648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.316326648 |
| Directory | /workspace/11.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.2407687901 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 182775519 ps |
| CPU time | 1.15 seconds |
| Started | Jan 24 01:05:13 PM PST 24 |
| Finished | Jan 24 01:06:02 PM PST 24 |
| Peak memory | 199524 kb |
| Host | smart-0f4b97d9-be50-47e3-a580-84b001d2e2fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2407687901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.2407687901 |
| Directory | /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/11.rstmgr_smoke.2020714613 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 116029996 ps |
| CPU time | 1.21 seconds |
| Started | Jan 24 01:05:14 PM PST 24 |
| Finished | Jan 24 01:06:03 PM PST 24 |
| Peak memory | 199600 kb |
| Host | smart-49e8b853-79ae-412d-b9cb-2d7e35266584 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2020714613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.2020714613 |
| Directory | /workspace/11.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/11.rstmgr_stress_all.3849408162 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 3067099856 ps |
| CPU time | 15.51 seconds |
| Started | Jan 24 01:05:14 PM PST 24 |
| Finished | Jan 24 01:06:18 PM PST 24 |
| Peak memory | 199724 kb |
| Host | smart-f4912767-7bbc-4a04-8c50-17416253fffc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849408162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3849408162 |
| Directory | /workspace/11.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/11.rstmgr_sw_rst.21207778 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 336660867 ps |
| CPU time | 2.17 seconds |
| Started | Jan 24 01:05:07 PM PST 24 |
| Finished | Jan 24 01:05:56 PM PST 24 |
| Peak memory | 199496 kb |
| Host | smart-186a0cef-bdc9-410a-be92-bba0a90d077a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=21207778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.21207778 |
| Directory | /workspace/11.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.925827386 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 62232698 ps |
| CPU time | 0.76 seconds |
| Started | Jan 24 01:05:08 PM PST 24 |
| Finished | Jan 24 01:05:56 PM PST 24 |
| Peak memory | 199572 kb |
| Host | smart-050f7859-da47-409e-881b-b23dd3df80e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=925827386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.925827386 |
| Directory | /workspace/11.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/12.rstmgr_alert_test.3111487028 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 86159144 ps |
| CPU time | 0.78 seconds |
| Started | Jan 24 01:05:24 PM PST 24 |
| Finished | Jan 24 01:06:15 PM PST 24 |
| Peak memory | 199500 kb |
| Host | smart-b9079d68-3875-46c7-8630-a22c1a47cf72 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111487028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3111487028 |
| Directory | /workspace/12.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.1069217188 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 2361750910 ps |
| CPU time | 7.57 seconds |
| Started | Jan 24 01:05:30 PM PST 24 |
| Finished | Jan 24 01:06:29 PM PST 24 |
| Peak memory | 218368 kb |
| Host | smart-15f691d8-d249-4359-8743-889820b9f801 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1069217188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.1069217188 |
| Directory | /workspace/12.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3493122699 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 244987916 ps |
| CPU time | 1.12 seconds |
| Started | Jan 24 01:05:27 PM PST 24 |
| Finished | Jan 24 01:06:18 PM PST 24 |
| Peak memory | 216720 kb |
| Host | smart-18202c80-ebc7-40cb-8b80-02b14ae02342 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3493122699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3493122699 |
| Directory | /workspace/12.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/12.rstmgr_reset.1622944153 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1406884508 ps |
| CPU time | 5.37 seconds |
| Started | Jan 24 01:05:24 PM PST 24 |
| Finished | Jan 24 01:06:19 PM PST 24 |
| Peak memory | 199796 kb |
| Host | smart-0cf59d6a-5127-437a-958f-31c556e016dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1622944153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.1622944153 |
| Directory | /workspace/12.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.985617867 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 173741254 ps |
| CPU time | 1.13 seconds |
| Started | Jan 24 01:05:31 PM PST 24 |
| Finished | Jan 24 01:06:23 PM PST 24 |
| Peak memory | 199524 kb |
| Host | smart-a50466e6-635d-4d13-96f0-a971e0e2d26d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=985617867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.985617867 |
| Directory | /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/12.rstmgr_smoke.3727763334 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 225450604 ps |
| CPU time | 1.48 seconds |
| Started | Jan 24 01:05:14 PM PST 24 |
| Finished | Jan 24 01:06:04 PM PST 24 |
| Peak memory | 199664 kb |
| Host | smart-eb4ae056-3b59-4241-a5cb-5fff7628cd68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3727763334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3727763334 |
| Directory | /workspace/12.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/12.rstmgr_stress_all.638630634 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 4143236416 ps |
| CPU time | 16.41 seconds |
| Started | Jan 24 01:05:29 PM PST 24 |
| Finished | Jan 24 01:06:37 PM PST 24 |
| Peak memory | 199860 kb |
| Host | smart-4261a486-bb41-403a-91f2-d3d1aa031349 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638630634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.638630634 |
| Directory | /workspace/12.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/12.rstmgr_sw_rst.135654020 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 406410411 ps |
| CPU time | 2.32 seconds |
| Started | Jan 24 01:05:20 PM PST 24 |
| Finished | Jan 24 01:06:11 PM PST 24 |
| Peak memory | 199464 kb |
| Host | smart-36fce485-10ca-4e53-a9c4-7962bcaa3ec6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=135654020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.135654020 |
| Directory | /workspace/12.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/13.rstmgr_alert_test.2196447078 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 84362576 ps |
| CPU time | 0.81 seconds |
| Started | Jan 24 01:22:42 PM PST 24 |
| Finished | Jan 24 01:23:39 PM PST 24 |
| Peak memory | 199520 kb |
| Host | smart-f71f921d-0f60-487c-ac12-d5c0eb11d716 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196447078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2196447078 |
| Directory | /workspace/13.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3313411877 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 1230423825 ps |
| CPU time | 5.47 seconds |
| Started | Jan 24 01:05:28 PM PST 24 |
| Finished | Jan 24 01:06:24 PM PST 24 |
| Peak memory | 216484 kb |
| Host | smart-41837750-6345-4224-b698-c09662c72137 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3313411877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3313411877 |
| Directory | /workspace/13.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.823004009 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 244248062 ps |
| CPU time | 1.03 seconds |
| Started | Jan 24 01:05:28 PM PST 24 |
| Finished | Jan 24 01:06:20 PM PST 24 |
| Peak memory | 216808 kb |
| Host | smart-8d18e2bf-3fd9-454c-b36a-65f4b226ea92 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=823004009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.823004009 |
| Directory | /workspace/13.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/13.rstmgr_por_stretcher.1622528375 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 175864713 ps |
| CPU time | 0.85 seconds |
| Started | Jan 24 01:05:29 PM PST 24 |
| Finished | Jan 24 01:06:21 PM PST 24 |
| Peak memory | 199388 kb |
| Host | smart-580120be-8419-48d9-8c84-03adcf1dec62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1622528375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1622528375 |
| Directory | /workspace/13.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/13.rstmgr_reset.1965608027 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 1729163819 ps |
| CPU time | 6.06 seconds |
| Started | Jan 24 01:05:31 PM PST 24 |
| Finished | Jan 24 01:06:27 PM PST 24 |
| Peak memory | 199720 kb |
| Host | smart-54c6def2-72cf-4193-a609-2bfb8eed2b57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1965608027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.1965608027 |
| Directory | /workspace/13.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.4182574217 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 154496047 ps |
| CPU time | 1.05 seconds |
| Started | Jan 24 01:05:24 PM PST 24 |
| Finished | Jan 24 01:06:16 PM PST 24 |
| Peak memory | 199584 kb |
| Host | smart-842de3c5-bcf8-4d4d-a186-e5fe1c98b318 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4182574217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.4182574217 |
| Directory | /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/13.rstmgr_smoke.3130401040 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 251484629 ps |
| CPU time | 1.53 seconds |
| Started | Jan 24 01:05:19 PM PST 24 |
| Finished | Jan 24 01:06:10 PM PST 24 |
| Peak memory | 199788 kb |
| Host | smart-46b2e31f-713c-499f-a907-f97f627768fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3130401040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3130401040 |
| Directory | /workspace/13.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/13.rstmgr_stress_all.4261365599 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 5003774475 ps |
| CPU time | 20.77 seconds |
| Started | Jan 24 01:05:21 PM PST 24 |
| Finished | Jan 24 01:06:31 PM PST 24 |
| Peak memory | 199892 kb |
| Host | smart-13ca8c6c-addb-4939-90df-5ce2f21ac772 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261365599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.4261365599 |
| Directory | /workspace/13.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/13.rstmgr_sw_rst.309462956 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 116745152 ps |
| CPU time | 1.48 seconds |
| Started | Jan 24 01:05:20 PM PST 24 |
| Finished | Jan 24 01:06:10 PM PST 24 |
| Peak memory | 199680 kb |
| Host | smart-894ebc05-a7c3-4721-8892-4e926c57ab6f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=309462956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.309462956 |
| Directory | /workspace/13.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.2058338833 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 73107271 ps |
| CPU time | 0.76 seconds |
| Started | Jan 24 01:05:28 PM PST 24 |
| Finished | Jan 24 01:06:19 PM PST 24 |
| Peak memory | 199528 kb |
| Host | smart-717be006-5bac-4ddf-89f9-11ec37d3bd15 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2058338833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2058338833 |
| Directory | /workspace/13.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/14.rstmgr_alert_test.1837824753 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 80869980 ps |
| CPU time | 0.81 seconds |
| Started | Jan 24 01:05:39 PM PST 24 |
| Finished | Jan 24 01:06:30 PM PST 24 |
| Peak memory | 199500 kb |
| Host | smart-1b4be6a6-0e22-445a-98aa-8d6d6bc81d3c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837824753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.1837824753 |
| Directory | /workspace/14.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.851622433 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 2350674307 ps |
| CPU time | 8.13 seconds |
| Started | Jan 24 01:28:44 PM PST 24 |
| Finished | Jan 24 01:29:14 PM PST 24 |
| Peak memory | 221712 kb |
| Host | smart-e10b8b22-f8f9-4348-aadf-8cd802825904 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=851622433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.851622433 |
| Directory | /workspace/14.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2913875574 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 244493982 ps |
| CPU time | 1.04 seconds |
| Started | Jan 24 01:05:34 PM PST 24 |
| Finished | Jan 24 01:06:25 PM PST 24 |
| Peak memory | 216792 kb |
| Host | smart-1da54270-5416-4a19-810f-d0ddd238f4e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2913875574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2913875574 |
| Directory | /workspace/14.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/14.rstmgr_por_stretcher.1680089488 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 93578782 ps |
| CPU time | 0.79 seconds |
| Started | Jan 24 01:05:48 PM PST 24 |
| Finished | Jan 24 01:06:42 PM PST 24 |
| Peak memory | 199340 kb |
| Host | smart-cffaf842-7f9e-4a60-a437-e8b55969e8d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1680089488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.1680089488 |
| Directory | /workspace/14.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/14.rstmgr_reset.1321090687 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 985794938 ps |
| CPU time | 5.12 seconds |
| Started | Jan 24 01:05:40 PM PST 24 |
| Finished | Jan 24 01:06:35 PM PST 24 |
| Peak memory | 199796 kb |
| Host | smart-31566cce-bfd2-454e-94a3-5bb1bef68162 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1321090687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1321090687 |
| Directory | /workspace/14.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.268110108 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 106580963 ps |
| CPU time | 1.04 seconds |
| Started | Jan 24 01:41:42 PM PST 24 |
| Finished | Jan 24 01:41:47 PM PST 24 |
| Peak memory | 199532 kb |
| Host | smart-cbe0bed5-cd93-4ea6-85d0-383f61421816 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=268110108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.268110108 |
| Directory | /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/14.rstmgr_smoke.1575529264 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 187916198 ps |
| CPU time | 1.26 seconds |
| Started | Jan 24 01:05:41 PM PST 24 |
| Finished | Jan 24 01:06:32 PM PST 24 |
| Peak memory | 199744 kb |
| Host | smart-b9a6fc8c-f7af-4e24-9044-d76d1ebd559f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1575529264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.1575529264 |
| Directory | /workspace/14.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/14.rstmgr_stress_all.382259585 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 3314691088 ps |
| CPU time | 15.78 seconds |
| Started | Jan 24 01:09:53 PM PST 24 |
| Finished | Jan 24 01:10:44 PM PST 24 |
| Peak memory | 199784 kb |
| Host | smart-0c81cece-e22a-466a-8adb-38726004a795 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382259585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.382259585 |
| Directory | /workspace/14.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/14.rstmgr_sw_rst.739951678 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 367232983 ps |
| CPU time | 2 seconds |
| Started | Jan 24 01:05:48 PM PST 24 |
| Finished | Jan 24 01:06:43 PM PST 24 |
| Peak memory | 199624 kb |
| Host | smart-bdbea512-fe99-4a2d-9d42-386aec475d5a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=739951678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.739951678 |
| Directory | /workspace/14.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.4091030039 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 134778694 ps |
| CPU time | 0.94 seconds |
| Started | Jan 24 01:05:41 PM PST 24 |
| Finished | Jan 24 01:06:32 PM PST 24 |
| Peak memory | 199560 kb |
| Host | smart-d17207c2-8804-41c7-bd2e-79c2b8a1b7e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4091030039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.4091030039 |
| Directory | /workspace/14.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.3864759972 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 1903758942 ps |
| CPU time | 7.03 seconds |
| Started | Jan 24 01:05:48 PM PST 24 |
| Finished | Jan 24 01:06:48 PM PST 24 |
| Peak memory | 216384 kb |
| Host | smart-8c883908-fe0a-429e-b748-45979c44b6d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3864759972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.3864759972 |
| Directory | /workspace/15.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1924123123 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 244750356 ps |
| CPU time | 1.02 seconds |
| Started | Jan 24 01:05:48 PM PST 24 |
| Finished | Jan 24 01:06:41 PM PST 24 |
| Peak memory | 216748 kb |
| Host | smart-5ef0452d-702a-45f5-a29a-39cd16aaa9dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1924123123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1924123123 |
| Directory | /workspace/15.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/15.rstmgr_por_stretcher.121724286 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 121454458 ps |
| CPU time | 0.74 seconds |
| Started | Jan 24 01:05:48 PM PST 24 |
| Finished | Jan 24 01:06:41 PM PST 24 |
| Peak memory | 199360 kb |
| Host | smart-d91b2aa1-d337-41f9-b52c-039acbd4b7dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=121724286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.121724286 |
| Directory | /workspace/15.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/15.rstmgr_reset.2131160460 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 813366473 ps |
| CPU time | 4.55 seconds |
| Started | Jan 24 01:45:40 PM PST 24 |
| Finished | Jan 24 01:45:50 PM PST 24 |
| Peak memory | 199708 kb |
| Host | smart-acd544a7-7936-42a2-85cb-73f7abaca39d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2131160460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2131160460 |
| Directory | /workspace/15.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.88722133 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 95113942 ps |
| CPU time | 1.01 seconds |
| Started | Jan 24 01:29:37 PM PST 24 |
| Finished | Jan 24 01:29:51 PM PST 24 |
| Peak memory | 199568 kb |
| Host | smart-526e2680-963f-459f-8356-2cbe75ee4acf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=88722133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.88722133 |
| Directory | /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/15.rstmgr_smoke.3292467393 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 203869784 ps |
| CPU time | 1.49 seconds |
| Started | Jan 24 01:28:59 PM PST 24 |
| Finished | Jan 24 01:29:17 PM PST 24 |
| Peak memory | 199768 kb |
| Host | smart-6b168276-cdb8-4d75-bd8e-b4d1a219e170 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3292467393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3292467393 |
| Directory | /workspace/15.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/15.rstmgr_stress_all.3563174998 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 5845247791 ps |
| CPU time | 25.72 seconds |
| Started | Jan 24 01:05:48 PM PST 24 |
| Finished | Jan 24 01:07:07 PM PST 24 |
| Peak memory | 199808 kb |
| Host | smart-1f5f1e34-ef38-457e-8206-2ce8d79c2c45 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563174998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.3563174998 |
| Directory | /workspace/15.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/15.rstmgr_sw_rst.1180325834 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 126245262 ps |
| CPU time | 1.72 seconds |
| Started | Jan 24 03:59:43 PM PST 24 |
| Finished | Jan 24 03:59:46 PM PST 24 |
| Peak memory | 199704 kb |
| Host | smart-30a6ef9d-bd01-4cd3-b3a9-28808aae22df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1180325834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.1180325834 |
| Directory | /workspace/15.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3411618558 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 193623652 ps |
| CPU time | 1.3 seconds |
| Started | Jan 24 01:21:47 PM PST 24 |
| Finished | Jan 24 01:22:46 PM PST 24 |
| Peak memory | 199576 kb |
| Host | smart-5e2816b6-3c1d-4b0e-a762-c5653649afbc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3411618558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3411618558 |
| Directory | /workspace/15.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/16.rstmgr_alert_test.1537967755 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 64998125 ps |
| CPU time | 0.75 seconds |
| Started | Jan 24 01:05:53 PM PST 24 |
| Finished | Jan 24 01:06:45 PM PST 24 |
| Peak memory | 199456 kb |
| Host | smart-03167c35-61b8-4314-bd19-228888f57f3b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537967755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1537967755 |
| Directory | /workspace/16.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2123858609 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1892555514 ps |
| CPU time | 7.27 seconds |
| Started | Jan 24 01:05:49 PM PST 24 |
| Finished | Jan 24 01:06:49 PM PST 24 |
| Peak memory | 217668 kb |
| Host | smart-ac1404f6-44e3-4c87-be0c-822d4fd2d7e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2123858609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2123858609 |
| Directory | /workspace/16.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3458348005 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 245192039 ps |
| CPU time | 1.06 seconds |
| Started | Jan 24 01:23:05 PM PST 24 |
| Finished | Jan 24 01:23:58 PM PST 24 |
| Peak memory | 216764 kb |
| Host | smart-ce4cbf74-095b-4a03-bf1d-c21c75dd14e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3458348005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.3458348005 |
| Directory | /workspace/16.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/16.rstmgr_por_stretcher.2418199899 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 101996895 ps |
| CPU time | 0.72 seconds |
| Started | Jan 24 01:38:02 PM PST 24 |
| Finished | Jan 24 01:38:29 PM PST 24 |
| Peak memory | 199392 kb |
| Host | smart-fc7386ca-8509-4a0a-bbd9-fe0942f78073 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2418199899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2418199899 |
| Directory | /workspace/16.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/16.rstmgr_reset.14475167 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 1565798830 ps |
| CPU time | 6.1 seconds |
| Started | Jan 24 01:05:47 PM PST 24 |
| Finished | Jan 24 01:06:45 PM PST 24 |
| Peak memory | 199740 kb |
| Host | smart-20477041-9a2a-4332-a472-6a1b36112cad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=14475167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.14475167 |
| Directory | /workspace/16.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3836577463 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 143746302 ps |
| CPU time | 1.1 seconds |
| Started | Jan 24 01:05:51 PM PST 24 |
| Finished | Jan 24 01:06:45 PM PST 24 |
| Peak memory | 199516 kb |
| Host | smart-e34ebd43-e769-4a97-abf3-a6af41a6dafe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3836577463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3836577463 |
| Directory | /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/16.rstmgr_smoke.3659764367 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 195788481 ps |
| CPU time | 1.26 seconds |
| Started | Jan 24 01:05:50 PM PST 24 |
| Finished | Jan 24 01:06:43 PM PST 24 |
| Peak memory | 199756 kb |
| Host | smart-2029ea03-0ae0-4577-b496-f87fe3105659 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3659764367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3659764367 |
| Directory | /workspace/16.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/16.rstmgr_stress_all.3801762129 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 4222570328 ps |
| CPU time | 15.16 seconds |
| Started | Jan 24 01:05:50 PM PST 24 |
| Finished | Jan 24 01:06:57 PM PST 24 |
| Peak memory | 199856 kb |
| Host | smart-badadf43-23b8-4d57-b9ad-e68db9501f02 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801762129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.3801762129 |
| Directory | /workspace/16.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/16.rstmgr_sw_rst.2485504583 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 300692784 ps |
| CPU time | 1.99 seconds |
| Started | Jan 24 01:05:55 PM PST 24 |
| Finished | Jan 24 01:06:49 PM PST 24 |
| Peak memory | 199648 kb |
| Host | smart-297dcee8-6db3-4ae7-ad1b-255eadfb52b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2485504583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2485504583 |
| Directory | /workspace/16.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.3664385319 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 145527115 ps |
| CPU time | 1 seconds |
| Started | Jan 24 02:32:37 PM PST 24 |
| Finished | Jan 24 02:33:08 PM PST 24 |
| Peak memory | 199588 kb |
| Host | smart-78381cf5-87f8-4ad6-bd1a-18155de5dfdb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3664385319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3664385319 |
| Directory | /workspace/16.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/17.rstmgr_alert_test.2157897108 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 57242000 ps |
| CPU time | 0.71 seconds |
| Started | Jan 24 01:05:57 PM PST 24 |
| Finished | Jan 24 01:06:49 PM PST 24 |
| Peak memory | 199552 kb |
| Host | smart-522a5967-0cad-4327-bb7f-f75d0067df8c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157897108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.2157897108 |
| Directory | /workspace/17.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.3187453358 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 1218539550 ps |
| CPU time | 5.64 seconds |
| Started | Jan 24 01:05:50 PM PST 24 |
| Finished | Jan 24 01:06:48 PM PST 24 |
| Peak memory | 221064 kb |
| Host | smart-4653ba41-71c7-4e06-a5f7-9e9b7349a9ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3187453358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.3187453358 |
| Directory | /workspace/17.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2363848428 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 245366290 ps |
| CPU time | 1.02 seconds |
| Started | Jan 24 01:32:25 PM PST 24 |
| Finished | Jan 24 01:33:06 PM PST 24 |
| Peak memory | 216028 kb |
| Host | smart-3c78e94b-081e-4141-98f2-ebdd4a981a11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2363848428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2363848428 |
| Directory | /workspace/17.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/17.rstmgr_por_stretcher.2622983640 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 187457452 ps |
| CPU time | 0.88 seconds |
| Started | Jan 24 01:06:03 PM PST 24 |
| Finished | Jan 24 01:06:57 PM PST 24 |
| Peak memory | 199368 kb |
| Host | smart-a66e905e-e908-487c-a11e-dab1d00dcf42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2622983640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.2622983640 |
| Directory | /workspace/17.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/17.rstmgr_reset.291474389 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 1296827261 ps |
| CPU time | 5.04 seconds |
| Started | Jan 24 01:05:52 PM PST 24 |
| Finished | Jan 24 01:06:49 PM PST 24 |
| Peak memory | 199708 kb |
| Host | smart-f39c5dcc-52a1-452c-b6a9-7c0b86f9fe44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=291474389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.291474389 |
| Directory | /workspace/17.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.189768840 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 109899931 ps |
| CPU time | 1.01 seconds |
| Started | Jan 24 01:11:38 PM PST 24 |
| Finished | Jan 24 01:12:27 PM PST 24 |
| Peak memory | 199568 kb |
| Host | smart-d4ecae82-5dc5-4530-ad71-595945e3ad0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=189768840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.189768840 |
| Directory | /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/17.rstmgr_smoke.3660253280 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 121746495 ps |
| CPU time | 1.2 seconds |
| Started | Jan 24 01:05:52 PM PST 24 |
| Finished | Jan 24 01:06:45 PM PST 24 |
| Peak memory | 199708 kb |
| Host | smart-034515ee-c971-45b3-980b-47942ff18d34 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3660253280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3660253280 |
| Directory | /workspace/17.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/17.rstmgr_stress_all.2527549152 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 2904258668 ps |
| CPU time | 14.07 seconds |
| Started | Jan 24 01:05:53 PM PST 24 |
| Finished | Jan 24 01:06:58 PM PST 24 |
| Peak memory | 199896 kb |
| Host | smart-24b98861-b2a7-4305-a538-989e4a3f294f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527549152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.2527549152 |
| Directory | /workspace/17.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/17.rstmgr_sw_rst.895441566 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 376448640 ps |
| CPU time | 2.33 seconds |
| Started | Jan 24 01:05:55 PM PST 24 |
| Finished | Jan 24 01:06:49 PM PST 24 |
| Peak memory | 199660 kb |
| Host | smart-b445a899-907f-45e7-ae4f-6ba175f51b36 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=895441566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.895441566 |
| Directory | /workspace/17.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.496018015 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 154287867 ps |
| CPU time | 1.06 seconds |
| Started | Jan 24 01:05:50 PM PST 24 |
| Finished | Jan 24 01:06:43 PM PST 24 |
| Peak memory | 199584 kb |
| Host | smart-1b4796b5-139e-4c81-b7ee-bfe10b39aff9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=496018015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.496018015 |
| Directory | /workspace/17.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/18.rstmgr_alert_test.1653032892 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 68194592 ps |
| CPU time | 0.76 seconds |
| Started | Jan 24 01:06:00 PM PST 24 |
| Finished | Jan 24 01:06:52 PM PST 24 |
| Peak memory | 199568 kb |
| Host | smart-7fb7c953-9f28-4de5-9517-dc1a19b3be84 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653032892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1653032892 |
| Directory | /workspace/18.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.822169076 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1238456708 ps |
| CPU time | 5.37 seconds |
| Started | Jan 24 01:05:59 PM PST 24 |
| Finished | Jan 24 01:06:55 PM PST 24 |
| Peak memory | 221080 kb |
| Host | smart-2163a90f-6154-42c7-9210-b7e300b1d524 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=822169076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.822169076 |
| Directory | /workspace/18.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.4173923323 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 243070818 ps |
| CPU time | 1.1 seconds |
| Started | Jan 24 01:06:03 PM PST 24 |
| Finished | Jan 24 01:06:58 PM PST 24 |
| Peak memory | 216892 kb |
| Host | smart-faa6252b-31cf-4caf-b6ab-afa9e28d5d0f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4173923323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.4173923323 |
| Directory | /workspace/18.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/18.rstmgr_por_stretcher.3360123337 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 149114759 ps |
| CPU time | 0.82 seconds |
| Started | Jan 24 01:28:08 PM PST 24 |
| Finished | Jan 24 01:28:36 PM PST 24 |
| Peak memory | 199312 kb |
| Host | smart-b9a2d67c-9e33-4d61-8050-f3a8b32df33a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3360123337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.3360123337 |
| Directory | /workspace/18.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/18.rstmgr_reset.300019967 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 944873776 ps |
| CPU time | 4.67 seconds |
| Started | Jan 24 01:06:07 PM PST 24 |
| Finished | Jan 24 01:07:07 PM PST 24 |
| Peak memory | 199760 kb |
| Host | smart-b886e59d-f92b-4b0f-9b2b-21a4a47bb5a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=300019967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.300019967 |
| Directory | /workspace/18.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2507493742 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 146109052 ps |
| CPU time | 1.08 seconds |
| Started | Jan 24 01:06:14 PM PST 24 |
| Finished | Jan 24 01:07:09 PM PST 24 |
| Peak memory | 199560 kb |
| Host | smart-75f449f4-e64d-4751-90b6-778c498ffcdf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2507493742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2507493742 |
| Directory | /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/18.rstmgr_smoke.707665081 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 193038202 ps |
| CPU time | 1.34 seconds |
| Started | Jan 24 01:06:02 PM PST 24 |
| Finished | Jan 24 01:06:56 PM PST 24 |
| Peak memory | 199768 kb |
| Host | smart-f36cf304-828f-4e4a-8605-42a870ea031b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=707665081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.707665081 |
| Directory | /workspace/18.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/18.rstmgr_stress_all.768260597 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 533918876 ps |
| CPU time | 3 seconds |
| Started | Jan 24 01:06:01 PM PST 24 |
| Finished | Jan 24 01:06:57 PM PST 24 |
| Peak memory | 199828 kb |
| Host | smart-2407b85b-bc48-40b7-94c4-dc18e94548e3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768260597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.768260597 |
| Directory | /workspace/18.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/18.rstmgr_sw_rst.3730050159 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 439322495 ps |
| CPU time | 2.57 seconds |
| Started | Jan 24 01:06:06 PM PST 24 |
| Finished | Jan 24 01:07:02 PM PST 24 |
| Peak memory | 199576 kb |
| Host | smart-01567d2a-d900-4848-a3e8-c1d6eb976c1d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3730050159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.3730050159 |
| Directory | /workspace/18.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2863534062 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 88908733 ps |
| CPU time | 0.82 seconds |
| Started | Jan 24 01:05:59 PM PST 24 |
| Finished | Jan 24 01:06:52 PM PST 24 |
| Peak memory | 199568 kb |
| Host | smart-a9a38af0-bab9-45c3-bf99-11ee82d1c03d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2863534062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2863534062 |
| Directory | /workspace/18.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/19.rstmgr_alert_test.2751518413 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 54188153 ps |
| CPU time | 0.75 seconds |
| Started | Jan 24 01:06:03 PM PST 24 |
| Finished | Jan 24 01:06:57 PM PST 24 |
| Peak memory | 199560 kb |
| Host | smart-790df814-9c4a-4237-afbe-428525202a79 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751518413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2751518413 |
| Directory | /workspace/19.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2276610795 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 244909572 ps |
| CPU time | 1.05 seconds |
| Started | Jan 24 01:06:03 PM PST 24 |
| Finished | Jan 24 01:06:58 PM PST 24 |
| Peak memory | 216776 kb |
| Host | smart-504165e1-7c33-438d-9c38-a19eb5b44847 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2276610795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2276610795 |
| Directory | /workspace/19.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/19.rstmgr_por_stretcher.4206449780 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 232453031 ps |
| CPU time | 0.92 seconds |
| Started | Jan 24 01:05:59 PM PST 24 |
| Finished | Jan 24 01:06:52 PM PST 24 |
| Peak memory | 199372 kb |
| Host | smart-d0692242-0a9b-4a6c-9852-41e8ce75afa3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4206449780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.4206449780 |
| Directory | /workspace/19.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/19.rstmgr_reset.1882392823 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 1025406567 ps |
| CPU time | 4.68 seconds |
| Started | Jan 24 01:06:01 PM PST 24 |
| Finished | Jan 24 01:06:58 PM PST 24 |
| Peak memory | 199800 kb |
| Host | smart-f1c32ebd-b10a-46b7-a7cb-21988514619d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1882392823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.1882392823 |
| Directory | /workspace/19.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3141738025 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 143441152 ps |
| CPU time | 1.12 seconds |
| Started | Jan 24 02:02:31 PM PST 24 |
| Finished | Jan 24 02:02:46 PM PST 24 |
| Peak memory | 199588 kb |
| Host | smart-e63b1044-07aa-425c-8128-4d183309f106 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3141738025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3141738025 |
| Directory | /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/19.rstmgr_smoke.2734948940 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 214152233 ps |
| CPU time | 1.39 seconds |
| Started | Jan 24 01:06:14 PM PST 24 |
| Finished | Jan 24 01:07:10 PM PST 24 |
| Peak memory | 199744 kb |
| Host | smart-4714a744-1406-41bf-bedc-aca2b666f0bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2734948940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2734948940 |
| Directory | /workspace/19.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/19.rstmgr_stress_all.1637621920 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 3802894013 ps |
| CPU time | 16.9 seconds |
| Started | Jan 24 02:54:58 PM PST 24 |
| Finished | Jan 24 02:55:26 PM PST 24 |
| Peak memory | 199928 kb |
| Host | smart-a7b5a72b-36b0-4df2-be47-e6a92f301d3d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637621920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1637621920 |
| Directory | /workspace/19.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.3739317276 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 242708307 ps |
| CPU time | 1.36 seconds |
| Started | Jan 24 01:06:05 PM PST 24 |
| Finished | Jan 24 01:07:01 PM PST 24 |
| Peak memory | 199728 kb |
| Host | smart-b6948589-2b19-45e3-ae41-a1a06d555af4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3739317276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.3739317276 |
| Directory | /workspace/19.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/2.rstmgr_alert_test.2362856419 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 77771746 ps |
| CPU time | 0.78 seconds |
| Started | Jan 24 01:04:14 PM PST 24 |
| Finished | Jan 24 01:05:00 PM PST 24 |
| Peak memory | 199452 kb |
| Host | smart-ba3a304f-65cf-40e3-951a-9d22c98b8b5a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362856419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.2362856419 |
| Directory | /workspace/2.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2325385771 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 2176623980 ps |
| CPU time | 7.95 seconds |
| Started | Jan 24 01:04:18 PM PST 24 |
| Finished | Jan 24 01:05:09 PM PST 24 |
| Peak memory | 216248 kb |
| Host | smart-f4544ef4-091c-4ed7-b3ed-c3289e4b7c88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2325385771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2325385771 |
| Directory | /workspace/2.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1080798912 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 244080633 ps |
| CPU time | 1.03 seconds |
| Started | Jan 24 01:04:12 PM PST 24 |
| Finished | Jan 24 01:04:58 PM PST 24 |
| Peak memory | 216360 kb |
| Host | smart-b43b2f7a-dc03-486d-8136-dd23b2c9e2e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1080798912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.1080798912 |
| Directory | /workspace/2.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/2.rstmgr_por_stretcher.762438359 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 87942666 ps |
| CPU time | 0.88 seconds |
| Started | Jan 24 01:04:05 PM PST 24 |
| Finished | Jan 24 01:04:51 PM PST 24 |
| Peak memory | 199328 kb |
| Host | smart-d064d5e3-2d7f-4db6-b4a1-3367126cf0f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=762438359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.762438359 |
| Directory | /workspace/2.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/2.rstmgr_reset.3561500100 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 903331163 ps |
| CPU time | 4.32 seconds |
| Started | Jan 24 01:04:14 PM PST 24 |
| Finished | Jan 24 01:05:04 PM PST 24 |
| Peak memory | 199728 kb |
| Host | smart-b17d96ae-abfb-4315-bca9-afff561d8f28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3561500100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3561500100 |
| Directory | /workspace/2.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/2.rstmgr_sec_cm.2319505462 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 8646602944 ps |
| CPU time | 14.68 seconds |
| Started | Jan 24 01:04:14 PM PST 24 |
| Finished | Jan 24 01:05:14 PM PST 24 |
| Peak memory | 216516 kb |
| Host | smart-00b31a8b-a605-4c49-87eb-b3467bf69970 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319505462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2319505462 |
| Directory | /workspace/2.rstmgr_sec_cm/latest |
| Test location | /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3812203854 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 156163285 ps |
| CPU time | 1.04 seconds |
| Started | Jan 24 01:04:12 PM PST 24 |
| Finished | Jan 24 01:04:57 PM PST 24 |
| Peak memory | 199432 kb |
| Host | smart-db9a3fb1-cbe1-4958-abc4-38f34899e4b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3812203854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3812203854 |
| Directory | /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/2.rstmgr_smoke.1105865255 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 112902131 ps |
| CPU time | 1.19 seconds |
| Started | Jan 24 01:04:10 PM PST 24 |
| Finished | Jan 24 01:04:55 PM PST 24 |
| Peak memory | 199792 kb |
| Host | smart-85e983d5-b900-4edf-96f7-ecd65436e540 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1105865255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1105865255 |
| Directory | /workspace/2.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/2.rstmgr_stress_all.1657327474 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 418736932 ps |
| CPU time | 1.93 seconds |
| Started | Jan 24 01:04:09 PM PST 24 |
| Finished | Jan 24 01:04:55 PM PST 24 |
| Peak memory | 199564 kb |
| Host | smart-12290f21-db26-4666-82ad-89c083fd0b9a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657327474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1657327474 |
| Directory | /workspace/2.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/2.rstmgr_sw_rst.1454164626 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 314702030 ps |
| CPU time | 2.17 seconds |
| Started | Jan 24 01:04:13 PM PST 24 |
| Finished | Jan 24 01:05:00 PM PST 24 |
| Peak memory | 199576 kb |
| Host | smart-b22d9832-6848-4e6a-8645-4276165b8f20 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1454164626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1454164626 |
| Directory | /workspace/2.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.3407563195 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 100784059 ps |
| CPU time | 0.85 seconds |
| Started | Jan 24 01:04:12 PM PST 24 |
| Finished | Jan 24 01:04:57 PM PST 24 |
| Peak memory | 199424 kb |
| Host | smart-20f43cbc-05ac-4da7-8a8c-e35cd53d8926 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3407563195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.3407563195 |
| Directory | /workspace/2.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/20.rstmgr_alert_test.1336745265 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 97660766 ps |
| CPU time | 0.81 seconds |
| Started | Jan 24 01:06:08 PM PST 24 |
| Finished | Jan 24 01:07:03 PM PST 24 |
| Peak memory | 199456 kb |
| Host | smart-826a3033-cb62-4561-847b-f141acaffaa1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336745265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1336745265 |
| Directory | /workspace/20.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.1263055643 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1887536969 ps |
| CPU time | 7.19 seconds |
| Started | Jan 24 01:06:03 PM PST 24 |
| Finished | Jan 24 01:07:04 PM PST 24 |
| Peak memory | 216392 kb |
| Host | smart-2c7bb84a-828c-4b38-a8ea-bea28a90342e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1263055643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1263055643 |
| Directory | /workspace/20.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.1001367211 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 245280196 ps |
| CPU time | 1.02 seconds |
| Started | Jan 24 01:43:11 PM PST 24 |
| Finished | Jan 24 01:43:38 PM PST 24 |
| Peak memory | 216896 kb |
| Host | smart-756fb631-b50d-4f91-be94-e43e29a53ebc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1001367211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.1001367211 |
| Directory | /workspace/20.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/20.rstmgr_por_stretcher.3967392758 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 198826820 ps |
| CPU time | 0.85 seconds |
| Started | Jan 24 01:36:40 PM PST 24 |
| Finished | Jan 24 01:37:15 PM PST 24 |
| Peak memory | 199364 kb |
| Host | smart-f644c061-231d-4f29-a18e-afbbaa5ab70e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3967392758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3967392758 |
| Directory | /workspace/20.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/20.rstmgr_reset.33028747 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 1031923614 ps |
| CPU time | 4.51 seconds |
| Started | Jan 24 01:06:02 PM PST 24 |
| Finished | Jan 24 01:06:59 PM PST 24 |
| Peak memory | 199764 kb |
| Host | smart-b91b025d-3529-4330-a23e-520956fbc2a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=33028747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.33028747 |
| Directory | /workspace/20.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/20.rstmgr_smoke.2482239280 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 258333243 ps |
| CPU time | 1.53 seconds |
| Started | Jan 24 01:14:34 PM PST 24 |
| Finished | Jan 24 01:15:01 PM PST 24 |
| Peak memory | 199800 kb |
| Host | smart-b693df8d-6f51-4700-9c75-bf3b0e77baa3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2482239280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2482239280 |
| Directory | /workspace/20.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/20.rstmgr_stress_all.2012215988 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 852623460 ps |
| CPU time | 3.9 seconds |
| Started | Jan 24 01:18:26 PM PST 24 |
| Finished | Jan 24 01:19:11 PM PST 24 |
| Peak memory | 199836 kb |
| Host | smart-dcd9e45c-f512-4de3-9cba-bb1cf3bb6819 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012215988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2012215988 |
| Directory | /workspace/20.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/20.rstmgr_sw_rst.3089664825 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 146407813 ps |
| CPU time | 1.73 seconds |
| Started | Jan 24 01:55:42 PM PST 24 |
| Finished | Jan 24 01:55:44 PM PST 24 |
| Peak memory | 199672 kb |
| Host | smart-4d8b2149-a7f6-45e7-ab91-76ce72225244 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3089664825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3089664825 |
| Directory | /workspace/20.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.178659839 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 77813664 ps |
| CPU time | 0.85 seconds |
| Started | Jan 24 02:57:34 PM PST 24 |
| Finished | Jan 24 02:57:46 PM PST 24 |
| Peak memory | 199648 kb |
| Host | smart-d88dd8f0-e9e0-4978-a6e8-df1139344475 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=178659839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.178659839 |
| Directory | /workspace/20.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/21.rstmgr_alert_test.2227172680 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 71654974 ps |
| CPU time | 0.78 seconds |
| Started | Jan 24 01:19:32 PM PST 24 |
| Finished | Jan 24 01:20:34 PM PST 24 |
| Peak memory | 199520 kb |
| Host | smart-5388f2c9-642c-4fa2-bf99-8b566690ad00 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227172680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2227172680 |
| Directory | /workspace/21.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1870893646 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 1222036327 ps |
| CPU time | 5.35 seconds |
| Started | Jan 24 01:06:14 PM PST 24 |
| Finished | Jan 24 01:07:14 PM PST 24 |
| Peak memory | 220548 kb |
| Host | smart-4f9cb762-3622-467f-a562-9a3e7219ae42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1870893646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1870893646 |
| Directory | /workspace/21.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2918404802 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 244650259 ps |
| CPU time | 1.06 seconds |
| Started | Jan 24 02:03:30 PM PST 24 |
| Finished | Jan 24 02:04:37 PM PST 24 |
| Peak memory | 216752 kb |
| Host | smart-99c03200-ca57-424d-876f-7ea2fccfb1a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2918404802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2918404802 |
| Directory | /workspace/21.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/21.rstmgr_por_stretcher.3003331524 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 126955197 ps |
| CPU time | 0.78 seconds |
| Started | Jan 24 01:06:18 PM PST 24 |
| Finished | Jan 24 01:07:15 PM PST 24 |
| Peak memory | 199360 kb |
| Host | smart-27bae1d7-6ed8-42a8-ac21-250abaf42db3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3003331524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.3003331524 |
| Directory | /workspace/21.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/21.rstmgr_reset.2789435793 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 1138043786 ps |
| CPU time | 4.84 seconds |
| Started | Jan 24 01:06:18 PM PST 24 |
| Finished | Jan 24 01:07:18 PM PST 24 |
| Peak memory | 199756 kb |
| Host | smart-36452934-9f41-4a67-9658-cac81bf640b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789435793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.2789435793 |
| Directory | /workspace/21.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.391637527 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 106522393 ps |
| CPU time | 0.95 seconds |
| Started | Jan 24 01:23:47 PM PST 24 |
| Finished | Jan 24 01:24:31 PM PST 24 |
| Peak memory | 199592 kb |
| Host | smart-277efaa1-2f6c-490b-a937-e20d2b60545e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=391637527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.391637527 |
| Directory | /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/21.rstmgr_smoke.1496358765 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 121374262 ps |
| CPU time | 1.09 seconds |
| Started | Jan 24 01:06:01 PM PST 24 |
| Finished | Jan 24 01:06:55 PM PST 24 |
| Peak memory | 199740 kb |
| Host | smart-2dd15e0b-2881-4b5b-9d84-5e1c64fde9f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1496358765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1496358765 |
| Directory | /workspace/21.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/21.rstmgr_stress_all.966460764 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 3133840465 ps |
| CPU time | 15.51 seconds |
| Started | Jan 24 01:06:18 PM PST 24 |
| Finished | Jan 24 01:07:29 PM PST 24 |
| Peak memory | 199840 kb |
| Host | smart-3d51d181-af8a-467c-89f9-545a09fc3c16 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966460764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.966460764 |
| Directory | /workspace/21.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/21.rstmgr_sw_rst.2530828636 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 129742210 ps |
| CPU time | 1.58 seconds |
| Started | Jan 24 01:06:14 PM PST 24 |
| Finished | Jan 24 01:07:10 PM PST 24 |
| Peak memory | 199624 kb |
| Host | smart-4afdee0a-3dc1-490e-bd01-41078775dad8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2530828636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2530828636 |
| Directory | /workspace/21.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.204048980 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 82736021 ps |
| CPU time | 0.81 seconds |
| Started | Jan 24 01:06:12 PM PST 24 |
| Finished | Jan 24 01:07:09 PM PST 24 |
| Peak memory | 199512 kb |
| Host | smart-3bda518c-2d5e-4a18-89e6-b7889c4ee0d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=204048980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.204048980 |
| Directory | /workspace/21.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/22.rstmgr_alert_test.1179926080 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 76409720 ps |
| CPU time | 0.78 seconds |
| Started | Jan 24 02:30:31 PM PST 24 |
| Finished | Jan 24 02:30:44 PM PST 24 |
| Peak memory | 199556 kb |
| Host | smart-45351850-147a-44d6-a3b3-22a4337febf3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179926080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1179926080 |
| Directory | /workspace/22.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1605959119 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1884413640 ps |
| CPU time | 7.26 seconds |
| Started | Jan 24 01:06:11 PM PST 24 |
| Finished | Jan 24 01:07:15 PM PST 24 |
| Peak memory | 220540 kb |
| Host | smart-752352cb-a584-45a4-a119-80750bccfc6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1605959119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1605959119 |
| Directory | /workspace/22.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3199337639 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 245400444 ps |
| CPU time | 1.05 seconds |
| Started | Jan 24 01:39:18 PM PST 24 |
| Finished | Jan 24 01:39:21 PM PST 24 |
| Peak memory | 216868 kb |
| Host | smart-1ace68f5-2bf0-401f-afea-9d559e85e894 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3199337639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.3199337639 |
| Directory | /workspace/22.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/22.rstmgr_por_stretcher.2018239339 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 85071622 ps |
| CPU time | 0.74 seconds |
| Started | Jan 24 01:49:47 PM PST 24 |
| Finished | Jan 24 01:49:50 PM PST 24 |
| Peak memory | 199364 kb |
| Host | smart-f00d5369-dbe5-4ef6-91da-34d177fef1c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2018239339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2018239339 |
| Directory | /workspace/22.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/22.rstmgr_reset.578658798 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 1706715268 ps |
| CPU time | 6.96 seconds |
| Started | Jan 24 01:06:07 PM PST 24 |
| Finished | Jan 24 01:07:08 PM PST 24 |
| Peak memory | 199744 kb |
| Host | smart-b04f2b8f-1f78-4c84-b6c1-9fe2642db2ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=578658798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.578658798 |
| Directory | /workspace/22.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.2043552019 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 96583225 ps |
| CPU time | 0.93 seconds |
| Started | Jan 24 01:06:14 PM PST 24 |
| Finished | Jan 24 01:07:09 PM PST 24 |
| Peak memory | 199528 kb |
| Host | smart-105fee47-b5e6-4dda-b732-a0008a145b3a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2043552019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.2043552019 |
| Directory | /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/22.rstmgr_smoke.1204447354 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 199705990 ps |
| CPU time | 1.36 seconds |
| Started | Jan 24 01:21:47 PM PST 24 |
| Finished | Jan 24 01:22:46 PM PST 24 |
| Peak memory | 199776 kb |
| Host | smart-012d83cf-5f90-45b8-8943-831ea0fc4465 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1204447354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.1204447354 |
| Directory | /workspace/22.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/22.rstmgr_sw_rst.874548870 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 469793099 ps |
| CPU time | 2.56 seconds |
| Started | Jan 24 01:06:14 PM PST 24 |
| Finished | Jan 24 01:07:11 PM PST 24 |
| Peak memory | 199596 kb |
| Host | smart-e8d30d43-a268-4ddf-9516-cbb87646de1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=874548870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.874548870 |
| Directory | /workspace/22.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3968482735 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 290289217 ps |
| CPU time | 1.55 seconds |
| Started | Jan 24 01:06:23 PM PST 24 |
| Finished | Jan 24 01:07:21 PM PST 24 |
| Peak memory | 199580 kb |
| Host | smart-f14e8bb6-3a62-4861-b866-2a9ee4e30550 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3968482735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3968482735 |
| Directory | /workspace/22.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/23.rstmgr_alert_test.3743599653 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 70581477 ps |
| CPU time | 0.74 seconds |
| Started | Jan 24 01:06:19 PM PST 24 |
| Finished | Jan 24 01:07:15 PM PST 24 |
| Peak memory | 199508 kb |
| Host | smart-77de4107-1c8d-41ce-9663-86e434d2a7ec |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743599653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3743599653 |
| Directory | /workspace/23.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3773446776 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 2175582660 ps |
| CPU time | 7.18 seconds |
| Started | Jan 24 01:06:21 PM PST 24 |
| Finished | Jan 24 01:07:24 PM PST 24 |
| Peak memory | 216608 kb |
| Host | smart-8d279a23-4613-46f8-9f89-83f52ef478c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3773446776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3773446776 |
| Directory | /workspace/23.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3498142843 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 244946079 ps |
| CPU time | 1.02 seconds |
| Started | Jan 24 01:06:26 PM PST 24 |
| Finished | Jan 24 01:07:24 PM PST 24 |
| Peak memory | 216844 kb |
| Host | smart-c7463806-c3e0-44e9-b4a9-2311971bc44c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3498142843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3498142843 |
| Directory | /workspace/23.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/23.rstmgr_por_stretcher.275929943 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 176030310 ps |
| CPU time | 0.84 seconds |
| Started | Jan 24 01:06:20 PM PST 24 |
| Finished | Jan 24 01:07:16 PM PST 24 |
| Peak memory | 199372 kb |
| Host | smart-2fbee606-fb66-4710-8fea-9763fa19f310 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=275929943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.275929943 |
| Directory | /workspace/23.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/23.rstmgr_reset.3158017938 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1577961498 ps |
| CPU time | 6.2 seconds |
| Started | Jan 24 01:06:19 PM PST 24 |
| Finished | Jan 24 01:07:21 PM PST 24 |
| Peak memory | 199728 kb |
| Host | smart-5dc513c2-f84d-4e96-b3fc-4fb10edcc97a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3158017938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.3158017938 |
| Directory | /workspace/23.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3620002963 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 181525002 ps |
| CPU time | 1.16 seconds |
| Started | Jan 24 01:06:26 PM PST 24 |
| Finished | Jan 24 01:07:24 PM PST 24 |
| Peak memory | 199536 kb |
| Host | smart-247c2f1e-f0be-427c-a47b-3c704a664792 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3620002963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3620002963 |
| Directory | /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/23.rstmgr_smoke.3513776293 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 121525831 ps |
| CPU time | 1.15 seconds |
| Started | Jan 24 01:11:33 PM PST 24 |
| Finished | Jan 24 01:12:18 PM PST 24 |
| Peak memory | 199764 kb |
| Host | smart-d6706fdb-5556-4259-9771-2727297e163e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3513776293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3513776293 |
| Directory | /workspace/23.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/23.rstmgr_stress_all.189868358 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 80904982 ps |
| CPU time | 0.77 seconds |
| Started | Jan 24 01:06:28 PM PST 24 |
| Finished | Jan 24 01:07:26 PM PST 24 |
| Peak memory | 199328 kb |
| Host | smart-780635e7-fc70-4f47-a1d0-4f84f696f327 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189868358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.189868358 |
| Directory | /workspace/23.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/23.rstmgr_sw_rst.367584969 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 515029602 ps |
| CPU time | 2.54 seconds |
| Started | Jan 24 01:06:22 PM PST 24 |
| Finished | Jan 24 01:07:21 PM PST 24 |
| Peak memory | 199656 kb |
| Host | smart-6db64f0e-3459-4f69-a487-2d8dc3706dbe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=367584969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.367584969 |
| Directory | /workspace/23.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.1553647218 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 148831241 ps |
| CPU time | 1.21 seconds |
| Started | Jan 24 01:06:26 PM PST 24 |
| Finished | Jan 24 01:07:24 PM PST 24 |
| Peak memory | 199568 kb |
| Host | smart-41c09edf-fcee-48af-8444-0fa348b46d30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1553647218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.1553647218 |
| Directory | /workspace/23.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/24.rstmgr_alert_test.379677378 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 66369198 ps |
| CPU time | 0.71 seconds |
| Started | Jan 24 01:06:34 PM PST 24 |
| Finished | Jan 24 01:07:34 PM PST 24 |
| Peak memory | 199568 kb |
| Host | smart-de588a7e-6057-4b33-83d0-39d806d568f6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379677378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.379677378 |
| Directory | /workspace/24.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.4242076253 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 2186541103 ps |
| CPU time | 7.65 seconds |
| Started | Jan 24 01:06:24 PM PST 24 |
| Finished | Jan 24 01:07:27 PM PST 24 |
| Peak memory | 217140 kb |
| Host | smart-def3ba21-08cf-4994-aebc-0c54716106c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4242076253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.4242076253 |
| Directory | /workspace/24.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.242075603 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 245108581 ps |
| CPU time | 1.1 seconds |
| Started | Jan 24 01:06:33 PM PST 24 |
| Finished | Jan 24 01:07:33 PM PST 24 |
| Peak memory | 216908 kb |
| Host | smart-f526956e-06d0-454d-8c57-c4de9a216024 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=242075603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.242075603 |
| Directory | /workspace/24.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/24.rstmgr_por_stretcher.4137270541 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 91278253 ps |
| CPU time | 0.69 seconds |
| Started | Jan 24 01:06:23 PM PST 24 |
| Finished | Jan 24 01:07:19 PM PST 24 |
| Peak memory | 199368 kb |
| Host | smart-a44debc0-dbab-42c8-839f-b189aa5ee983 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4137270541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.4137270541 |
| Directory | /workspace/24.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/24.rstmgr_reset.265362887 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 977668290 ps |
| CPU time | 4.68 seconds |
| Started | Jan 24 01:06:28 PM PST 24 |
| Finished | Jan 24 01:07:30 PM PST 24 |
| Peak memory | 199668 kb |
| Host | smart-4caa85a7-b8fd-4e5d-ab14-5ff283d27e1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=265362887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.265362887 |
| Directory | /workspace/24.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.2493510437 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 178287657 ps |
| CPU time | 1.13 seconds |
| Started | Jan 24 01:06:20 PM PST 24 |
| Finished | Jan 24 01:07:16 PM PST 24 |
| Peak memory | 199620 kb |
| Host | smart-cc8a4129-93c9-469e-9e7a-adff46d15569 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2493510437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.2493510437 |
| Directory | /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/24.rstmgr_smoke.2518882400 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 112489921 ps |
| CPU time | 1.11 seconds |
| Started | Jan 24 01:06:20 PM PST 24 |
| Finished | Jan 24 01:07:16 PM PST 24 |
| Peak memory | 199768 kb |
| Host | smart-c2994230-1733-4607-9793-dc8add8ee5fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2518882400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2518882400 |
| Directory | /workspace/24.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/24.rstmgr_stress_all.241166879 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 105910395 ps |
| CPU time | 0.83 seconds |
| Started | Jan 24 01:06:33 PM PST 24 |
| Finished | Jan 24 01:07:33 PM PST 24 |
| Peak memory | 199444 kb |
| Host | smart-f4b022da-104a-485b-99c4-0670e04b969f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241166879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.241166879 |
| Directory | /workspace/24.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/24.rstmgr_sw_rst.4013456697 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 259538708 ps |
| CPU time | 1.83 seconds |
| Started | Jan 24 01:06:24 PM PST 24 |
| Finished | Jan 24 01:07:21 PM PST 24 |
| Peak memory | 199592 kb |
| Host | smart-b82e720f-e844-4f04-81bb-b58d1472634f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4013456697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.4013456697 |
| Directory | /workspace/24.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.149417935 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 68031188 ps |
| CPU time | 0.79 seconds |
| Started | Jan 24 01:06:28 PM PST 24 |
| Finished | Jan 24 01:07:26 PM PST 24 |
| Peak memory | 199456 kb |
| Host | smart-92c3bbc2-80ff-488a-b05c-85992f99c217 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=149417935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.149417935 |
| Directory | /workspace/24.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/25.rstmgr_alert_test.2173541925 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 76415659 ps |
| CPU time | 0.75 seconds |
| Started | Jan 24 01:06:35 PM PST 24 |
| Finished | Jan 24 01:07:34 PM PST 24 |
| Peak memory | 199544 kb |
| Host | smart-73f893d7-caba-40d1-996e-5f1fb25d453f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173541925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.2173541925 |
| Directory | /workspace/25.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.1589452005 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1221368238 ps |
| CPU time | 6 seconds |
| Started | Jan 24 01:06:31 PM PST 24 |
| Finished | Jan 24 01:07:35 PM PST 24 |
| Peak memory | 217536 kb |
| Host | smart-f6551f7c-1e61-40cd-a601-8ebfd3b42f7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1589452005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1589452005 |
| Directory | /workspace/25.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3605990438 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 244872226 ps |
| CPU time | 1.06 seconds |
| Started | Jan 24 01:06:37 PM PST 24 |
| Finished | Jan 24 01:07:37 PM PST 24 |
| Peak memory | 216908 kb |
| Host | smart-ba6acbdc-a3aa-4b74-82d4-bce235e7f4f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3605990438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3605990438 |
| Directory | /workspace/25.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/25.rstmgr_por_stretcher.2148964483 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 134743885 ps |
| CPU time | 0.84 seconds |
| Started | Jan 24 01:06:33 PM PST 24 |
| Finished | Jan 24 01:07:33 PM PST 24 |
| Peak memory | 199364 kb |
| Host | smart-b1466936-eb50-49c5-a5a9-251ad5343ab9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2148964483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2148964483 |
| Directory | /workspace/25.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/25.rstmgr_reset.2029517238 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 1061575309 ps |
| CPU time | 5.07 seconds |
| Started | Jan 24 01:06:36 PM PST 24 |
| Finished | Jan 24 01:07:41 PM PST 24 |
| Peak memory | 199796 kb |
| Host | smart-90822558-3574-457e-b0ae-b7a938a6f36e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2029517238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.2029517238 |
| Directory | /workspace/25.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1249438899 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 98824041 ps |
| CPU time | 0.97 seconds |
| Started | Jan 24 01:06:32 PM PST 24 |
| Finished | Jan 24 01:07:32 PM PST 24 |
| Peak memory | 199568 kb |
| Host | smart-90758c02-ee17-4d3d-b0b5-b819d8e17d64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1249438899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1249438899 |
| Directory | /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/25.rstmgr_smoke.3374814784 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 236442167 ps |
| CPU time | 1.41 seconds |
| Started | Jan 24 01:06:31 PM PST 24 |
| Finished | Jan 24 01:07:31 PM PST 24 |
| Peak memory | 199656 kb |
| Host | smart-bd2c05dd-a910-4e92-8220-f44acdc18dce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3374814784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3374814784 |
| Directory | /workspace/25.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/25.rstmgr_stress_all.1771728595 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 7387914012 ps |
| CPU time | 34.93 seconds |
| Started | Jan 24 01:06:37 PM PST 24 |
| Finished | Jan 24 01:08:12 PM PST 24 |
| Peak memory | 199920 kb |
| Host | smart-6ba2711c-1f8f-4baa-8397-1e86c9a27506 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771728595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1771728595 |
| Directory | /workspace/25.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/25.rstmgr_sw_rst.100187255 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 537458758 ps |
| CPU time | 2.67 seconds |
| Started | Jan 24 01:06:36 PM PST 24 |
| Finished | Jan 24 01:07:39 PM PST 24 |
| Peak memory | 199636 kb |
| Host | smart-6ef59298-c66a-45a6-9b79-3c623aeb9178 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=100187255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.100187255 |
| Directory | /workspace/25.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2923068887 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 109374672 ps |
| CPU time | 0.89 seconds |
| Started | Jan 24 01:18:13 PM PST 24 |
| Finished | Jan 24 01:19:02 PM PST 24 |
| Peak memory | 199568 kb |
| Host | smart-e59a574a-d6c9-4655-8cb7-035be4e713de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2923068887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2923068887 |
| Directory | /workspace/25.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/26.rstmgr_alert_test.2731507022 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 97156701 ps |
| CPU time | 0.84 seconds |
| Started | Jan 24 01:06:46 PM PST 24 |
| Finished | Jan 24 01:07:46 PM PST 24 |
| Peak memory | 199456 kb |
| Host | smart-c77dcbee-6f6c-40ae-9911-bbb9a5d74d23 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731507022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2731507022 |
| Directory | /workspace/26.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.2597609984 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 1907204720 ps |
| CPU time | 6.92 seconds |
| Started | Jan 24 01:06:45 PM PST 24 |
| Finished | Jan 24 01:07:52 PM PST 24 |
| Peak memory | 220632 kb |
| Host | smart-e43513b0-c0f6-4044-aba9-7311747bf7cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2597609984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2597609984 |
| Directory | /workspace/26.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1711611917 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 245035791 ps |
| CPU time | 1.09 seconds |
| Started | Jan 24 01:06:48 PM PST 24 |
| Finished | Jan 24 01:07:48 PM PST 24 |
| Peak memory | 216708 kb |
| Host | smart-4caa1219-6cfc-4ef7-be75-929f29e08cb0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1711611917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1711611917 |
| Directory | /workspace/26.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/26.rstmgr_por_stretcher.1496369478 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 150400585 ps |
| CPU time | 0.8 seconds |
| Started | Jan 24 01:06:36 PM PST 24 |
| Finished | Jan 24 01:07:37 PM PST 24 |
| Peak memory | 199400 kb |
| Host | smart-0aa7e54a-7893-4e83-8fc1-654becaf86d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1496369478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.1496369478 |
| Directory | /workspace/26.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/26.rstmgr_reset.598551929 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1464788206 ps |
| CPU time | 6.03 seconds |
| Started | Jan 24 01:06:34 PM PST 24 |
| Finished | Jan 24 01:07:39 PM PST 24 |
| Peak memory | 199772 kb |
| Host | smart-b5c3508d-a4e9-4b25-a9e0-95cd54107d41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=598551929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.598551929 |
| Directory | /workspace/26.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.4016776718 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 112452678 ps |
| CPU time | 0.99 seconds |
| Started | Jan 24 01:06:47 PM PST 24 |
| Finished | Jan 24 01:07:47 PM PST 24 |
| Peak memory | 199592 kb |
| Host | smart-5c0f3e01-670b-4770-af34-1428a9a5248a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4016776718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.4016776718 |
| Directory | /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/26.rstmgr_smoke.4063851867 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 127534336 ps |
| CPU time | 1.17 seconds |
| Started | Jan 24 01:06:31 PM PST 24 |
| Finished | Jan 24 01:07:30 PM PST 24 |
| Peak memory | 199720 kb |
| Host | smart-18100ced-ad24-4b7c-a57d-e128cca214bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4063851867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.4063851867 |
| Directory | /workspace/26.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/26.rstmgr_stress_all.867992610 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 6123198713 ps |
| CPU time | 23.68 seconds |
| Started | Jan 24 01:06:45 PM PST 24 |
| Finished | Jan 24 01:08:09 PM PST 24 |
| Peak memory | 199388 kb |
| Host | smart-787a7053-b43b-4d7c-9e10-80f6198a63c2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867992610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.867992610 |
| Directory | /workspace/26.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/26.rstmgr_sw_rst.3971849659 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 452497707 ps |
| CPU time | 2.55 seconds |
| Started | Jan 24 01:06:51 PM PST 24 |
| Finished | Jan 24 01:07:54 PM PST 24 |
| Peak memory | 199624 kb |
| Host | smart-3db6ff77-05a0-4382-a605-86eb1d603088 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3971849659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.3971849659 |
| Directory | /workspace/26.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2298965225 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 94064660 ps |
| CPU time | 0.85 seconds |
| Started | Jan 24 01:06:33 PM PST 24 |
| Finished | Jan 24 01:07:34 PM PST 24 |
| Peak memory | 199560 kb |
| Host | smart-97d6e3e4-1248-44eb-8d72-ec194f216e99 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2298965225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2298965225 |
| Directory | /workspace/26.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/27.rstmgr_alert_test.2453495520 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 67539752 ps |
| CPU time | 0.79 seconds |
| Started | Jan 24 01:06:57 PM PST 24 |
| Finished | Jan 24 01:07:58 PM PST 24 |
| Peak memory | 199544 kb |
| Host | smart-37a25d0c-20ab-4aa6-b98d-2050ba3afa9c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453495520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2453495520 |
| Directory | /workspace/27.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3840941109 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 1878387717 ps |
| CPU time | 6.92 seconds |
| Started | Jan 24 01:06:51 PM PST 24 |
| Finished | Jan 24 01:07:58 PM PST 24 |
| Peak memory | 216484 kb |
| Host | smart-42031196-03cb-4b0e-b893-1fc704b9f842 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3840941109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3840941109 |
| Directory | /workspace/27.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3124409723 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 243410002 ps |
| CPU time | 1.12 seconds |
| Started | Jan 24 01:32:58 PM PST 24 |
| Finished | Jan 24 01:33:28 PM PST 24 |
| Peak memory | 216764 kb |
| Host | smart-40b49006-f67b-4b2b-9808-9a3e1a992ca6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3124409723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3124409723 |
| Directory | /workspace/27.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/27.rstmgr_por_stretcher.3543278954 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 161233389 ps |
| CPU time | 0.86 seconds |
| Started | Jan 24 01:06:40 PM PST 24 |
| Finished | Jan 24 01:07:40 PM PST 24 |
| Peak memory | 199400 kb |
| Host | smart-9182ea22-91dd-49ce-b9c5-6f6216532f1d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3543278954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.3543278954 |
| Directory | /workspace/27.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/27.rstmgr_reset.4226300167 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 1355455655 ps |
| CPU time | 4.92 seconds |
| Started | Jan 24 01:06:40 PM PST 24 |
| Finished | Jan 24 01:07:44 PM PST 24 |
| Peak memory | 199768 kb |
| Host | smart-d6c1386d-1456-405d-8d6d-fd7f5dba4bd3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4226300167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.4226300167 |
| Directory | /workspace/27.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3985798989 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 146570353 ps |
| CPU time | 1.14 seconds |
| Started | Jan 24 01:06:42 PM PST 24 |
| Finished | Jan 24 01:07:43 PM PST 24 |
| Peak memory | 199584 kb |
| Host | smart-689122bb-6f3e-4ebe-8ba0-543708c0190a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3985798989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.3985798989 |
| Directory | /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/27.rstmgr_smoke.828998216 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 265816637 ps |
| CPU time | 1.44 seconds |
| Started | Jan 24 01:06:48 PM PST 24 |
| Finished | Jan 24 01:07:48 PM PST 24 |
| Peak memory | 199732 kb |
| Host | smart-7949ea0f-2cc7-4d75-ab7f-26f86aa98862 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=828998216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.828998216 |
| Directory | /workspace/27.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/27.rstmgr_stress_all.3804395708 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 3364595500 ps |
| CPU time | 15.69 seconds |
| Started | Jan 24 01:06:42 PM PST 24 |
| Finished | Jan 24 01:07:58 PM PST 24 |
| Peak memory | 199828 kb |
| Host | smart-5a8c6eeb-dac7-4ef2-a980-aa3045ff5e34 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804395708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3804395708 |
| Directory | /workspace/27.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/27.rstmgr_sw_rst.2421007646 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 396702867 ps |
| CPU time | 2.06 seconds |
| Started | Jan 24 01:06:51 PM PST 24 |
| Finished | Jan 24 01:07:53 PM PST 24 |
| Peak memory | 199612 kb |
| Host | smart-f6ea4c2a-d686-42b3-bc16-38dfcd946a81 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2421007646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.2421007646 |
| Directory | /workspace/27.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2315433106 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 122659519 ps |
| CPU time | 0.99 seconds |
| Started | Jan 24 01:06:46 PM PST 24 |
| Finished | Jan 24 01:07:47 PM PST 24 |
| Peak memory | 199516 kb |
| Host | smart-71ab02b3-4283-4ab1-82db-6b691f0c4857 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2315433106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2315433106 |
| Directory | /workspace/27.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/28.rstmgr_alert_test.2254398815 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 67397997 ps |
| CPU time | 0.76 seconds |
| Started | Jan 24 01:06:56 PM PST 24 |
| Finished | Jan 24 01:07:58 PM PST 24 |
| Peak memory | 199496 kb |
| Host | smart-23928acf-9e6f-4789-90d5-531f02df27e3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254398815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.2254398815 |
| Directory | /workspace/28.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3806669542 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 1228119161 ps |
| CPU time | 6.09 seconds |
| Started | Jan 24 01:06:57 PM PST 24 |
| Finished | Jan 24 01:08:03 PM PST 24 |
| Peak memory | 220756 kb |
| Host | smart-f040364c-e87b-45ae-912e-8ade04bb91be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3806669542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3806669542 |
| Directory | /workspace/28.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1062673 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 243657212 ps |
| CPU time | 1.11 seconds |
| Started | Jan 24 01:06:57 PM PST 24 |
| Finished | Jan 24 01:07:58 PM PST 24 |
| Peak memory | 216588 kb |
| Host | smart-cf797859-b983-44d6-ac20-8b30e0537f7e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1062673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1062673 |
| Directory | /workspace/28.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/28.rstmgr_por_stretcher.2976357551 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 129775794 ps |
| CPU time | 0.77 seconds |
| Started | Jan 24 01:07:05 PM PST 24 |
| Finished | Jan 24 01:08:02 PM PST 24 |
| Peak memory | 199036 kb |
| Host | smart-b3d88038-8b25-411c-8693-ddff7217a745 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2976357551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2976357551 |
| Directory | /workspace/28.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/28.rstmgr_reset.557034149 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 909541893 ps |
| CPU time | 4.64 seconds |
| Started | Jan 24 02:14:01 PM PST 24 |
| Finished | Jan 24 02:14:13 PM PST 24 |
| Peak memory | 199800 kb |
| Host | smart-0aa5ca3e-1a04-4566-843b-b625c378fba6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=557034149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.557034149 |
| Directory | /workspace/28.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.1492210166 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 145733226 ps |
| CPU time | 1.07 seconds |
| Started | Jan 24 01:16:30 PM PST 24 |
| Finished | Jan 24 01:17:15 PM PST 24 |
| Peak memory | 199572 kb |
| Host | smart-1ecd6008-46d6-4528-a100-d6a3579eed56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1492210166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.1492210166 |
| Directory | /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/28.rstmgr_smoke.2473271174 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 254696429 ps |
| CPU time | 1.48 seconds |
| Started | Jan 24 01:06:57 PM PST 24 |
| Finished | Jan 24 01:07:59 PM PST 24 |
| Peak memory | 199488 kb |
| Host | smart-e54162ac-7e91-4255-bed0-bc20a31a6e28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2473271174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2473271174 |
| Directory | /workspace/28.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/28.rstmgr_stress_all.655678663 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 1286797605 ps |
| CPU time | 5.91 seconds |
| Started | Jan 24 01:36:15 PM PST 24 |
| Finished | Jan 24 01:36:55 PM PST 24 |
| Peak memory | 199796 kb |
| Host | smart-cbe7fc74-0f3d-4a24-a2ea-2dc418dc6c98 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655678663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.655678663 |
| Directory | /workspace/28.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/28.rstmgr_sw_rst.2532787960 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 113287765 ps |
| CPU time | 1.47 seconds |
| Started | Jan 24 01:07:00 PM PST 24 |
| Finished | Jan 24 01:08:00 PM PST 24 |
| Peak memory | 199640 kb |
| Host | smart-519e899a-5b67-4da5-b24c-d920c1641695 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2532787960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.2532787960 |
| Directory | /workspace/28.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.2566607930 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 268787285 ps |
| CPU time | 1.49 seconds |
| Started | Jan 24 01:07:05 PM PST 24 |
| Finished | Jan 24 01:08:03 PM PST 24 |
| Peak memory | 199564 kb |
| Host | smart-cdfd7d1a-8534-4c9e-a994-044ee0b33f45 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2566607930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2566607930 |
| Directory | /workspace/28.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/29.rstmgr_alert_test.2868749149 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 83038154 ps |
| CPU time | 0.79 seconds |
| Started | Jan 24 01:06:58 PM PST 24 |
| Finished | Jan 24 01:07:58 PM PST 24 |
| Peak memory | 199524 kb |
| Host | smart-69177566-1bdf-4808-a974-fafa24566248 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868749149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.2868749149 |
| Directory | /workspace/29.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.928206414 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 245193002 ps |
| CPU time | 1.07 seconds |
| Started | Jan 24 01:06:55 PM PST 24 |
| Finished | Jan 24 01:07:56 PM PST 24 |
| Peak memory | 216888 kb |
| Host | smart-9990fb51-95e5-4bf9-ad82-93e7b3bb4717 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=928206414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.928206414 |
| Directory | /workspace/29.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/29.rstmgr_por_stretcher.683840909 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 72452451 ps |
| CPU time | 0.69 seconds |
| Started | Jan 24 01:07:00 PM PST 24 |
| Finished | Jan 24 01:08:00 PM PST 24 |
| Peak memory | 199352 kb |
| Host | smart-f7fe1271-a7c6-4d29-9da8-4152f18db59a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=683840909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.683840909 |
| Directory | /workspace/29.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/29.rstmgr_reset.3978486523 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 1251743777 ps |
| CPU time | 5.16 seconds |
| Started | Jan 24 01:06:58 PM PST 24 |
| Finished | Jan 24 01:08:02 PM PST 24 |
| Peak memory | 199744 kb |
| Host | smart-5afae9b1-e372-4421-bf83-a58ce02f6d01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3978486523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.3978486523 |
| Directory | /workspace/29.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1583895575 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 109693808 ps |
| CPU time | 1.04 seconds |
| Started | Jan 24 01:06:57 PM PST 24 |
| Finished | Jan 24 01:07:58 PM PST 24 |
| Peak memory | 199516 kb |
| Host | smart-1903a90b-b858-422d-88d8-dbd76ac3e0ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1583895575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1583895575 |
| Directory | /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/29.rstmgr_smoke.1738725900 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 255292315 ps |
| CPU time | 1.42 seconds |
| Started | Jan 24 01:07:05 PM PST 24 |
| Finished | Jan 24 01:08:03 PM PST 24 |
| Peak memory | 199728 kb |
| Host | smart-ff7919fc-66ef-4f33-ab0a-6f246485b7bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1738725900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1738725900 |
| Directory | /workspace/29.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/29.rstmgr_stress_all.2906028187 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 4486949738 ps |
| CPU time | 15.5 seconds |
| Started | Jan 24 01:06:53 PM PST 24 |
| Finished | Jan 24 01:08:07 PM PST 24 |
| Peak memory | 199800 kb |
| Host | smart-927a96ff-b7ab-4e80-a8b6-3cf0cb95bcae |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906028187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.2906028187 |
| Directory | /workspace/29.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/29.rstmgr_sw_rst.2988862717 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 380165461 ps |
| CPU time | 2.06 seconds |
| Started | Jan 24 01:07:05 PM PST 24 |
| Finished | Jan 24 01:08:04 PM PST 24 |
| Peak memory | 199624 kb |
| Host | smart-2ab99143-6a4a-4220-b92a-4b18e58f7320 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2988862717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2988862717 |
| Directory | /workspace/29.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1625057180 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 111439987 ps |
| CPU time | 0.87 seconds |
| Started | Jan 24 01:07:00 PM PST 24 |
| Finished | Jan 24 01:08:00 PM PST 24 |
| Peak memory | 199608 kb |
| Host | smart-991503dc-84a8-4c21-ab0f-b2465d494921 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1625057180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1625057180 |
| Directory | /workspace/29.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/3.rstmgr_alert_test.324599187 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 66280980 ps |
| CPU time | 0.77 seconds |
| Started | Jan 24 01:04:14 PM PST 24 |
| Finished | Jan 24 01:04:59 PM PST 24 |
| Peak memory | 199316 kb |
| Host | smart-c72fe566-ffba-477c-9589-7a68740bbd08 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324599187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.324599187 |
| Directory | /workspace/3.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1798201425 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 2174632433 ps |
| CPU time | 8.15 seconds |
| Started | Jan 24 01:04:14 PM PST 24 |
| Finished | Jan 24 01:05:08 PM PST 24 |
| Peak memory | 216504 kb |
| Host | smart-8a697e58-ffbc-47e9-abce-c78244973331 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1798201425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1798201425 |
| Directory | /workspace/3.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2437655952 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 245076162 ps |
| CPU time | 1.22 seconds |
| Started | Jan 24 01:04:14 PM PST 24 |
| Finished | Jan 24 01:05:01 PM PST 24 |
| Peak memory | 216656 kb |
| Host | smart-49a7c5b7-db58-435a-ab54-6afdd340b798 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2437655952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2437655952 |
| Directory | /workspace/3.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/3.rstmgr_por_stretcher.3210978345 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 149278745 ps |
| CPU time | 0.87 seconds |
| Started | Jan 24 01:04:10 PM PST 24 |
| Finished | Jan 24 01:04:55 PM PST 24 |
| Peak memory | 199296 kb |
| Host | smart-4f90655b-99d0-4606-be22-f8eaf1d65f35 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3210978345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3210978345 |
| Directory | /workspace/3.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/3.rstmgr_reset.722703067 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 1739338032 ps |
| CPU time | 6.35 seconds |
| Started | Jan 24 01:04:11 PM PST 24 |
| Finished | Jan 24 01:05:01 PM PST 24 |
| Peak memory | 199788 kb |
| Host | smart-fd4b76a4-b534-4c5f-951c-5c2872c3cce8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=722703067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.722703067 |
| Directory | /workspace/3.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/3.rstmgr_sec_cm.2184684514 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 8873390235 ps |
| CPU time | 13.12 seconds |
| Started | Jan 24 01:04:13 PM PST 24 |
| Finished | Jan 24 01:05:11 PM PST 24 |
| Peak memory | 220596 kb |
| Host | smart-9ccd1ab5-be23-40d4-9372-57922c92118a |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184684514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2184684514 |
| Directory | /workspace/3.rstmgr_sec_cm/latest |
| Test location | /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2868117549 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 167659825 ps |
| CPU time | 1.08 seconds |
| Started | Jan 24 01:04:14 PM PST 24 |
| Finished | Jan 24 01:04:59 PM PST 24 |
| Peak memory | 199456 kb |
| Host | smart-3c7defc8-00cf-4aa5-985d-036ed3e015d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2868117549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2868117549 |
| Directory | /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/3.rstmgr_smoke.2215125979 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 122367511 ps |
| CPU time | 1.14 seconds |
| Started | Jan 24 01:04:12 PM PST 24 |
| Finished | Jan 24 01:04:58 PM PST 24 |
| Peak memory | 199200 kb |
| Host | smart-5f64d35a-e068-4b1b-9957-ea3266914f37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2215125979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2215125979 |
| Directory | /workspace/3.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/3.rstmgr_stress_all.2911254171 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 7369836579 ps |
| CPU time | 30 seconds |
| Started | Jan 24 01:04:22 PM PST 24 |
| Finished | Jan 24 01:05:36 PM PST 24 |
| Peak memory | 199804 kb |
| Host | smart-e6255bb1-4798-44a4-af21-f32b6b974f57 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911254171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.2911254171 |
| Directory | /workspace/3.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/3.rstmgr_sw_rst.2530843270 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 369154459 ps |
| CPU time | 2.3 seconds |
| Started | Jan 24 01:04:13 PM PST 24 |
| Finished | Jan 24 01:05:00 PM PST 24 |
| Peak memory | 199576 kb |
| Host | smart-377bb42b-3401-4533-acbf-b13c84bbe0da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2530843270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2530843270 |
| Directory | /workspace/3.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.4050488492 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 119869144 ps |
| CPU time | 0.92 seconds |
| Started | Jan 24 01:04:12 PM PST 24 |
| Finished | Jan 24 01:04:57 PM PST 24 |
| Peak memory | 199460 kb |
| Host | smart-f4189427-91e2-4ffc-8a3b-5f159208789b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4050488492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.4050488492 |
| Directory | /workspace/3.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/30.rstmgr_alert_test.501226840 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 77166244 ps |
| CPU time | 0.8 seconds |
| Started | Jan 24 01:07:05 PM PST 24 |
| Finished | Jan 24 01:08:02 PM PST 24 |
| Peak memory | 199224 kb |
| Host | smart-b7ac097f-cd29-47f4-a1c7-59686c1bda61 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501226840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.501226840 |
| Directory | /workspace/30.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.3844914657 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 1221576784 ps |
| CPU time | 5.29 seconds |
| Started | Jan 24 01:07:00 PM PST 24 |
| Finished | Jan 24 01:08:04 PM PST 24 |
| Peak memory | 217632 kb |
| Host | smart-0d4a2c61-6531-4486-b40b-37796b8da8e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3844914657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.3844914657 |
| Directory | /workspace/30.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3290859959 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 243982657 ps |
| CPU time | 1.21 seconds |
| Started | Jan 24 01:19:55 PM PST 24 |
| Finished | Jan 24 01:20:58 PM PST 24 |
| Peak memory | 216708 kb |
| Host | smart-0460e7f5-c7cf-4407-928e-5ce599e9482d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3290859959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3290859959 |
| Directory | /workspace/30.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/30.rstmgr_por_stretcher.2447051110 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 144291134 ps |
| CPU time | 0.79 seconds |
| Started | Jan 24 02:41:11 PM PST 24 |
| Finished | Jan 24 02:41:26 PM PST 24 |
| Peak memory | 199388 kb |
| Host | smart-f2d68d93-312e-4e80-83a1-e9d957639662 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2447051110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2447051110 |
| Directory | /workspace/30.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/30.rstmgr_reset.1500959659 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 786193953 ps |
| CPU time | 3.77 seconds |
| Started | Jan 24 01:06:53 PM PST 24 |
| Finished | Jan 24 01:07:55 PM PST 24 |
| Peak memory | 199712 kb |
| Host | smart-011f026c-c10b-47ff-be1d-4e9847c9478c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1500959659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.1500959659 |
| Directory | /workspace/30.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.357192936 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 98706103 ps |
| CPU time | 0.95 seconds |
| Started | Jan 24 01:06:56 PM PST 24 |
| Finished | Jan 24 01:07:58 PM PST 24 |
| Peak memory | 199552 kb |
| Host | smart-df773ee1-547d-4999-86ba-501b3c033e8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=357192936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.357192936 |
| Directory | /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/30.rstmgr_smoke.2954355325 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 115658999 ps |
| CPU time | 1.19 seconds |
| Started | Jan 24 01:07:05 PM PST 24 |
| Finished | Jan 24 01:08:03 PM PST 24 |
| Peak memory | 199748 kb |
| Host | smart-bb2d93f0-8180-4baa-bb80-d1dfe6c16230 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2954355325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2954355325 |
| Directory | /workspace/30.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/30.rstmgr_stress_all.612659417 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 2298504627 ps |
| CPU time | 8.02 seconds |
| Started | Jan 24 01:38:29 PM PST 24 |
| Finished | Jan 24 01:39:01 PM PST 24 |
| Peak memory | 199836 kb |
| Host | smart-a59429f2-2e6e-4890-9bee-ed2414d93e41 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612659417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.612659417 |
| Directory | /workspace/30.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/30.rstmgr_sw_rst.3816591056 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 120608913 ps |
| CPU time | 1.5 seconds |
| Started | Jan 24 01:07:05 PM PST 24 |
| Finished | Jan 24 01:08:03 PM PST 24 |
| Peak memory | 199644 kb |
| Host | smart-8682a0a9-ffe4-4d47-b46b-229b957351ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3816591056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.3816591056 |
| Directory | /workspace/30.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.1459604891 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 247788387 ps |
| CPU time | 1.35 seconds |
| Started | Jan 24 01:06:57 PM PST 24 |
| Finished | Jan 24 01:07:58 PM PST 24 |
| Peak memory | 199584 kb |
| Host | smart-91aee02a-6ed8-40d5-9d9d-e2a10a4e476b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1459604891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.1459604891 |
| Directory | /workspace/30.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/31.rstmgr_alert_test.3932869189 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 73832028 ps |
| CPU time | 0.78 seconds |
| Started | Jan 24 01:06:59 PM PST 24 |
| Finished | Jan 24 01:07:58 PM PST 24 |
| Peak memory | 199396 kb |
| Host | smart-ea7b3600-a2b4-4a37-a5f1-417a810db102 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932869189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.3932869189 |
| Directory | /workspace/31.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1231545326 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 1894373733 ps |
| CPU time | 7.09 seconds |
| Started | Jan 24 01:07:12 PM PST 24 |
| Finished | Jan 24 01:08:18 PM PST 24 |
| Peak memory | 217000 kb |
| Host | smart-4a34a3a8-67e3-46df-b448-6a3434196f04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1231545326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1231545326 |
| Directory | /workspace/31.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.2891077309 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 246443051 ps |
| CPU time | 1.04 seconds |
| Started | Jan 24 01:07:03 PM PST 24 |
| Finished | Jan 24 01:08:02 PM PST 24 |
| Peak memory | 216904 kb |
| Host | smart-21adafc2-1372-4644-891f-6092efaf3241 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2891077309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.2891077309 |
| Directory | /workspace/31.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/31.rstmgr_por_stretcher.3254735354 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 220831451 ps |
| CPU time | 0.94 seconds |
| Started | Jan 24 01:07:12 PM PST 24 |
| Finished | Jan 24 01:08:12 PM PST 24 |
| Peak memory | 199332 kb |
| Host | smart-a6b1321f-1712-4929-bfce-c850508564d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3254735354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.3254735354 |
| Directory | /workspace/31.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/31.rstmgr_reset.753542419 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1461911754 ps |
| CPU time | 5.72 seconds |
| Started | Jan 24 01:07:11 PM PST 24 |
| Finished | Jan 24 01:08:15 PM PST 24 |
| Peak memory | 199728 kb |
| Host | smart-7d87e4b5-0ce6-40fa-8b56-e07a441e22a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=753542419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.753542419 |
| Directory | /workspace/31.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.1169371204 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 100615797 ps |
| CPU time | 0.94 seconds |
| Started | Jan 24 01:07:03 PM PST 24 |
| Finished | Jan 24 01:08:02 PM PST 24 |
| Peak memory | 199592 kb |
| Host | smart-c16b5833-83bf-4285-a989-3eae0dab120d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1169371204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.1169371204 |
| Directory | /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/31.rstmgr_smoke.4128938753 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 114278657 ps |
| CPU time | 1.18 seconds |
| Started | Jan 24 01:07:01 PM PST 24 |
| Finished | Jan 24 01:08:00 PM PST 24 |
| Peak memory | 199784 kb |
| Host | smart-c796abf7-e9d7-451f-89a9-48b2bfbf7da4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4128938753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.4128938753 |
| Directory | /workspace/31.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/31.rstmgr_stress_all.459386430 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 16001699785 ps |
| CPU time | 53.51 seconds |
| Started | Jan 24 01:07:08 PM PST 24 |
| Finished | Jan 24 01:08:59 PM PST 24 |
| Peak memory | 199780 kb |
| Host | smart-f191f289-ec55-46aa-aad2-70b065eb6b6c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459386430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.459386430 |
| Directory | /workspace/31.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/31.rstmgr_sw_rst.1511156452 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 129570907 ps |
| CPU time | 1.6 seconds |
| Started | Jan 24 04:01:09 PM PST 24 |
| Finished | Jan 24 04:01:13 PM PST 24 |
| Peak memory | 199716 kb |
| Host | smart-65e3ead7-7e85-45fe-93a9-726504e4903b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1511156452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1511156452 |
| Directory | /workspace/31.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2992714004 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 145116194 ps |
| CPU time | 1.11 seconds |
| Started | Jan 24 01:07:00 PM PST 24 |
| Finished | Jan 24 01:07:59 PM PST 24 |
| Peak memory | 199552 kb |
| Host | smart-ca693dd1-2a59-4251-b0ac-d2d3e2d3a288 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2992714004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2992714004 |
| Directory | /workspace/31.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/32.rstmgr_alert_test.3480532402 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 67941281 ps |
| CPU time | 0.76 seconds |
| Started | Jan 24 01:07:13 PM PST 24 |
| Finished | Jan 24 01:08:12 PM PST 24 |
| Peak memory | 199552 kb |
| Host | smart-3d178c86-f9a0-4604-ac83-59f279f25e97 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480532402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.3480532402 |
| Directory | /workspace/32.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2163178224 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 1882462201 ps |
| CPU time | 6.97 seconds |
| Started | Jan 24 01:07:13 PM PST 24 |
| Finished | Jan 24 01:08:18 PM PST 24 |
| Peak memory | 217072 kb |
| Host | smart-dd4f39cf-5c0c-48f7-a90d-c10a721a798d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2163178224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2163178224 |
| Directory | /workspace/32.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.3196825008 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 244900431 ps |
| CPU time | 1.15 seconds |
| Started | Jan 24 01:07:13 PM PST 24 |
| Finished | Jan 24 01:08:12 PM PST 24 |
| Peak memory | 216896 kb |
| Host | smart-88752504-505a-4451-80e3-73d93a871073 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3196825008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.3196825008 |
| Directory | /workspace/32.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/32.rstmgr_por_stretcher.1891886834 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 102744369 ps |
| CPU time | 0.8 seconds |
| Started | Jan 24 01:07:15 PM PST 24 |
| Finished | Jan 24 01:08:13 PM PST 24 |
| Peak memory | 199368 kb |
| Host | smart-038a4625-65b4-41af-b147-9034f534e2ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1891886834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1891886834 |
| Directory | /workspace/32.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/32.rstmgr_reset.3509968350 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 1401207262 ps |
| CPU time | 5.48 seconds |
| Started | Jan 24 01:07:17 PM PST 24 |
| Finished | Jan 24 01:08:19 PM PST 24 |
| Peak memory | 199748 kb |
| Host | smart-ae13517a-716a-42c2-bf88-befca7540ac3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3509968350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.3509968350 |
| Directory | /workspace/32.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1432596334 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 106574453 ps |
| CPU time | 0.95 seconds |
| Started | Jan 24 01:07:18 PM PST 24 |
| Finished | Jan 24 01:08:15 PM PST 24 |
| Peak memory | 199588 kb |
| Host | smart-c7a98d61-55ac-4e39-9180-10296e3f210f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1432596334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1432596334 |
| Directory | /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/32.rstmgr_smoke.2211805800 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 247701104 ps |
| CPU time | 1.41 seconds |
| Started | Jan 24 01:07:18 PM PST 24 |
| Finished | Jan 24 01:08:15 PM PST 24 |
| Peak memory | 199784 kb |
| Host | smart-640d5a9d-08d0-4a2a-bb59-c4a001bdc020 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2211805800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2211805800 |
| Directory | /workspace/32.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/32.rstmgr_stress_all.263385092 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 13868508474 ps |
| CPU time | 45.64 seconds |
| Started | Jan 24 01:07:21 PM PST 24 |
| Finished | Jan 24 01:09:03 PM PST 24 |
| Peak memory | 199776 kb |
| Host | smart-877e7eed-7c99-4e99-99c2-344770359d01 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263385092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.263385092 |
| Directory | /workspace/32.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/32.rstmgr_sw_rst.1107693379 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 132582122 ps |
| CPU time | 1.5 seconds |
| Started | Jan 24 01:07:17 PM PST 24 |
| Finished | Jan 24 01:08:15 PM PST 24 |
| Peak memory | 199624 kb |
| Host | smart-f0e5f4e9-1104-41c2-b41f-d398f636230b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1107693379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.1107693379 |
| Directory | /workspace/32.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.1116602958 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 161866238 ps |
| CPU time | 1.39 seconds |
| Started | Jan 24 01:07:14 PM PST 24 |
| Finished | Jan 24 01:08:13 PM PST 24 |
| Peak memory | 199768 kb |
| Host | smart-ed1a75f3-8bee-4207-aab2-cfb590704296 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1116602958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.1116602958 |
| Directory | /workspace/32.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/33.rstmgr_alert_test.3652552078 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 68870266 ps |
| CPU time | 0.72 seconds |
| Started | Jan 24 01:07:29 PM PST 24 |
| Finished | Jan 24 01:08:27 PM PST 24 |
| Peak memory | 199540 kb |
| Host | smart-7735cd07-8290-41b9-b21f-8f04f8cd8544 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652552078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.3652552078 |
| Directory | /workspace/33.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2637675775 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 1915255502 ps |
| CPU time | 7.5 seconds |
| Started | Jan 24 01:07:29 PM PST 24 |
| Finished | Jan 24 01:08:34 PM PST 24 |
| Peak memory | 220984 kb |
| Host | smart-6a4d669e-fb38-4dd1-bc30-23df5daa510a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2637675775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2637675775 |
| Directory | /workspace/33.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2859981874 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 243493498 ps |
| CPU time | 1.06 seconds |
| Started | Jan 24 01:07:32 PM PST 24 |
| Finished | Jan 24 01:08:30 PM PST 24 |
| Peak memory | 216804 kb |
| Host | smart-01581caa-e221-43c2-9dc6-4c30c33fe5b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2859981874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2859981874 |
| Directory | /workspace/33.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/33.rstmgr_por_stretcher.3630383037 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 206152723 ps |
| CPU time | 0.94 seconds |
| Started | Jan 24 01:07:16 PM PST 24 |
| Finished | Jan 24 01:08:14 PM PST 24 |
| Peak memory | 199384 kb |
| Host | smart-5d7e1f73-b466-42d1-b24d-cd7682e7acab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3630383037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.3630383037 |
| Directory | /workspace/33.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/33.rstmgr_reset.822494363 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1443338080 ps |
| CPU time | 5.53 seconds |
| Started | Jan 24 01:07:20 PM PST 24 |
| Finished | Jan 24 01:08:23 PM PST 24 |
| Peak memory | 199780 kb |
| Host | smart-728ced39-24bc-4c30-8ed9-aac201213b88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=822494363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.822494363 |
| Directory | /workspace/33.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1315248389 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 178405066 ps |
| CPU time | 1.13 seconds |
| Started | Jan 24 01:07:28 PM PST 24 |
| Finished | Jan 24 01:08:27 PM PST 24 |
| Peak memory | 199620 kb |
| Host | smart-69e7d0e6-4c4b-406c-b8e6-991a7831fa3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1315248389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.1315248389 |
| Directory | /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/33.rstmgr_smoke.2704855898 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 251439843 ps |
| CPU time | 1.49 seconds |
| Started | Jan 24 01:07:15 PM PST 24 |
| Finished | Jan 24 01:08:15 PM PST 24 |
| Peak memory | 199736 kb |
| Host | smart-7bfe312c-939b-45fb-8981-96e0092031fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2704855898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2704855898 |
| Directory | /workspace/33.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/33.rstmgr_stress_all.283139858 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 1386497906 ps |
| CPU time | 5.27 seconds |
| Started | Jan 24 01:07:29 PM PST 24 |
| Finished | Jan 24 01:08:32 PM PST 24 |
| Peak memory | 199752 kb |
| Host | smart-338e1964-33bc-4b4f-94ca-ff0299eec226 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283139858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.283139858 |
| Directory | /workspace/33.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/33.rstmgr_sw_rst.440337585 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 114944314 ps |
| CPU time | 1.77 seconds |
| Started | Jan 24 01:07:32 PM PST 24 |
| Finished | Jan 24 01:08:30 PM PST 24 |
| Peak memory | 199432 kb |
| Host | smart-f908065f-e43e-4170-8a96-96517b9074c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=440337585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.440337585 |
| Directory | /workspace/33.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.462451256 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 80410091 ps |
| CPU time | 0.79 seconds |
| Started | Jan 24 01:07:21 PM PST 24 |
| Finished | Jan 24 01:08:18 PM PST 24 |
| Peak memory | 199504 kb |
| Host | smart-c2cb92b8-6245-47d5-b91d-53c4aee9f2f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=462451256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.462451256 |
| Directory | /workspace/33.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/34.rstmgr_alert_test.1812225948 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 63616064 ps |
| CPU time | 0.73 seconds |
| Started | Jan 24 01:07:49 PM PST 24 |
| Finished | Jan 24 01:08:39 PM PST 24 |
| Peak memory | 199508 kb |
| Host | smart-9423d95a-a258-4024-b489-21441bf65229 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812225948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.1812225948 |
| Directory | /workspace/34.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3526994098 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 245040916 ps |
| CPU time | 1.09 seconds |
| Started | Jan 24 01:07:46 PM PST 24 |
| Finished | Jan 24 01:08:38 PM PST 24 |
| Peak memory | 216820 kb |
| Host | smart-712acf89-a849-490a-9465-c1810f7c12b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3526994098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3526994098 |
| Directory | /workspace/34.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/34.rstmgr_por_stretcher.2885329071 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 104105695 ps |
| CPU time | 0.76 seconds |
| Started | Jan 24 01:07:28 PM PST 24 |
| Finished | Jan 24 01:08:27 PM PST 24 |
| Peak memory | 199368 kb |
| Host | smart-e06350f3-89ec-44b8-ae33-cc69d0595acf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2885329071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2885329071 |
| Directory | /workspace/34.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/34.rstmgr_reset.4224209893 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 992214378 ps |
| CPU time | 4.61 seconds |
| Started | Jan 24 01:07:26 PM PST 24 |
| Finished | Jan 24 01:08:27 PM PST 24 |
| Peak memory | 199804 kb |
| Host | smart-73fee720-d87b-4e06-a613-0ff16448a00d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4224209893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.4224209893 |
| Directory | /workspace/34.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1748412128 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 109576610 ps |
| CPU time | 0.99 seconds |
| Started | Jan 24 01:07:32 PM PST 24 |
| Finished | Jan 24 01:08:30 PM PST 24 |
| Peak memory | 199524 kb |
| Host | smart-ba5100ce-c52c-46a4-8b62-0404dab31949 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1748412128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1748412128 |
| Directory | /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/34.rstmgr_smoke.3647382656 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 115250036 ps |
| CPU time | 1.14 seconds |
| Started | Jan 24 01:07:29 PM PST 24 |
| Finished | Jan 24 01:08:28 PM PST 24 |
| Peak memory | 199676 kb |
| Host | smart-628fb7d5-2f9c-49f0-bbec-e3533c9b0b27 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3647382656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.3647382656 |
| Directory | /workspace/34.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/34.rstmgr_stress_all.2186335426 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 218449555 ps |
| CPU time | 1.21 seconds |
| Started | Jan 24 01:07:49 PM PST 24 |
| Finished | Jan 24 01:08:40 PM PST 24 |
| Peak memory | 199572 kb |
| Host | smart-062445eb-4d4d-4810-946c-955eb813e96f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186335426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.2186335426 |
| Directory | /workspace/34.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/34.rstmgr_sw_rst.1459270857 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 139024664 ps |
| CPU time | 1.82 seconds |
| Started | Jan 24 01:45:10 PM PST 24 |
| Finished | Jan 24 01:45:23 PM PST 24 |
| Peak memory | 199696 kb |
| Host | smart-822f9c78-2fcd-4ce9-b4e2-3908975002f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1459270857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.1459270857 |
| Directory | /workspace/34.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.2819461732 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 91621769 ps |
| CPU time | 0.87 seconds |
| Started | Jan 24 01:07:32 PM PST 24 |
| Finished | Jan 24 01:08:29 PM PST 24 |
| Peak memory | 199316 kb |
| Host | smart-cc60d999-f87d-4958-8364-54d9bc2ef03e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2819461732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.2819461732 |
| Directory | /workspace/34.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/35.rstmgr_alert_test.3112143675 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 77497852 ps |
| CPU time | 0.81 seconds |
| Started | Jan 24 01:07:53 PM PST 24 |
| Finished | Jan 24 01:08:40 PM PST 24 |
| Peak memory | 199580 kb |
| Host | smart-dae6497d-3bfa-4a7c-9143-5df2a3aca21a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112143675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3112143675 |
| Directory | /workspace/35.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1056782454 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 1895212860 ps |
| CPU time | 7.27 seconds |
| Started | Jan 24 01:07:52 PM PST 24 |
| Finished | Jan 24 01:08:47 PM PST 24 |
| Peak memory | 221140 kb |
| Host | smart-890f4773-a619-4427-a093-f687328b4b62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1056782454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1056782454 |
| Directory | /workspace/35.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.739336687 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 244989802 ps |
| CPU time | 1.14 seconds |
| Started | Jan 24 01:07:47 PM PST 24 |
| Finished | Jan 24 01:08:38 PM PST 24 |
| Peak memory | 216892 kb |
| Host | smart-e028ef03-bb0c-47c7-ae39-f552b1f7b0ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=739336687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.739336687 |
| Directory | /workspace/35.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/35.rstmgr_por_stretcher.271883165 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 227406011 ps |
| CPU time | 0.9 seconds |
| Started | Jan 24 01:07:44 PM PST 24 |
| Finished | Jan 24 01:08:36 PM PST 24 |
| Peak memory | 199348 kb |
| Host | smart-8bd50399-2e40-4047-bf27-55dc00ccbff5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=271883165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.271883165 |
| Directory | /workspace/35.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/35.rstmgr_reset.3768026452 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 1770796774 ps |
| CPU time | 6.59 seconds |
| Started | Jan 24 01:07:49 PM PST 24 |
| Finished | Jan 24 01:08:45 PM PST 24 |
| Peak memory | 199816 kb |
| Host | smart-7cac7123-7350-4254-9c94-697c04dbbf9a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3768026452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3768026452 |
| Directory | /workspace/35.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3057179496 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 97155442 ps |
| CPU time | 0.97 seconds |
| Started | Jan 24 01:07:44 PM PST 24 |
| Finished | Jan 24 01:08:37 PM PST 24 |
| Peak memory | 199568 kb |
| Host | smart-d28d661a-298a-4184-81d5-772821c45627 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3057179496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3057179496 |
| Directory | /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/35.rstmgr_smoke.713064233 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 241160027 ps |
| CPU time | 1.48 seconds |
| Started | Jan 24 01:07:49 PM PST 24 |
| Finished | Jan 24 01:08:40 PM PST 24 |
| Peak memory | 199776 kb |
| Host | smart-17406778-49b4-4a72-a933-5b1d1458a185 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=713064233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.713064233 |
| Directory | /workspace/35.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/35.rstmgr_stress_all.2203395831 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 11756797817 ps |
| CPU time | 39.66 seconds |
| Started | Jan 24 01:07:53 PM PST 24 |
| Finished | Jan 24 01:09:19 PM PST 24 |
| Peak memory | 199904 kb |
| Host | smart-33347933-8cac-40cc-b311-462e793893c1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203395831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2203395831 |
| Directory | /workspace/35.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/35.rstmgr_sw_rst.2813403471 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 332363239 ps |
| CPU time | 2.06 seconds |
| Started | Jan 24 01:07:46 PM PST 24 |
| Finished | Jan 24 01:08:39 PM PST 24 |
| Peak memory | 199620 kb |
| Host | smart-0a705379-9370-46dd-a8b6-d15fb9823e6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2813403471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.2813403471 |
| Directory | /workspace/35.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2078845745 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 110611162 ps |
| CPU time | 0.99 seconds |
| Started | Jan 24 01:07:49 PM PST 24 |
| Finished | Jan 24 01:08:39 PM PST 24 |
| Peak memory | 199600 kb |
| Host | smart-888cdc0b-df22-4dd5-9584-a4bc32e57d5b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2078845745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2078845745 |
| Directory | /workspace/35.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/36.rstmgr_alert_test.1488606019 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 86204093 ps |
| CPU time | 0.78 seconds |
| Started | Jan 24 01:08:10 PM PST 24 |
| Finished | Jan 24 01:08:50 PM PST 24 |
| Peak memory | 199456 kb |
| Host | smart-345ad92f-3213-478e-98c1-184caa7e2c98 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488606019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.1488606019 |
| Directory | /workspace/36.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2923723905 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1884371940 ps |
| CPU time | 6.69 seconds |
| Started | Jan 24 01:08:03 PM PST 24 |
| Finished | Jan 24 01:08:50 PM PST 24 |
| Peak memory | 217652 kb |
| Host | smart-53ef05af-5fe9-4980-9071-e06f2b796d53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2923723905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2923723905 |
| Directory | /workspace/36.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3024796556 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 244413803 ps |
| CPU time | 1.16 seconds |
| Started | Jan 24 01:08:02 PM PST 24 |
| Finished | Jan 24 01:08:45 PM PST 24 |
| Peak memory | 216420 kb |
| Host | smart-e8711411-88b2-48ca-ad24-c27e2b97c7e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3024796556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3024796556 |
| Directory | /workspace/36.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/36.rstmgr_por_stretcher.471178292 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 163243558 ps |
| CPU time | 0.96 seconds |
| Started | Jan 24 01:07:50 PM PST 24 |
| Finished | Jan 24 01:08:40 PM PST 24 |
| Peak memory | 199396 kb |
| Host | smart-cad0826f-b6b6-4123-b29c-0869ee57eeb0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=471178292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.471178292 |
| Directory | /workspace/36.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/36.rstmgr_reset.3504400064 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 818582194 ps |
| CPU time | 4.02 seconds |
| Started | Jan 24 01:07:50 PM PST 24 |
| Finished | Jan 24 01:08:43 PM PST 24 |
| Peak memory | 199796 kb |
| Host | smart-97598834-7929-4351-8e1f-221436888931 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3504400064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3504400064 |
| Directory | /workspace/36.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.4263086301 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 175691992 ps |
| CPU time | 1.14 seconds |
| Started | Jan 24 01:08:02 PM PST 24 |
| Finished | Jan 24 01:08:45 PM PST 24 |
| Peak memory | 198852 kb |
| Host | smart-28cd0e89-a015-4edb-b866-c831d1a5d95b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4263086301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.4263086301 |
| Directory | /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/36.rstmgr_smoke.660142247 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 192991579 ps |
| CPU time | 1.33 seconds |
| Started | Jan 24 01:07:46 PM PST 24 |
| Finished | Jan 24 01:08:39 PM PST 24 |
| Peak memory | 199728 kb |
| Host | smart-bd52ee47-0c20-4796-86fa-5e2b5710ee1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=660142247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.660142247 |
| Directory | /workspace/36.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/36.rstmgr_stress_all.1453470433 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 12186416686 ps |
| CPU time | 42.62 seconds |
| Started | Jan 24 01:08:01 PM PST 24 |
| Finished | Jan 24 01:09:25 PM PST 24 |
| Peak memory | 199852 kb |
| Host | smart-dc559c40-0157-413f-bf1e-cca5ae84f455 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453470433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1453470433 |
| Directory | /workspace/36.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/36.rstmgr_sw_rst.3475364608 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 341862974 ps |
| CPU time | 2.21 seconds |
| Started | Jan 24 01:08:04 PM PST 24 |
| Finished | Jan 24 01:08:49 PM PST 24 |
| Peak memory | 199588 kb |
| Host | smart-e93b913a-e335-446f-a6a3-d96deda88af8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3475364608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3475364608 |
| Directory | /workspace/36.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.864482875 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 115040095 ps |
| CPU time | 1.05 seconds |
| Started | Jan 24 01:07:53 PM PST 24 |
| Finished | Jan 24 01:08:41 PM PST 24 |
| Peak memory | 199628 kb |
| Host | smart-8317dcd7-3dd7-43a3-8948-338a17633c78 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=864482875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.864482875 |
| Directory | /workspace/36.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/37.rstmgr_alert_test.3651081852 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 77956897 ps |
| CPU time | 0.78 seconds |
| Started | Jan 24 01:08:09 PM PST 24 |
| Finished | Jan 24 01:08:50 PM PST 24 |
| Peak memory | 199384 kb |
| Host | smart-a4c2652d-0637-4035-8a32-68e257bc5436 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651081852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.3651081852 |
| Directory | /workspace/37.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3251136660 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 1222919079 ps |
| CPU time | 5.71 seconds |
| Started | Jan 24 01:08:09 PM PST 24 |
| Finished | Jan 24 01:08:55 PM PST 24 |
| Peak memory | 216324 kb |
| Host | smart-21672133-f885-43b9-963c-55252c1501d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3251136660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3251136660 |
| Directory | /workspace/37.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1041441733 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 244411617 ps |
| CPU time | 1.1 seconds |
| Started | Jan 24 01:15:16 PM PST 24 |
| Finished | Jan 24 01:15:58 PM PST 24 |
| Peak memory | 216744 kb |
| Host | smart-312bc507-724d-4b81-8bf9-12d9a354bc87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1041441733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1041441733 |
| Directory | /workspace/37.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/37.rstmgr_por_stretcher.900345865 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 259071108 ps |
| CPU time | 0.98 seconds |
| Started | Jan 24 01:08:10 PM PST 24 |
| Finished | Jan 24 01:08:50 PM PST 24 |
| Peak memory | 199320 kb |
| Host | smart-969fc8e5-0828-4dfb-8133-0ed9317fd764 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=900345865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.900345865 |
| Directory | /workspace/37.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/37.rstmgr_reset.1406271468 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 1770969858 ps |
| CPU time | 6.34 seconds |
| Started | Jan 24 01:08:00 PM PST 24 |
| Finished | Jan 24 01:08:49 PM PST 24 |
| Peak memory | 199764 kb |
| Host | smart-bb03287f-5e0b-43df-a74b-9a0e3944245e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1406271468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1406271468 |
| Directory | /workspace/37.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2662632666 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 158540170 ps |
| CPU time | 1.1 seconds |
| Started | Jan 24 01:07:59 PM PST 24 |
| Finished | Jan 24 01:08:43 PM PST 24 |
| Peak memory | 199552 kb |
| Host | smart-2cda4255-2dcc-4b95-9399-1d6870826f06 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2662632666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.2662632666 |
| Directory | /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/37.rstmgr_smoke.403486239 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 265491257 ps |
| CPU time | 1.46 seconds |
| Started | Jan 24 01:36:00 PM PST 24 |
| Finished | Jan 24 01:36:31 PM PST 24 |
| Peak memory | 199768 kb |
| Host | smart-e57fbb16-93e8-4858-93aa-21a7bd0badcd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=403486239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.403486239 |
| Directory | /workspace/37.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/37.rstmgr_stress_all.1378690188 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 4148940409 ps |
| CPU time | 19.71 seconds |
| Started | Jan 24 01:08:10 PM PST 24 |
| Finished | Jan 24 01:09:09 PM PST 24 |
| Peak memory | 199816 kb |
| Host | smart-5daa7099-5cfa-4d6c-8380-95f527cf86d7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378690188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.1378690188 |
| Directory | /workspace/37.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/37.rstmgr_sw_rst.1246652733 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 350367340 ps |
| CPU time | 1.9 seconds |
| Started | Jan 24 01:08:05 PM PST 24 |
| Finished | Jan 24 01:08:48 PM PST 24 |
| Peak memory | 199576 kb |
| Host | smart-d8787113-4683-4a3f-92b9-52d8b325ef53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1246652733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.1246652733 |
| Directory | /workspace/37.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.69253749 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 127826705 ps |
| CPU time | 0.98 seconds |
| Started | Jan 24 01:08:05 PM PST 24 |
| Finished | Jan 24 01:08:47 PM PST 24 |
| Peak memory | 199524 kb |
| Host | smart-6d01ee33-da7a-4412-a877-91d718a57523 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=69253749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.69253749 |
| Directory | /workspace/37.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/38.rstmgr_alert_test.4200551129 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 75317318 ps |
| CPU time | 0.76 seconds |
| Started | Jan 24 01:08:17 PM PST 24 |
| Finished | Jan 24 01:08:56 PM PST 24 |
| Peak memory | 199496 kb |
| Host | smart-56982f82-46cf-4d3c-bf72-c9ba06925c3d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200551129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.4200551129 |
| Directory | /workspace/38.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.1761744013 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1902461787 ps |
| CPU time | 7.74 seconds |
| Started | Jan 24 01:08:10 PM PST 24 |
| Finished | Jan 24 01:08:57 PM PST 24 |
| Peak memory | 216864 kb |
| Host | smart-4a54f3ff-dbac-4a18-ae6d-058ba8351afb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1761744013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1761744013 |
| Directory | /workspace/38.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.3226499488 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 243791271 ps |
| CPU time | 1.11 seconds |
| Started | Jan 24 01:08:09 PM PST 24 |
| Finished | Jan 24 01:08:50 PM PST 24 |
| Peak memory | 216748 kb |
| Host | smart-0fb80576-ac32-44d0-bcff-d35d9a8591ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3226499488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.3226499488 |
| Directory | /workspace/38.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/38.rstmgr_por_stretcher.993603571 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 124480973 ps |
| CPU time | 0.78 seconds |
| Started | Jan 24 01:08:10 PM PST 24 |
| Finished | Jan 24 01:08:50 PM PST 24 |
| Peak memory | 199280 kb |
| Host | smart-9ddb2c7e-d00e-4cd0-8f0b-6d43c2914280 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=993603571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.993603571 |
| Directory | /workspace/38.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/38.rstmgr_reset.3934560175 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 1279381002 ps |
| CPU time | 4.94 seconds |
| Started | Jan 24 01:08:10 PM PST 24 |
| Finished | Jan 24 01:08:54 PM PST 24 |
| Peak memory | 199772 kb |
| Host | smart-5dafdd95-9364-4b32-a954-248c169418d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3934560175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3934560175 |
| Directory | /workspace/38.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.2389310081 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 154110690 ps |
| CPU time | 1.06 seconds |
| Started | Jan 24 01:35:42 PM PST 24 |
| Finished | Jan 24 01:36:11 PM PST 24 |
| Peak memory | 199572 kb |
| Host | smart-cbc5d482-c83e-4b85-9d25-8ff50748215a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2389310081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.2389310081 |
| Directory | /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/38.rstmgr_smoke.1200534262 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 233192793 ps |
| CPU time | 1.42 seconds |
| Started | Jan 24 01:08:04 PM PST 24 |
| Finished | Jan 24 01:08:48 PM PST 24 |
| Peak memory | 199676 kb |
| Host | smart-787db050-8254-4103-b511-49da87153d3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1200534262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.1200534262 |
| Directory | /workspace/38.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/38.rstmgr_stress_all.3099431572 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 14101652371 ps |
| CPU time | 56.5 seconds |
| Started | Jan 24 01:08:09 PM PST 24 |
| Finished | Jan 24 01:09:45 PM PST 24 |
| Peak memory | 199848 kb |
| Host | smart-9ebd0a12-1fcf-4b12-945a-960d8edb800b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099431572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3099431572 |
| Directory | /workspace/38.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/38.rstmgr_sw_rst.3843020259 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 510741177 ps |
| CPU time | 2.9 seconds |
| Started | Jan 24 01:56:28 PM PST 24 |
| Finished | Jan 24 01:56:36 PM PST 24 |
| Peak memory | 199632 kb |
| Host | smart-9e458bc3-5fcd-41c2-b375-e3fb3399efc4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3843020259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.3843020259 |
| Directory | /workspace/38.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2054899372 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 281026264 ps |
| CPU time | 1.51 seconds |
| Started | Jan 24 01:08:09 PM PST 24 |
| Finished | Jan 24 01:08:50 PM PST 24 |
| Peak memory | 199560 kb |
| Host | smart-d384a8c3-541f-46ea-acf7-e63ec0b3bbeb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2054899372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2054899372 |
| Directory | /workspace/38.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/39.rstmgr_alert_test.317824874 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 64829379 ps |
| CPU time | 0.77 seconds |
| Started | Jan 24 01:12:22 PM PST 24 |
| Finished | Jan 24 01:13:12 PM PST 24 |
| Peak memory | 199508 kb |
| Host | smart-5b0811fc-e1a6-41c1-99db-78768e4a7434 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317824874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.317824874 |
| Directory | /workspace/39.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.2520274336 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 1230244134 ps |
| CPU time | 5.83 seconds |
| Started | Jan 24 01:08:24 PM PST 24 |
| Finished | Jan 24 01:09:05 PM PST 24 |
| Peak memory | 221524 kb |
| Host | smart-b43792f0-bcf0-4fb4-83e3-70b9de1a81e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2520274336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2520274336 |
| Directory | /workspace/39.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2208592328 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 243902658 ps |
| CPU time | 1.08 seconds |
| Started | Jan 24 01:08:21 PM PST 24 |
| Finished | Jan 24 01:08:59 PM PST 24 |
| Peak memory | 216892 kb |
| Host | smart-816822e2-7c80-471f-aa4a-6a69961fc720 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2208592328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2208592328 |
| Directory | /workspace/39.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/39.rstmgr_por_stretcher.2215004478 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 87112237 ps |
| CPU time | 0.72 seconds |
| Started | Jan 24 01:08:20 PM PST 24 |
| Finished | Jan 24 01:08:58 PM PST 24 |
| Peak memory | 199332 kb |
| Host | smart-30e5052f-20e5-4254-ba6e-692c518431ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2215004478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2215004478 |
| Directory | /workspace/39.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/39.rstmgr_reset.1806451102 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 1263457031 ps |
| CPU time | 5.75 seconds |
| Started | Jan 24 01:08:21 PM PST 24 |
| Finished | Jan 24 01:09:04 PM PST 24 |
| Peak memory | 199780 kb |
| Host | smart-b588e4c1-3482-4e23-960b-5daefca5d6a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1806451102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1806451102 |
| Directory | /workspace/39.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.375178874 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 175405059 ps |
| CPU time | 1.15 seconds |
| Started | Jan 24 01:39:21 PM PST 24 |
| Finished | Jan 24 01:39:26 PM PST 24 |
| Peak memory | 199568 kb |
| Host | smart-49c9177a-8f65-4b17-820d-213af3bcbecf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=375178874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.375178874 |
| Directory | /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/39.rstmgr_smoke.103706350 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 238540100 ps |
| CPU time | 1.39 seconds |
| Started | Jan 24 01:08:22 PM PST 24 |
| Finished | Jan 24 01:08:59 PM PST 24 |
| Peak memory | 199676 kb |
| Host | smart-db2049aa-dfc4-43e9-b5d8-53fb0f266951 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=103706350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.103706350 |
| Directory | /workspace/39.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/39.rstmgr_stress_all.842797343 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 9189193931 ps |
| CPU time | 30.8 seconds |
| Started | Jan 24 01:08:17 PM PST 24 |
| Finished | Jan 24 01:09:25 PM PST 24 |
| Peak memory | 199812 kb |
| Host | smart-0163319c-a60c-4286-8fe9-b8ec90ae6dda |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842797343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.842797343 |
| Directory | /workspace/39.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/39.rstmgr_sw_rst.708923430 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 349743608 ps |
| CPU time | 2.26 seconds |
| Started | Jan 24 01:08:22 PM PST 24 |
| Finished | Jan 24 01:09:00 PM PST 24 |
| Peak memory | 199652 kb |
| Host | smart-e1531b01-54bd-4258-ba36-f24528f8e8bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=708923430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.708923430 |
| Directory | /workspace/39.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.919017388 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 89488433 ps |
| CPU time | 0.87 seconds |
| Started | Jan 24 01:08:22 PM PST 24 |
| Finished | Jan 24 01:08:59 PM PST 24 |
| Peak memory | 199480 kb |
| Host | smart-3a4e1160-ab32-423c-8620-0999eca1954d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=919017388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.919017388 |
| Directory | /workspace/39.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/4.rstmgr_alert_test.1542890003 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 92449765 ps |
| CPU time | 0.83 seconds |
| Started | Jan 24 01:04:40 PM PST 24 |
| Finished | Jan 24 01:05:19 PM PST 24 |
| Peak memory | 199468 kb |
| Host | smart-77c2e456-5207-43b8-8e95-056c6cc6b170 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542890003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.1542890003 |
| Directory | /workspace/4.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2837090721 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 1221751301 ps |
| CPU time | 5.83 seconds |
| Started | Jan 24 01:04:19 PM PST 24 |
| Finished | Jan 24 01:05:08 PM PST 24 |
| Peak memory | 217520 kb |
| Host | smart-b8bf8061-b014-44f5-9666-9b720d08c2f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2837090721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2837090721 |
| Directory | /workspace/4.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2630096488 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 244781434 ps |
| CPU time | 1.1 seconds |
| Started | Jan 24 01:04:18 PM PST 24 |
| Finished | Jan 24 01:05:02 PM PST 24 |
| Peak memory | 216696 kb |
| Host | smart-3097ad0f-576f-4604-9f1a-bd2f41b3d12a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2630096488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.2630096488 |
| Directory | /workspace/4.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/4.rstmgr_por_stretcher.3048980037 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 94290767 ps |
| CPU time | 0.74 seconds |
| Started | Jan 24 01:04:23 PM PST 24 |
| Finished | Jan 24 01:05:06 PM PST 24 |
| Peak memory | 199324 kb |
| Host | smart-2d335fda-a2c3-4bb6-bf59-b7c31b0ef87c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3048980037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3048980037 |
| Directory | /workspace/4.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/4.rstmgr_reset.4243793683 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1185958249 ps |
| CPU time | 5.59 seconds |
| Started | Jan 24 01:04:22 PM PST 24 |
| Finished | Jan 24 01:05:11 PM PST 24 |
| Peak memory | 199720 kb |
| Host | smart-16ecbb6e-fcdf-441d-91be-b78f9bdfa6f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4243793683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.4243793683 |
| Directory | /workspace/4.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/4.rstmgr_sec_cm.1778247368 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 16506279133 ps |
| CPU time | 28.29 seconds |
| Started | Jan 24 01:04:41 PM PST 24 |
| Finished | Jan 24 01:05:47 PM PST 24 |
| Peak memory | 217684 kb |
| Host | smart-dbb352c3-97b2-4675-b722-bc8335d062f2 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778247368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.1778247368 |
| Directory | /workspace/4.rstmgr_sec_cm/latest |
| Test location | /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.528783358 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 97953303 ps |
| CPU time | 0.94 seconds |
| Started | Jan 24 01:04:23 PM PST 24 |
| Finished | Jan 24 01:05:06 PM PST 24 |
| Peak memory | 199528 kb |
| Host | smart-744737fa-1564-41f3-ba2e-8206e4d6263a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=528783358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.528783358 |
| Directory | /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/4.rstmgr_smoke.2483819500 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 223775648 ps |
| CPU time | 1.4 seconds |
| Started | Jan 24 01:04:26 PM PST 24 |
| Finished | Jan 24 01:05:09 PM PST 24 |
| Peak memory | 199724 kb |
| Host | smart-3a7db0a9-d22b-4358-b79c-b21b729d8d7e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2483819500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2483819500 |
| Directory | /workspace/4.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/4.rstmgr_stress_all.3459773824 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 5388945175 ps |
| CPU time | 23.62 seconds |
| Started | Jan 24 01:04:19 PM PST 24 |
| Finished | Jan 24 01:05:25 PM PST 24 |
| Peak memory | 199904 kb |
| Host | smart-27dd0eab-20de-498d-b57f-6358e0925003 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459773824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3459773824 |
| Directory | /workspace/4.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/4.rstmgr_sw_rst.579649815 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 367376788 ps |
| CPU time | 2.27 seconds |
| Started | Jan 24 01:04:25 PM PST 24 |
| Finished | Jan 24 01:05:10 PM PST 24 |
| Peak memory | 199596 kb |
| Host | smart-c8b9025f-ea15-4d1a-b2ea-baee1d86157e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=579649815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.579649815 |
| Directory | /workspace/4.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.2276797580 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 263033928 ps |
| CPU time | 1.39 seconds |
| Started | Jan 24 01:04:25 PM PST 24 |
| Finished | Jan 24 01:05:09 PM PST 24 |
| Peak memory | 199524 kb |
| Host | smart-c6e48709-1252-4e8e-b3a7-97cd552bbc26 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2276797580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2276797580 |
| Directory | /workspace/4.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/40.rstmgr_alert_test.2687211468 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 75538134 ps |
| CPU time | 0.79 seconds |
| Started | Jan 24 01:08:31 PM PST 24 |
| Finished | Jan 24 01:09:05 PM PST 24 |
| Peak memory | 199552 kb |
| Host | smart-9c27688d-8eac-44e5-aa84-e43f70a542b8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687211468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2687211468 |
| Directory | /workspace/40.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.884212749 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 1884671381 ps |
| CPU time | 6.92 seconds |
| Started | Jan 24 01:08:22 PM PST 24 |
| Finished | Jan 24 01:09:05 PM PST 24 |
| Peak memory | 217684 kb |
| Host | smart-3940746e-3b41-4ef2-9adf-7ebe8aa7551b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=884212749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.884212749 |
| Directory | /workspace/40.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2136434917 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 244195290 ps |
| CPU time | 1.19 seconds |
| Started | Jan 24 02:20:11 PM PST 24 |
| Finished | Jan 24 02:20:30 PM PST 24 |
| Peak memory | 216856 kb |
| Host | smart-83135966-6376-4ed4-8032-38f2c27a7242 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2136434917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2136434917 |
| Directory | /workspace/40.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/40.rstmgr_por_stretcher.2408942770 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 176122611 ps |
| CPU time | 0.84 seconds |
| Started | Jan 24 01:08:17 PM PST 24 |
| Finished | Jan 24 01:08:56 PM PST 24 |
| Peak memory | 199364 kb |
| Host | smart-d799df8c-dfd5-40ec-aa3d-ecd765d0a311 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2408942770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.2408942770 |
| Directory | /workspace/40.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/40.rstmgr_reset.1878096310 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 1049285701 ps |
| CPU time | 4.97 seconds |
| Started | Jan 24 01:42:50 PM PST 24 |
| Finished | Jan 24 01:43:34 PM PST 24 |
| Peak memory | 199708 kb |
| Host | smart-77d1b186-0416-4519-95c8-77aa41448a2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1878096310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.1878096310 |
| Directory | /workspace/40.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.915400159 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 187777730 ps |
| CPU time | 1.2 seconds |
| Started | Jan 24 01:38:24 PM PST 24 |
| Finished | Jan 24 01:38:48 PM PST 24 |
| Peak memory | 199568 kb |
| Host | smart-685f2956-3295-4a0a-8c89-d4a3c84fe537 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=915400159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.915400159 |
| Directory | /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/40.rstmgr_smoke.1057530733 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 107445770 ps |
| CPU time | 1.15 seconds |
| Started | Jan 24 01:08:17 PM PST 24 |
| Finished | Jan 24 01:08:57 PM PST 24 |
| Peak memory | 199764 kb |
| Host | smart-ca5e6d5d-482c-4e96-bbcc-778ad2f68a20 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1057530733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.1057530733 |
| Directory | /workspace/40.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/40.rstmgr_stress_all.3179565161 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 5081193613 ps |
| CPU time | 17.96 seconds |
| Started | Jan 24 01:08:30 PM PST 24 |
| Finished | Jan 24 01:09:21 PM PST 24 |
| Peak memory | 199780 kb |
| Host | smart-6394de89-48c9-44f2-8459-184e60596b2d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179565161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3179565161 |
| Directory | /workspace/40.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/40.rstmgr_sw_rst.1293730694 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 147706129 ps |
| CPU time | 1.78 seconds |
| Started | Jan 24 01:08:17 PM PST 24 |
| Finished | Jan 24 01:08:57 PM PST 24 |
| Peak memory | 199612 kb |
| Host | smart-5ec4c617-5b5b-47f9-b635-debe1feed269 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1293730694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.1293730694 |
| Directory | /workspace/40.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.1471703498 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 66574623 ps |
| CPU time | 0.73 seconds |
| Started | Jan 24 01:23:32 PM PST 24 |
| Finished | Jan 24 01:24:18 PM PST 24 |
| Peak memory | 199588 kb |
| Host | smart-39d6d2f6-4201-4aab-92ae-b2f6db7c5750 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1471703498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.1471703498 |
| Directory | /workspace/40.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/41.rstmgr_alert_test.2571752424 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 76856396 ps |
| CPU time | 0.8 seconds |
| Started | Jan 24 01:40:49 PM PST 24 |
| Finished | Jan 24 01:41:34 PM PST 24 |
| Peak memory | 199584 kb |
| Host | smart-f04f4a55-321a-4fb5-912b-85d9c866a67b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571752424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.2571752424 |
| Directory | /workspace/41.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1057621910 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 2165384573 ps |
| CPU time | 8.48 seconds |
| Started | Jan 24 01:28:41 PM PST 24 |
| Finished | Jan 24 01:29:12 PM PST 24 |
| Peak memory | 218204 kb |
| Host | smart-c2dd4f35-21e6-4985-a259-e1951aac8d97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1057621910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1057621910 |
| Directory | /workspace/41.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.126662875 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 244399807 ps |
| CPU time | 1.1 seconds |
| Started | Jan 24 01:08:35 PM PST 24 |
| Finished | Jan 24 01:09:10 PM PST 24 |
| Peak memory | 216708 kb |
| Host | smart-81139047-95df-41e1-84e8-34ab620addd8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=126662875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.126662875 |
| Directory | /workspace/41.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/41.rstmgr_por_stretcher.2928128372 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 93535820 ps |
| CPU time | 0.72 seconds |
| Started | Jan 24 01:12:44 PM PST 24 |
| Finished | Jan 24 01:13:36 PM PST 24 |
| Peak memory | 199324 kb |
| Host | smart-7dc79661-4e5c-4300-89db-6f3e4bd826e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2928128372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.2928128372 |
| Directory | /workspace/41.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/41.rstmgr_reset.372048138 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 1746502669 ps |
| CPU time | 6.35 seconds |
| Started | Jan 24 01:08:31 PM PST 24 |
| Finished | Jan 24 01:09:10 PM PST 24 |
| Peak memory | 199804 kb |
| Host | smart-7c0e25fa-7cd6-420d-a2b9-324243ea9012 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=372048138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.372048138 |
| Directory | /workspace/41.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.8175251 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 110106762 ps |
| CPU time | 1.05 seconds |
| Started | Jan 24 01:08:30 PM PST 24 |
| Finished | Jan 24 01:09:05 PM PST 24 |
| Peak memory | 199608 kb |
| Host | smart-d7d9c0ec-91e8-4c6a-b710-793add9841bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=8175251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.8175251 |
| Directory | /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/41.rstmgr_smoke.3366194489 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 248415235 ps |
| CPU time | 1.58 seconds |
| Started | Jan 24 01:32:16 PM PST 24 |
| Finished | Jan 24 01:33:01 PM PST 24 |
| Peak memory | 199776 kb |
| Host | smart-759cdbd2-1cfe-4605-a8ec-b31067b4c154 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3366194489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.3366194489 |
| Directory | /workspace/41.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/41.rstmgr_stress_all.1646998388 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 13334517852 ps |
| CPU time | 48.01 seconds |
| Started | Jan 24 01:24:04 PM PST 24 |
| Finished | Jan 24 01:25:28 PM PST 24 |
| Peak memory | 199828 kb |
| Host | smart-37976d65-2eda-42b8-ae70-5039c46cc89a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646998388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1646998388 |
| Directory | /workspace/41.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/41.rstmgr_sw_rst.3666823156 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 125147450 ps |
| CPU time | 1.51 seconds |
| Started | Jan 24 01:08:31 PM PST 24 |
| Finished | Jan 24 01:09:06 PM PST 24 |
| Peak memory | 199656 kb |
| Host | smart-c32fca3b-a57a-46fc-9aa8-f54f62eaaea5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3666823156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.3666823156 |
| Directory | /workspace/41.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.4284075006 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 132828561 ps |
| CPU time | 1 seconds |
| Started | Jan 24 01:08:37 PM PST 24 |
| Finished | Jan 24 01:09:12 PM PST 24 |
| Peak memory | 199568 kb |
| Host | smart-ef01e000-c1e6-434f-a56f-47802115e4f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4284075006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.4284075006 |
| Directory | /workspace/41.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/42.rstmgr_alert_test.3176876337 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 73450760 ps |
| CPU time | 0.77 seconds |
| Started | Jan 24 01:15:21 PM PST 24 |
| Finished | Jan 24 01:16:07 PM PST 24 |
| Peak memory | 199532 kb |
| Host | smart-d84f7a16-9c07-4a3b-ae0a-e90eb3f1c517 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176876337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3176876337 |
| Directory | /workspace/42.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.307310404 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 1217247186 ps |
| CPU time | 5.69 seconds |
| Started | Jan 24 01:08:40 PM PST 24 |
| Finished | Jan 24 01:09:24 PM PST 24 |
| Peak memory | 216972 kb |
| Host | smart-bb82c0a7-0cb8-4aa3-8100-6625c1d427e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=307310404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.307310404 |
| Directory | /workspace/42.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2602023719 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 243584374 ps |
| CPU time | 1.07 seconds |
| Started | Jan 24 01:08:39 PM PST 24 |
| Finished | Jan 24 01:09:17 PM PST 24 |
| Peak memory | 216776 kb |
| Host | smart-ce3f254b-de19-4303-ac90-d7bc1fbec6f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2602023719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2602023719 |
| Directory | /workspace/42.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/42.rstmgr_por_stretcher.1879118731 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 82945465 ps |
| CPU time | 0.74 seconds |
| Started | Jan 24 01:08:31 PM PST 24 |
| Finished | Jan 24 01:09:05 PM PST 24 |
| Peak memory | 199324 kb |
| Host | smart-9a553d53-d76d-4270-ae62-0215a3db8f1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1879118731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1879118731 |
| Directory | /workspace/42.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/42.rstmgr_reset.3630517506 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 1905248307 ps |
| CPU time | 6.84 seconds |
| Started | Jan 24 01:08:32 PM PST 24 |
| Finished | Jan 24 01:09:13 PM PST 24 |
| Peak memory | 199784 kb |
| Host | smart-fc2dad0c-2119-4fc1-8e93-2e8f38310fdb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3630517506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3630517506 |
| Directory | /workspace/42.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1803582867 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 141324552 ps |
| CPU time | 1.05 seconds |
| Started | Jan 24 01:19:54 PM PST 24 |
| Finished | Jan 24 01:20:57 PM PST 24 |
| Peak memory | 199568 kb |
| Host | smart-44a310ed-9efa-4519-97a1-fc8ada1c4834 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1803582867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1803582867 |
| Directory | /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/42.rstmgr_smoke.1859852285 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 222416257 ps |
| CPU time | 1.36 seconds |
| Started | Jan 24 01:08:35 PM PST 24 |
| Finished | Jan 24 01:09:10 PM PST 24 |
| Peak memory | 199680 kb |
| Host | smart-d4f67791-d05e-4045-b8f3-eabd2f10a98f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1859852285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.1859852285 |
| Directory | /workspace/42.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/42.rstmgr_stress_all.3021011537 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 10047573683 ps |
| CPU time | 35.69 seconds |
| Started | Jan 24 02:22:00 PM PST 24 |
| Finished | Jan 24 02:23:31 PM PST 24 |
| Peak memory | 199828 kb |
| Host | smart-9f4527b5-54aa-4a50-9286-cce70e4579a3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021011537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.3021011537 |
| Directory | /workspace/42.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/42.rstmgr_sw_rst.3660782368 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 114199454 ps |
| CPU time | 1.4 seconds |
| Started | Jan 24 01:40:07 PM PST 24 |
| Finished | Jan 24 01:41:00 PM PST 24 |
| Peak memory | 199632 kb |
| Host | smart-782e064f-2d20-4812-9c1c-b1344c282afd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3660782368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3660782368 |
| Directory | /workspace/42.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.797050092 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 206208455 ps |
| CPU time | 1.33 seconds |
| Started | Jan 24 02:12:59 PM PST 24 |
| Finished | Jan 24 02:13:20 PM PST 24 |
| Peak memory | 199568 kb |
| Host | smart-167e03ef-322e-46c5-941b-4d0285d98afe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=797050092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.797050092 |
| Directory | /workspace/42.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/43.rstmgr_alert_test.2091122920 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 65779355 ps |
| CPU time | 0.72 seconds |
| Started | Jan 24 01:08:39 PM PST 24 |
| Finished | Jan 24 01:09:17 PM PST 24 |
| Peak memory | 199536 kb |
| Host | smart-3f631460-934e-4a12-8a80-8b797b46a2cf |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091122920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2091122920 |
| Directory | /workspace/43.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.1925945786 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1230830791 ps |
| CPU time | 5.46 seconds |
| Started | Jan 24 01:18:25 PM PST 24 |
| Finished | Jan 24 01:19:12 PM PST 24 |
| Peak memory | 221024 kb |
| Host | smart-2be5e990-cb1c-4a6d-ac86-3893749335f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1925945786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.1925945786 |
| Directory | /workspace/43.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.863265117 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 247077755 ps |
| CPU time | 1.02 seconds |
| Started | Jan 24 01:08:43 PM PST 24 |
| Finished | Jan 24 01:09:22 PM PST 24 |
| Peak memory | 216856 kb |
| Host | smart-00a11798-f7f1-4a88-b090-b3687d904744 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=863265117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.863265117 |
| Directory | /workspace/43.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/43.rstmgr_por_stretcher.2774922699 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 137068000 ps |
| CPU time | 0.79 seconds |
| Started | Jan 24 01:08:36 PM PST 24 |
| Finished | Jan 24 01:09:10 PM PST 24 |
| Peak memory | 199332 kb |
| Host | smart-d3497a9a-c72f-436e-9869-6469e45008e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2774922699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2774922699 |
| Directory | /workspace/43.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/43.rstmgr_reset.3272102992 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 692911354 ps |
| CPU time | 3.6 seconds |
| Started | Jan 24 01:29:07 PM PST 24 |
| Finished | Jan 24 01:29:25 PM PST 24 |
| Peak memory | 199824 kb |
| Host | smart-ba2acc72-34a7-4e66-b42f-033eea353c7c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3272102992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.3272102992 |
| Directory | /workspace/43.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1191954472 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 178332421 ps |
| CPU time | 1.18 seconds |
| Started | Jan 24 02:33:20 PM PST 24 |
| Finished | Jan 24 02:33:47 PM PST 24 |
| Peak memory | 199568 kb |
| Host | smart-7727598a-25be-473e-84fe-e618d17b5ea1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1191954472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1191954472 |
| Directory | /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/43.rstmgr_smoke.1052515970 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 188321220 ps |
| CPU time | 1.43 seconds |
| Started | Jan 24 01:08:34 PM PST 24 |
| Finished | Jan 24 01:09:09 PM PST 24 |
| Peak memory | 199716 kb |
| Host | smart-453eb632-10c5-425e-a317-9c75d12669f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1052515970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1052515970 |
| Directory | /workspace/43.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/43.rstmgr_stress_all.2393705600 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 5051697648 ps |
| CPU time | 23 seconds |
| Started | Jan 24 01:08:44 PM PST 24 |
| Finished | Jan 24 01:09:45 PM PST 24 |
| Peak memory | 199796 kb |
| Host | smart-ebf5c0e0-36ae-480a-b880-be780101b9c1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393705600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.2393705600 |
| Directory | /workspace/43.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/43.rstmgr_sw_rst.192842104 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 426030444 ps |
| CPU time | 2.37 seconds |
| Started | Jan 24 01:48:53 PM PST 24 |
| Finished | Jan 24 01:49:02 PM PST 24 |
| Peak memory | 199708 kb |
| Host | smart-60ddbf2a-6a26-4f84-91b3-288cb6292de3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=192842104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.192842104 |
| Directory | /workspace/43.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.2767940906 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 98487742 ps |
| CPU time | 0.83 seconds |
| Started | Jan 24 01:08:35 PM PST 24 |
| Finished | Jan 24 01:09:10 PM PST 24 |
| Peak memory | 199536 kb |
| Host | smart-0ee65e0e-965b-4cdb-a708-fd305afa6cd3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2767940906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.2767940906 |
| Directory | /workspace/43.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/44.rstmgr_alert_test.4084151503 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 53581458 ps |
| CPU time | 0.74 seconds |
| Started | Jan 24 01:12:21 PM PST 24 |
| Finished | Jan 24 01:13:12 PM PST 24 |
| Peak memory | 199508 kb |
| Host | smart-1adeb1e6-6cad-477e-beb7-b4ef12058bf9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084151503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.4084151503 |
| Directory | /workspace/44.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3030210721 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1909039150 ps |
| CPU time | 7.15 seconds |
| Started | Jan 24 01:08:41 PM PST 24 |
| Finished | Jan 24 01:09:26 PM PST 24 |
| Peak memory | 220996 kb |
| Host | smart-e4fe61cd-81cb-49f2-ac03-f275b967b6ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3030210721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3030210721 |
| Directory | /workspace/44.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.4011349595 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 244320906 ps |
| CPU time | 1.12 seconds |
| Started | Jan 24 01:08:41 PM PST 24 |
| Finished | Jan 24 01:09:20 PM PST 24 |
| Peak memory | 216872 kb |
| Host | smart-8e0bd881-dd82-4278-87df-53ae614f6eb9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4011349595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.4011349595 |
| Directory | /workspace/44.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/44.rstmgr_por_stretcher.602081705 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 152616867 ps |
| CPU time | 0.78 seconds |
| Started | Jan 24 01:08:42 PM PST 24 |
| Finished | Jan 24 01:09:21 PM PST 24 |
| Peak memory | 199316 kb |
| Host | smart-4836940e-3f14-4bc8-8cb8-dc3241741b71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=602081705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.602081705 |
| Directory | /workspace/44.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/44.rstmgr_reset.802565490 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 1487379487 ps |
| CPU time | 6.85 seconds |
| Started | Jan 24 01:56:42 PM PST 24 |
| Finished | Jan 24 01:56:58 PM PST 24 |
| Peak memory | 199688 kb |
| Host | smart-8fc00978-08e7-4f95-97e1-3f4b538de288 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=802565490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.802565490 |
| Directory | /workspace/44.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3748499708 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 178909803 ps |
| CPU time | 1.12 seconds |
| Started | Jan 24 01:08:42 PM PST 24 |
| Finished | Jan 24 01:09:21 PM PST 24 |
| Peak memory | 199572 kb |
| Host | smart-941b5ca2-1453-4c7e-ad83-df334800f8d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3748499708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3748499708 |
| Directory | /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/44.rstmgr_smoke.3768463200 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 192483114 ps |
| CPU time | 1.33 seconds |
| Started | Jan 24 01:40:58 PM PST 24 |
| Finished | Jan 24 01:41:36 PM PST 24 |
| Peak memory | 199776 kb |
| Host | smart-6834cb58-c8a9-4208-baa7-08f59b381178 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3768463200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.3768463200 |
| Directory | /workspace/44.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/44.rstmgr_stress_all.4029409719 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 8445271831 ps |
| CPU time | 30.74 seconds |
| Started | Jan 24 01:08:41 PM PST 24 |
| Finished | Jan 24 01:09:51 PM PST 24 |
| Peak memory | 199832 kb |
| Host | smart-a1e8fa58-f246-4e8e-af36-81a90a18da1e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029409719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.4029409719 |
| Directory | /workspace/44.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/44.rstmgr_sw_rst.2268510474 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 121497333 ps |
| CPU time | 1.4 seconds |
| Started | Jan 24 01:08:40 PM PST 24 |
| Finished | Jan 24 01:09:18 PM PST 24 |
| Peak memory | 199668 kb |
| Host | smart-54d8137c-c0a9-48e1-bc37-76f41915ae6c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2268510474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.2268510474 |
| Directory | /workspace/44.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.3059963550 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 134486146 ps |
| CPU time | 1.09 seconds |
| Started | Jan 24 01:08:45 PM PST 24 |
| Finished | Jan 24 01:09:24 PM PST 24 |
| Peak memory | 199528 kb |
| Host | smart-9ddca2ee-b3cb-4a36-85d8-d623b2819e9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3059963550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.3059963550 |
| Directory | /workspace/44.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/45.rstmgr_alert_test.2686308755 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 68071499 ps |
| CPU time | 0.79 seconds |
| Started | Jan 24 01:08:57 PM PST 24 |
| Finished | Jan 24 01:09:31 PM PST 24 |
| Peak memory | 199456 kb |
| Host | smart-ddb4e034-6fd1-44f6-8c1e-1f6247017343 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686308755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.2686308755 |
| Directory | /workspace/45.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.3971773108 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1895927184 ps |
| CPU time | 7.05 seconds |
| Started | Jan 24 01:08:58 PM PST 24 |
| Finished | Jan 24 01:09:38 PM PST 24 |
| Peak memory | 221016 kb |
| Host | smart-15184480-0ee7-48f0-ba28-190c61b0188a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3971773108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.3971773108 |
| Directory | /workspace/45.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3814015396 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 243702659 ps |
| CPU time | 1.08 seconds |
| Started | Jan 24 01:09:00 PM PST 24 |
| Finished | Jan 24 01:09:33 PM PST 24 |
| Peak memory | 216868 kb |
| Host | smart-ae269311-9174-450d-9d9a-a408f1303d71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3814015396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3814015396 |
| Directory | /workspace/45.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/45.rstmgr_por_stretcher.2223341425 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 85986127 ps |
| CPU time | 0.73 seconds |
| Started | Jan 24 01:08:42 PM PST 24 |
| Finished | Jan 24 01:09:21 PM PST 24 |
| Peak memory | 199368 kb |
| Host | smart-30cb7428-04d7-4f78-99f2-5504dcf9b660 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2223341425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.2223341425 |
| Directory | /workspace/45.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/45.rstmgr_reset.3761487372 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 689530595 ps |
| CPU time | 3.65 seconds |
| Started | Jan 24 01:23:14 PM PST 24 |
| Finished | Jan 24 01:24:08 PM PST 24 |
| Peak memory | 199764 kb |
| Host | smart-5e759ec4-04de-45a1-b22b-7a7257013428 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3761487372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.3761487372 |
| Directory | /workspace/45.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3153862454 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 107287031 ps |
| CPU time | 0.97 seconds |
| Started | Jan 24 01:08:59 PM PST 24 |
| Finished | Jan 24 01:09:33 PM PST 24 |
| Peak memory | 199552 kb |
| Host | smart-4526b0a2-d708-40b1-a7eb-9e0a05a9e26d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3153862454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3153862454 |
| Directory | /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/45.rstmgr_smoke.2172174224 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 191160669 ps |
| CPU time | 1.4 seconds |
| Started | Jan 24 02:42:38 PM PST 24 |
| Finished | Jan 24 02:43:04 PM PST 24 |
| Peak memory | 199832 kb |
| Host | smart-758ab804-d15b-4857-82cd-b12203874774 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2172174224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2172174224 |
| Directory | /workspace/45.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/45.rstmgr_stress_all.121901919 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 8506933758 ps |
| CPU time | 36.74 seconds |
| Started | Jan 24 01:08:59 PM PST 24 |
| Finished | Jan 24 01:10:08 PM PST 24 |
| Peak memory | 199828 kb |
| Host | smart-31c80190-e83c-4cb6-a3d1-1dacb8d55855 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121901919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.121901919 |
| Directory | /workspace/45.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/45.rstmgr_sw_rst.810941325 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 158444603 ps |
| CPU time | 1.86 seconds |
| Started | Jan 24 01:08:59 PM PST 24 |
| Finished | Jan 24 01:09:33 PM PST 24 |
| Peak memory | 199700 kb |
| Host | smart-0451ad84-0ba9-4b6f-8ce8-0e1d0089f28f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=810941325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.810941325 |
| Directory | /workspace/45.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.1877429623 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 267648636 ps |
| CPU time | 1.47 seconds |
| Started | Jan 24 01:08:56 PM PST 24 |
| Finished | Jan 24 01:09:31 PM PST 24 |
| Peak memory | 199588 kb |
| Host | smart-5fcd47ba-6290-46b1-a0e0-0cf832cb068d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1877429623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.1877429623 |
| Directory | /workspace/45.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/46.rstmgr_alert_test.777929796 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 69489562 ps |
| CPU time | 0.77 seconds |
| Started | Jan 24 01:09:04 PM PST 24 |
| Finished | Jan 24 01:09:39 PM PST 24 |
| Peak memory | 197776 kb |
| Host | smart-d5a4f70a-d6ea-4503-b6bc-df8196e6ec00 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777929796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.777929796 |
| Directory | /workspace/46.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.3951142581 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 1875332357 ps |
| CPU time | 7.29 seconds |
| Started | Jan 24 01:08:58 PM PST 24 |
| Finished | Jan 24 01:09:38 PM PST 24 |
| Peak memory | 221176 kb |
| Host | smart-14d0ad70-5a10-4ba4-a334-6f5c9ae25335 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3951142581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.3951142581 |
| Directory | /workspace/46.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.91345195 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 243784408 ps |
| CPU time | 1.06 seconds |
| Started | Jan 24 01:09:01 PM PST 24 |
| Finished | Jan 24 01:09:35 PM PST 24 |
| Peak memory | 216892 kb |
| Host | smart-42635f3f-15b4-48b4-9025-02d987d0c674 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=91345195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.91345195 |
| Directory | /workspace/46.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/46.rstmgr_por_stretcher.1771210652 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 191987419 ps |
| CPU time | 0.85 seconds |
| Started | Jan 24 01:08:56 PM PST 24 |
| Finished | Jan 24 01:09:30 PM PST 24 |
| Peak memory | 199364 kb |
| Host | smart-26a4af46-4bb1-44ce-bce2-e55c09e4eb56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1771210652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.1771210652 |
| Directory | /workspace/46.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/46.rstmgr_reset.3465233193 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1983204474 ps |
| CPU time | 7.19 seconds |
| Started | Jan 24 01:08:56 PM PST 24 |
| Finished | Jan 24 01:09:37 PM PST 24 |
| Peak memory | 199704 kb |
| Host | smart-43d4697b-0e95-406e-81fb-92f924f4af43 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3465233193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.3465233193 |
| Directory | /workspace/46.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.3503227728 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 183951372 ps |
| CPU time | 1.22 seconds |
| Started | Jan 24 01:09:04 PM PST 24 |
| Finished | Jan 24 01:09:39 PM PST 24 |
| Peak memory | 198032 kb |
| Host | smart-e7a2e4d1-ee30-44d6-b46e-f613e94af0d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3503227728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.3503227728 |
| Directory | /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/46.rstmgr_smoke.2316811176 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 249989941 ps |
| CPU time | 1.54 seconds |
| Started | Jan 24 01:08:57 PM PST 24 |
| Finished | Jan 24 01:09:32 PM PST 24 |
| Peak memory | 199728 kb |
| Host | smart-1692e9fe-f4cf-447c-9b49-2745a561bc4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2316811176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.2316811176 |
| Directory | /workspace/46.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/46.rstmgr_stress_all.918909460 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 12010006351 ps |
| CPU time | 45.94 seconds |
| Started | Jan 24 01:08:58 PM PST 24 |
| Finished | Jan 24 01:10:17 PM PST 24 |
| Peak memory | 199812 kb |
| Host | smart-67ff1c27-7696-444a-b214-c9c409c08e00 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918909460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.918909460 |
| Directory | /workspace/46.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/46.rstmgr_sw_rst.1010196454 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 466903281 ps |
| CPU time | 2.63 seconds |
| Started | Jan 24 01:08:58 PM PST 24 |
| Finished | Jan 24 01:09:34 PM PST 24 |
| Peak memory | 199644 kb |
| Host | smart-49b136e7-16d4-43e4-847b-749461647737 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1010196454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.1010196454 |
| Directory | /workspace/46.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.3381636387 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 97863030 ps |
| CPU time | 0.96 seconds |
| Started | Jan 24 01:08:59 PM PST 24 |
| Finished | Jan 24 01:09:33 PM PST 24 |
| Peak memory | 199568 kb |
| Host | smart-5e71a8a6-3884-4805-b07a-833a72c5fdda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3381636387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.3381636387 |
| Directory | /workspace/46.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/47.rstmgr_alert_test.4291035802 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 80957021 ps |
| CPU time | 0.81 seconds |
| Started | Jan 24 01:09:16 PM PST 24 |
| Finished | Jan 24 01:09:55 PM PST 24 |
| Peak memory | 199564 kb |
| Host | smart-f2ff28e8-271e-4a50-89a0-92dc0a15e674 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291035802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.4291035802 |
| Directory | /workspace/47.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.2800365553 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 1224877281 ps |
| CPU time | 6.09 seconds |
| Started | Jan 24 01:09:19 PM PST 24 |
| Finished | Jan 24 01:10:04 PM PST 24 |
| Peak memory | 217412 kb |
| Host | smart-008ee709-a11b-4aca-b6b4-2d905af6265e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2800365553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.2800365553 |
| Directory | /workspace/47.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1310570827 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 244986284 ps |
| CPU time | 1.14 seconds |
| Started | Jan 24 01:09:17 PM PST 24 |
| Finished | Jan 24 01:09:57 PM PST 24 |
| Peak memory | 216708 kb |
| Host | smart-5b4ae99a-d76b-42a7-9ea1-4d946e514b53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1310570827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.1310570827 |
| Directory | /workspace/47.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/47.rstmgr_por_stretcher.3363907237 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 94409412 ps |
| CPU time | 0.77 seconds |
| Started | Jan 24 01:08:58 PM PST 24 |
| Finished | Jan 24 01:09:32 PM PST 24 |
| Peak memory | 199320 kb |
| Host | smart-3169d84d-2ec1-4823-b07e-2041abc229cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3363907237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3363907237 |
| Directory | /workspace/47.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/47.rstmgr_reset.755014345 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 1476251503 ps |
| CPU time | 5.86 seconds |
| Started | Jan 24 01:09:00 PM PST 24 |
| Finished | Jan 24 01:09:38 PM PST 24 |
| Peak memory | 199760 kb |
| Host | smart-ee6e46c3-b96f-4d4b-befc-14a9c67503eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=755014345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.755014345 |
| Directory | /workspace/47.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.735204060 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 155200470 ps |
| CPU time | 1.07 seconds |
| Started | Jan 24 01:09:00 PM PST 24 |
| Finished | Jan 24 01:09:35 PM PST 24 |
| Peak memory | 199588 kb |
| Host | smart-caa90e30-ff97-4f44-8076-1eaafebb5770 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=735204060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.735204060 |
| Directory | /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/47.rstmgr_smoke.865465857 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 193855961 ps |
| CPU time | 1.41 seconds |
| Started | Jan 24 01:08:58 PM PST 24 |
| Finished | Jan 24 01:09:33 PM PST 24 |
| Peak memory | 199712 kb |
| Host | smart-5f09f08e-e423-40bb-8178-ab9118920762 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=865465857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.865465857 |
| Directory | /workspace/47.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/47.rstmgr_stress_all.3966869717 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 309740016 ps |
| CPU time | 1.62 seconds |
| Started | Jan 24 01:09:16 PM PST 24 |
| Finished | Jan 24 01:09:56 PM PST 24 |
| Peak memory | 199812 kb |
| Host | smart-a455eba0-91f8-4351-9746-2c9aa136f3d4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966869717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3966869717 |
| Directory | /workspace/47.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/47.rstmgr_sw_rst.1094510944 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 333958453 ps |
| CPU time | 2.14 seconds |
| Started | Jan 24 01:08:58 PM PST 24 |
| Finished | Jan 24 01:09:34 PM PST 24 |
| Peak memory | 199672 kb |
| Host | smart-6c6a352e-913f-4cc1-87cf-6369447fe68e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1094510944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.1094510944 |
| Directory | /workspace/47.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.2404898861 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 140450804 ps |
| CPU time | 1.1 seconds |
| Started | Jan 24 01:08:57 PM PST 24 |
| Finished | Jan 24 01:09:31 PM PST 24 |
| Peak memory | 199512 kb |
| Host | smart-85a7ff5a-4fab-4201-a81a-0daa5e23014d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2404898861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.2404898861 |
| Directory | /workspace/47.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.2258469348 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 1909126772 ps |
| CPU time | 7.46 seconds |
| Started | Jan 24 01:09:19 PM PST 24 |
| Finished | Jan 24 01:10:05 PM PST 24 |
| Peak memory | 216932 kb |
| Host | smart-6fcae205-e5b7-4b1b-a39c-50ebff38f6d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2258469348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2258469348 |
| Directory | /workspace/48.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.8323107 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 243822805 ps |
| CPU time | 1.11 seconds |
| Started | Jan 24 01:09:20 PM PST 24 |
| Finished | Jan 24 01:09:59 PM PST 24 |
| Peak memory | 216860 kb |
| Host | smart-adec8751-8a4e-483d-97ce-4f0f2198ae8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=8323107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.8323107 |
| Directory | /workspace/48.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/48.rstmgr_por_stretcher.1224930803 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 199944542 ps |
| CPU time | 0.94 seconds |
| Started | Jan 24 01:09:20 PM PST 24 |
| Finished | Jan 24 01:09:59 PM PST 24 |
| Peak memory | 199368 kb |
| Host | smart-0581e844-77ca-400f-84ef-9c602f2e99d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1224930803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1224930803 |
| Directory | /workspace/48.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/48.rstmgr_reset.3886289502 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 1638052208 ps |
| CPU time | 6.44 seconds |
| Started | Jan 24 01:09:16 PM PST 24 |
| Finished | Jan 24 01:10:01 PM PST 24 |
| Peak memory | 199784 kb |
| Host | smart-c555f3f0-dd65-457c-86d9-359373637c88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3886289502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3886289502 |
| Directory | /workspace/48.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.952084267 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 101328625 ps |
| CPU time | 0.96 seconds |
| Started | Jan 24 01:09:16 PM PST 24 |
| Finished | Jan 24 01:09:55 PM PST 24 |
| Peak memory | 199608 kb |
| Host | smart-5f0bbb1e-29af-40e8-bf2f-b5dcd1c0d751 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=952084267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.952084267 |
| Directory | /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/48.rstmgr_smoke.2437549565 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 125106760 ps |
| CPU time | 1.22 seconds |
| Started | Jan 24 01:09:16 PM PST 24 |
| Finished | Jan 24 01:09:56 PM PST 24 |
| Peak memory | 199784 kb |
| Host | smart-5f805fde-5e7e-4334-90bb-80f792cfcff2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2437549565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2437549565 |
| Directory | /workspace/48.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/48.rstmgr_stress_all.1819079256 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 13203300098 ps |
| CPU time | 43.07 seconds |
| Started | Jan 24 01:09:17 PM PST 24 |
| Finished | Jan 24 01:10:40 PM PST 24 |
| Peak memory | 199824 kb |
| Host | smart-a0f23310-38e4-430e-82db-bc74fd4b6d4f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819079256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1819079256 |
| Directory | /workspace/48.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/48.rstmgr_sw_rst.28651270 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 121872887 ps |
| CPU time | 1.62 seconds |
| Started | Jan 24 01:09:12 PM PST 24 |
| Finished | Jan 24 01:09:51 PM PST 24 |
| Peak memory | 199636 kb |
| Host | smart-88eac0ae-1deb-41c7-b93a-2377a54f9493 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=28651270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.28651270 |
| Directory | /workspace/48.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.360522584 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 87154376 ps |
| CPU time | 0.86 seconds |
| Started | Jan 24 01:09:19 PM PST 24 |
| Finished | Jan 24 01:09:59 PM PST 24 |
| Peak memory | 199560 kb |
| Host | smart-bb579b93-ad2d-4721-8c5f-1b9fb8d02dc1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=360522584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.360522584 |
| Directory | /workspace/48.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/49.rstmgr_alert_test.4285302907 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 79828047 ps |
| CPU time | 0.73 seconds |
| Started | Jan 24 01:19:10 PM PST 24 |
| Finished | Jan 24 01:20:11 PM PST 24 |
| Peak memory | 199508 kb |
| Host | smart-ee2e65f2-5795-490f-9b38-b10c2386e107 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285302907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.4285302907 |
| Directory | /workspace/49.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.1958142579 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 1220614461 ps |
| CPU time | 5.57 seconds |
| Started | Jan 24 01:09:16 PM PST 24 |
| Finished | Jan 24 01:10:00 PM PST 24 |
| Peak memory | 216548 kb |
| Host | smart-da9b35d9-6b6f-46fe-a472-d8a6aaeb4cd7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1958142579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1958142579 |
| Directory | /workspace/49.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3376948911 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 244399467 ps |
| CPU time | 1.01 seconds |
| Started | Jan 24 01:09:12 PM PST 24 |
| Finished | Jan 24 01:09:50 PM PST 24 |
| Peak memory | 216808 kb |
| Host | smart-7c392481-131f-46b8-9c6d-e3d141d4ff2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3376948911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3376948911 |
| Directory | /workspace/49.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/49.rstmgr_por_stretcher.1023202352 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 225957937 ps |
| CPU time | 0.88 seconds |
| Started | Jan 24 01:09:20 PM PST 24 |
| Finished | Jan 24 01:09:59 PM PST 24 |
| Peak memory | 199364 kb |
| Host | smart-27523568-2f80-4a42-bc60-c04d6802d5cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1023202352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1023202352 |
| Directory | /workspace/49.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/49.rstmgr_reset.802440147 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 989742928 ps |
| CPU time | 4.98 seconds |
| Started | Jan 24 01:09:15 PM PST 24 |
| Finished | Jan 24 01:09:59 PM PST 24 |
| Peak memory | 199772 kb |
| Host | smart-9352487e-b795-4545-9638-5fd59cebd1f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=802440147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.802440147 |
| Directory | /workspace/49.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2382060210 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 149739285 ps |
| CPU time | 1.1 seconds |
| Started | Jan 24 01:09:13 PM PST 24 |
| Finished | Jan 24 01:09:51 PM PST 24 |
| Peak memory | 199584 kb |
| Host | smart-082dc13e-99f7-4799-8c10-be8de211dcdd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2382060210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2382060210 |
| Directory | /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/49.rstmgr_smoke.2331871695 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 191907226 ps |
| CPU time | 1.3 seconds |
| Started | Jan 24 01:09:20 PM PST 24 |
| Finished | Jan 24 01:09:59 PM PST 24 |
| Peak memory | 199768 kb |
| Host | smart-cd3d1020-e9a5-403a-9247-315a8dba669a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2331871695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2331871695 |
| Directory | /workspace/49.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/49.rstmgr_stress_all.528180293 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 3207846980 ps |
| CPU time | 13.6 seconds |
| Started | Jan 24 01:09:15 PM PST 24 |
| Finished | Jan 24 01:10:06 PM PST 24 |
| Peak memory | 199832 kb |
| Host | smart-e6700d7f-d83d-416b-ac30-71aa4bed9582 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528180293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.528180293 |
| Directory | /workspace/49.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/49.rstmgr_sw_rst.1680019373 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 124947695 ps |
| CPU time | 1.5 seconds |
| Started | Jan 24 01:09:20 PM PST 24 |
| Finished | Jan 24 01:10:00 PM PST 24 |
| Peak memory | 199620 kb |
| Host | smart-70e04b8d-5f11-4719-8afe-ea990cc3631c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1680019373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.1680019373 |
| Directory | /workspace/49.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1728777463 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 266205850 ps |
| CPU time | 1.48 seconds |
| Started | Jan 24 01:09:15 PM PST 24 |
| Finished | Jan 24 01:09:56 PM PST 24 |
| Peak memory | 199572 kb |
| Host | smart-aecbb3c5-d921-4474-a73b-44e3ff21d8b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1728777463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1728777463 |
| Directory | /workspace/49.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/5.rstmgr_alert_test.2175952940 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 54868604 ps |
| CPU time | 0.71 seconds |
| Started | Jan 24 01:04:41 PM PST 24 |
| Finished | Jan 24 01:05:19 PM PST 24 |
| Peak memory | 199528 kb |
| Host | smart-2ab1850e-da54-471d-939c-adf5f0f52756 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175952940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.2175952940 |
| Directory | /workspace/5.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.808162402 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1905752744 ps |
| CPU time | 6.82 seconds |
| Started | Jan 24 01:04:33 PM PST 24 |
| Finished | Jan 24 01:05:18 PM PST 24 |
| Peak memory | 216908 kb |
| Host | smart-fc80db9e-8121-4e21-8224-f0c604e1cb53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=808162402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.808162402 |
| Directory | /workspace/5.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.579598994 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 244204835 ps |
| CPU time | 1.1 seconds |
| Started | Jan 24 01:04:34 PM PST 24 |
| Finished | Jan 24 01:05:14 PM PST 24 |
| Peak memory | 216832 kb |
| Host | smart-1cb9c55e-99ec-49e5-ae39-3e4f18d5a278 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=579598994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.579598994 |
| Directory | /workspace/5.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/5.rstmgr_por_stretcher.2258125542 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 158572103 ps |
| CPU time | 0.79 seconds |
| Started | Jan 24 01:04:43 PM PST 24 |
| Finished | Jan 24 01:05:23 PM PST 24 |
| Peak memory | 199356 kb |
| Host | smart-b61b3dbd-2640-424b-b5ea-8440f9f60400 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2258125542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.2258125542 |
| Directory | /workspace/5.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/5.rstmgr_reset.1189411947 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 1874621942 ps |
| CPU time | 7.67 seconds |
| Started | Jan 24 01:04:43 PM PST 24 |
| Finished | Jan 24 01:05:30 PM PST 24 |
| Peak memory | 199760 kb |
| Host | smart-7d4fd2df-eeb2-4ee4-9030-513f0ce2b911 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1189411947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1189411947 |
| Directory | /workspace/5.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3462612122 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 103281478 ps |
| CPU time | 0.96 seconds |
| Started | Jan 24 01:06:45 PM PST 24 |
| Finished | Jan 24 01:07:46 PM PST 24 |
| Peak memory | 199540 kb |
| Host | smart-9115e8d2-b8ed-40c6-ad23-06be64795b36 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3462612122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3462612122 |
| Directory | /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/5.rstmgr_smoke.190242546 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 122147250 ps |
| CPU time | 1.19 seconds |
| Started | Jan 24 01:04:33 PM PST 24 |
| Finished | Jan 24 01:05:14 PM PST 24 |
| Peak memory | 199760 kb |
| Host | smart-61b47352-1b0a-4294-9ced-226326cce33c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=190242546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.190242546 |
| Directory | /workspace/5.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/5.rstmgr_stress_all.516406524 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 13901356268 ps |
| CPU time | 43.91 seconds |
| Started | Jan 24 01:04:39 PM PST 24 |
| Finished | Jan 24 01:06:01 PM PST 24 |
| Peak memory | 199844 kb |
| Host | smart-9490e839-05b7-4bee-92b8-6643acaa5691 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516406524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.516406524 |
| Directory | /workspace/5.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/5.rstmgr_sw_rst.3251809669 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 365153653 ps |
| CPU time | 2.31 seconds |
| Started | Jan 24 01:04:43 PM PST 24 |
| Finished | Jan 24 01:05:25 PM PST 24 |
| Peak memory | 199628 kb |
| Host | smart-102bffdf-389a-44b4-a287-df6ab29f4b7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3251809669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3251809669 |
| Directory | /workspace/5.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.3616485828 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 152123326 ps |
| CPU time | 1.33 seconds |
| Started | Jan 24 01:04:27 PM PST 24 |
| Finished | Jan 24 01:05:10 PM PST 24 |
| Peak memory | 199688 kb |
| Host | smart-d2509307-e5da-4ab6-96b4-b1f70b34e9ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3616485828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.3616485828 |
| Directory | /workspace/5.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/6.rstmgr_alert_test.2600378682 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 72825591 ps |
| CPU time | 0.84 seconds |
| Started | Jan 24 01:04:44 PM PST 24 |
| Finished | Jan 24 01:05:24 PM PST 24 |
| Peak memory | 199560 kb |
| Host | smart-61cc823a-68ff-4db7-9c33-8915c6ccda55 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600378682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.2600378682 |
| Directory | /workspace/6.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.2406856951 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 2166001189 ps |
| CPU time | 7.14 seconds |
| Started | Jan 24 01:04:29 PM PST 24 |
| Finished | Jan 24 01:05:17 PM PST 24 |
| Peak memory | 216372 kb |
| Host | smart-a6715179-731e-4e7a-8a79-1b5f98c76760 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2406856951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2406856951 |
| Directory | /workspace/6.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2600771112 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 243790887 ps |
| CPU time | 1.19 seconds |
| Started | Jan 24 01:04:30 PM PST 24 |
| Finished | Jan 24 01:05:11 PM PST 24 |
| Peak memory | 216844 kb |
| Host | smart-6fb6a3d1-0cb7-4db7-9a13-de0de5d0885d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2600771112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2600771112 |
| Directory | /workspace/6.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/6.rstmgr_por_stretcher.868973222 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 187539550 ps |
| CPU time | 0.83 seconds |
| Started | Jan 24 01:04:32 PM PST 24 |
| Finished | Jan 24 01:05:12 PM PST 24 |
| Peak memory | 199184 kb |
| Host | smart-a399d23f-c67f-429f-a999-c272c76cf116 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=868973222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.868973222 |
| Directory | /workspace/6.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/6.rstmgr_reset.2243465950 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 1466134695 ps |
| CPU time | 5.57 seconds |
| Started | Jan 24 01:04:41 PM PST 24 |
| Finished | Jan 24 01:05:24 PM PST 24 |
| Peak memory | 199780 kb |
| Host | smart-4bc2f4ea-773b-4f7f-b675-38c3add42cf1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2243465950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2243465950 |
| Directory | /workspace/6.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.2299269140 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 177573652 ps |
| CPU time | 1.2 seconds |
| Started | Jan 24 01:04:34 PM PST 24 |
| Finished | Jan 24 01:05:14 PM PST 24 |
| Peak memory | 199536 kb |
| Host | smart-32463c56-6fb1-4dff-a0bc-6c4a09cff19c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2299269140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.2299269140 |
| Directory | /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/6.rstmgr_smoke.3963789181 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 249246259 ps |
| CPU time | 1.62 seconds |
| Started | Jan 24 01:04:32 PM PST 24 |
| Finished | Jan 24 01:05:13 PM PST 24 |
| Peak memory | 199560 kb |
| Host | smart-ca719278-4909-48bb-83dd-9f64d6c2f1b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3963789181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.3963789181 |
| Directory | /workspace/6.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/6.rstmgr_stress_all.1886659609 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 2346089013 ps |
| CPU time | 11.33 seconds |
| Started | Jan 24 01:04:37 PM PST 24 |
| Finished | Jan 24 01:05:26 PM PST 24 |
| Peak memory | 199788 kb |
| Host | smart-83056a24-c8d9-4420-9d6c-971cc0c188d7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886659609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1886659609 |
| Directory | /workspace/6.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/6.rstmgr_sw_rst.1262919627 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 148613303 ps |
| CPU time | 1.79 seconds |
| Started | Jan 24 01:04:33 PM PST 24 |
| Finished | Jan 24 01:05:14 PM PST 24 |
| Peak memory | 199616 kb |
| Host | smart-16bd24a0-bdf4-4b8f-b2dd-69136d4fd7af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1262919627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1262919627 |
| Directory | /workspace/6.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.2476584479 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 134068413 ps |
| CPU time | 1.11 seconds |
| Started | Jan 24 01:04:41 PM PST 24 |
| Finished | Jan 24 01:05:20 PM PST 24 |
| Peak memory | 199580 kb |
| Host | smart-1b06813f-fdbd-437e-9f8b-0f683fc90b89 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2476584479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.2476584479 |
| Directory | /workspace/6.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/7.rstmgr_alert_test.805795035 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 71321271 ps |
| CPU time | 0.83 seconds |
| Started | Jan 24 01:04:46 PM PST 24 |
| Finished | Jan 24 01:05:28 PM PST 24 |
| Peak memory | 199552 kb |
| Host | smart-5e21ade1-4ebf-406d-9e86-e3a003beb735 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805795035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.805795035 |
| Directory | /workspace/7.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.344365178 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 1222865614 ps |
| CPU time | 5.55 seconds |
| Started | Jan 24 01:04:44 PM PST 24 |
| Finished | Jan 24 01:05:29 PM PST 24 |
| Peak memory | 217944 kb |
| Host | smart-188080d1-6892-4231-81e3-6bbb89976670 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=344365178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.344365178 |
| Directory | /workspace/7.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.113931798 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 244248227 ps |
| CPU time | 1.14 seconds |
| Started | Jan 24 01:04:46 PM PST 24 |
| Finished | Jan 24 01:05:28 PM PST 24 |
| Peak memory | 216816 kb |
| Host | smart-88e5feb2-b9b2-45a7-8eef-fffddd77e35a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=113931798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.113931798 |
| Directory | /workspace/7.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/7.rstmgr_por_stretcher.3635413607 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 190321898 ps |
| CPU time | 0.85 seconds |
| Started | Jan 24 01:05:02 PM PST 24 |
| Finished | Jan 24 01:05:48 PM PST 24 |
| Peak memory | 199376 kb |
| Host | smart-b878641e-6e41-49ab-b0df-12fb8e60af71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3635413607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.3635413607 |
| Directory | /workspace/7.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/7.rstmgr_reset.3313297335 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 1818005081 ps |
| CPU time | 7.26 seconds |
| Started | Jan 24 01:04:46 PM PST 24 |
| Finished | Jan 24 01:05:35 PM PST 24 |
| Peak memory | 199788 kb |
| Host | smart-be776252-0fa5-4690-994d-901271db272f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3313297335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3313297335 |
| Directory | /workspace/7.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.571017155 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 146579004 ps |
| CPU time | 1.13 seconds |
| Started | Jan 24 01:04:46 PM PST 24 |
| Finished | Jan 24 01:05:29 PM PST 24 |
| Peak memory | 199612 kb |
| Host | smart-614662bb-97bd-4d1e-9b07-55e23fe0211e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=571017155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.571017155 |
| Directory | /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/7.rstmgr_smoke.2766050966 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 121374464 ps |
| CPU time | 1.22 seconds |
| Started | Jan 24 01:04:45 PM PST 24 |
| Finished | Jan 24 01:05:28 PM PST 24 |
| Peak memory | 199764 kb |
| Host | smart-282b218f-0107-449d-9f6c-9994e3d7942f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2766050966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2766050966 |
| Directory | /workspace/7.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/7.rstmgr_stress_all.730499973 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1272131154 ps |
| CPU time | 6.65 seconds |
| Started | Jan 24 01:04:45 PM PST 24 |
| Finished | Jan 24 01:05:32 PM PST 24 |
| Peak memory | 199764 kb |
| Host | smart-f7c5559f-b06c-4e48-a074-54bb44763529 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730499973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.730499973 |
| Directory | /workspace/7.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/7.rstmgr_sw_rst.3358389731 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 127410500 ps |
| CPU time | 1.4 seconds |
| Started | Jan 24 01:04:43 PM PST 24 |
| Finished | Jan 24 01:05:25 PM PST 24 |
| Peak memory | 199440 kb |
| Host | smart-2d02d2ec-c1b8-4c7a-86d6-3b6fa3d923ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3358389731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3358389731 |
| Directory | /workspace/7.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3073975425 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 76525688 ps |
| CPU time | 0.81 seconds |
| Started | Jan 24 01:04:46 PM PST 24 |
| Finished | Jan 24 01:05:28 PM PST 24 |
| Peak memory | 199460 kb |
| Host | smart-f3b4c9e1-ab7a-4ef2-9c7e-844a48607d9a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3073975425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3073975425 |
| Directory | /workspace/7.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/8.rstmgr_alert_test.136919441 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 85325018 ps |
| CPU time | 0.78 seconds |
| Started | Jan 24 01:05:03 PM PST 24 |
| Finished | Jan 24 01:05:48 PM PST 24 |
| Peak memory | 199368 kb |
| Host | smart-9492b3a2-4c85-49ac-92a6-180854845f2c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136919441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.136919441 |
| Directory | /workspace/8.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.3697485806 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1888172896 ps |
| CPU time | 7.3 seconds |
| Started | Jan 24 01:05:05 PM PST 24 |
| Finished | Jan 24 01:05:58 PM PST 24 |
| Peak memory | 220624 kb |
| Host | smart-11205297-8673-43b6-87a2-5ee9f779c0ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3697485806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.3697485806 |
| Directory | /workspace/8.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1381690419 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 243985834 ps |
| CPU time | 1.09 seconds |
| Started | Jan 24 01:04:54 PM PST 24 |
| Finished | Jan 24 01:05:41 PM PST 24 |
| Peak memory | 216888 kb |
| Host | smart-d1754a85-8576-4c50-9058-b222c9f858c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1381690419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1381690419 |
| Directory | /workspace/8.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/8.rstmgr_por_stretcher.3013366030 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 219455300 ps |
| CPU time | 0.86 seconds |
| Started | Jan 24 01:05:03 PM PST 24 |
| Finished | Jan 24 01:05:48 PM PST 24 |
| Peak memory | 199232 kb |
| Host | smart-36f623f0-a7ae-4ea8-a874-beb7f30938da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3013366030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3013366030 |
| Directory | /workspace/8.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/8.rstmgr_reset.204761660 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 1316582728 ps |
| CPU time | 5.05 seconds |
| Started | Jan 24 01:05:05 PM PST 24 |
| Finished | Jan 24 01:05:55 PM PST 24 |
| Peak memory | 199832 kb |
| Host | smart-5390cabd-d553-4eac-b771-a0671fa1dd35 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=204761660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.204761660 |
| Directory | /workspace/8.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.3493488069 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 103746687 ps |
| CPU time | 1.02 seconds |
| Started | Jan 24 01:05:06 PM PST 24 |
| Finished | Jan 24 01:05:52 PM PST 24 |
| Peak memory | 199488 kb |
| Host | smart-52da9463-9546-44c8-961d-3c8b69055afe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3493488069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.3493488069 |
| Directory | /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/8.rstmgr_smoke.702535267 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 198692327 ps |
| CPU time | 1.31 seconds |
| Started | Jan 24 01:05:06 PM PST 24 |
| Finished | Jan 24 01:05:52 PM PST 24 |
| Peak memory | 199704 kb |
| Host | smart-2c6373f6-1c37-4ab3-8373-da190764da5d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=702535267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.702535267 |
| Directory | /workspace/8.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/8.rstmgr_stress_all.1837666198 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 2124083030 ps |
| CPU time | 7.4 seconds |
| Started | Jan 24 01:05:05 PM PST 24 |
| Finished | Jan 24 01:05:58 PM PST 24 |
| Peak memory | 199780 kb |
| Host | smart-64d24c9e-065f-4fcd-9178-1a2d87f20b5f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837666198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.1837666198 |
| Directory | /workspace/8.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/8.rstmgr_sw_rst.3570949190 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 123707452 ps |
| CPU time | 1.57 seconds |
| Started | Jan 24 01:04:54 PM PST 24 |
| Finished | Jan 24 01:05:40 PM PST 24 |
| Peak memory | 199588 kb |
| Host | smart-6d7f8838-2d9d-4112-a058-389bb5dfaf70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3570949190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3570949190 |
| Directory | /workspace/8.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.76520667 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 150481098 ps |
| CPU time | 1.18 seconds |
| Started | Jan 24 01:05:03 PM PST 24 |
| Finished | Jan 24 01:05:49 PM PST 24 |
| Peak memory | 199428 kb |
| Host | smart-fd80c46a-9c3c-4922-99f5-809946c1ae09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=76520667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.76520667 |
| Directory | /workspace/8.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/9.rstmgr_alert_test.3195879310 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 83536351 ps |
| CPU time | 0.87 seconds |
| Started | Jan 24 01:05:07 PM PST 24 |
| Finished | Jan 24 01:05:55 PM PST 24 |
| Peak memory | 199464 kb |
| Host | smart-4a04d05f-198e-4a38-b3e5-95e573cb7116 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195879310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3195879310 |
| Directory | /workspace/9.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.3927841278 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1226662635 ps |
| CPU time | 5.52 seconds |
| Started | Jan 24 01:05:07 PM PST 24 |
| Finished | Jan 24 01:05:58 PM PST 24 |
| Peak memory | 216952 kb |
| Host | smart-8abadc00-46a4-4db9-aea6-b075ba75c185 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3927841278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.3927841278 |
| Directory | /workspace/9.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2701268232 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 243816564 ps |
| CPU time | 1.04 seconds |
| Started | Jan 24 01:05:07 PM PST 24 |
| Finished | Jan 24 01:05:54 PM PST 24 |
| Peak memory | 216740 kb |
| Host | smart-6e0fa025-e49c-4594-8e8a-9761f590f101 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2701268232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2701268232 |
| Directory | /workspace/9.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/9.rstmgr_por_stretcher.3849695894 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 111195856 ps |
| CPU time | 0.79 seconds |
| Started | Jan 24 01:05:07 PM PST 24 |
| Finished | Jan 24 01:05:54 PM PST 24 |
| Peak memory | 199328 kb |
| Host | smart-7cb677d6-8c42-4984-b8d6-ed8524d6ad27 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3849695894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3849695894 |
| Directory | /workspace/9.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/9.rstmgr_reset.867816857 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 977415085 ps |
| CPU time | 4.73 seconds |
| Started | Jan 24 01:05:09 PM PST 24 |
| Finished | Jan 24 01:06:01 PM PST 24 |
| Peak memory | 199760 kb |
| Host | smart-77f822ad-4492-417d-9edc-b2a33998502c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=867816857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.867816857 |
| Directory | /workspace/9.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.190256593 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 178070373 ps |
| CPU time | 1.29 seconds |
| Started | Jan 24 01:05:01 PM PST 24 |
| Finished | Jan 24 01:05:48 PM PST 24 |
| Peak memory | 199564 kb |
| Host | smart-476fec58-6a6f-4a11-9d6a-eea5be934e3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=190256593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.190256593 |
| Directory | /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/9.rstmgr_smoke.4258847321 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 202814207 ps |
| CPU time | 1.35 seconds |
| Started | Jan 24 01:05:03 PM PST 24 |
| Finished | Jan 24 01:05:49 PM PST 24 |
| Peak memory | 199612 kb |
| Host | smart-01a41bff-ff49-4738-88bd-91e26d4337cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4258847321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.4258847321 |
| Directory | /workspace/9.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/9.rstmgr_stress_all.4168694272 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 8077090568 ps |
| CPU time | 30.34 seconds |
| Started | Jan 24 01:05:07 PM PST 24 |
| Finished | Jan 24 01:06:23 PM PST 24 |
| Peak memory | 199828 kb |
| Host | smart-317eb50d-e22e-42bd-b256-4133dcf2a936 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168694272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.4168694272 |
| Directory | /workspace/9.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/9.rstmgr_sw_rst.632224606 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 327866931 ps |
| CPU time | 2.09 seconds |
| Started | Jan 24 01:05:07 PM PST 24 |
| Finished | Jan 24 01:05:55 PM PST 24 |
| Peak memory | 199640 kb |
| Host | smart-582a64e1-3653-4174-b844-55cb1d65deed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=632224606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.632224606 |
| Directory | /workspace/9.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.510586007 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 164787251 ps |
| CPU time | 1.16 seconds |
| Started | Jan 24 01:05:10 PM PST 24 |
| Finished | Jan 24 01:05:59 PM PST 24 |
| Peak memory | 199756 kb |
| Host | smart-c6841a9a-f299-4808-8eca-55d35d9c10ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=510586007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.510586007 |
| Directory | /workspace/9.rstmgr_sw_rst_reset_race/latest |
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