Module Definition
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Module : rstmgr_cnsty_chk
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.99 96.49 84.62 100.00 92.31 96.55 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_cnsty_chk_0/rtl/rstmgr_cnsty_chk.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 96.17 96.49 91.67 100.00 92.31 96.55 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.17 96.49 91.67 100.00 92.31 96.55 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.87 98.41 86.21 100.00 92.31 98.31 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_child_handshake 90.00 100.00 60.00 100.00 100.00
u_child_sync 100.00 100.00 100.00
u_parent_sync 100.00 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00

Line Coverage for Module : rstmgr_cnsty_chk
Line No.TotalCoveredPercent
TOTAL575596.49
ALWAYS4133100.00
ALWAYS5033100.00
ALWAYS11333100.00
CONT_ASSIGN12400
ALWAYS12766100.00
CONT_ASSIGN14011100.00
ALWAYS151413995.12
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_cnsty_chk_0/rtl/rstmgr_cnsty_chk.sv' or '../src/lowrisc_ip_rstmgr_cnsty_chk_0/rtl/rstmgr_cnsty_chk.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
44 1 1
50 1 1
51 1 1
53 1 1
113 3 3
124 unreachable
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE
140 1 1
151 1 1
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
158 1 1
162 1 1
163 1 1
MISSING_ELSE
172 1 1
173 1 1
174 1 1
175 1 1
176 1 1
177 1 1
MISSING_ELSE
183 1 1
185 1 1
186 unreachable
187 1 1
188 1 1
189 1 1
MISSING_ELSE
195 1 1
197 1 1
198 unreachable
199 1 1
200 1 1
201 1 1
MISSING_ELSE
209 1 1
213 1 1
214 1 1
215 1 1
216 1 1
217 1 1
MISSING_ELSE
231 1 1
232 1 1
235 0 1
236 0 1
237 1 1
238 unreachable
239 1 1
240 1 1
241 1 1
MISSING_ELSE
246 1 1
250 1 1


Cond Coverage for Module : rstmgr_cnsty_chk
TotalCoveredPercent
Conditions262284.62
Logical262284.62
Non-Logical00
Event00

 LINE       131
 EXPRESSION (cnt_inc && ((!timeout)))
             ---1---    ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10UnreachableT1,T2,T3
11CoveredT1,T2,T3

 LINE       140
 EXPRESSION (sync_parent_rst || sw_rst_req_i)
             -------1-------    ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       162
 EXPRESSION (((!sync_child_rst)) && ((!sync_parent_rst)))
             ---------1---------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       172
 EXPRESSION (sync_child_rst && src_valid)
             -------1------    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       174
 EXPRESSION (sync_child_rst && ((!sync_parent_rst)))
             -------1------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       176
 EXPRESSION (sync_parent_rst && ((!sync_child_rst)))
             -------1-------    ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       185
 EXPRESSION (timeout && ((!sync_parent_rst)))
             ---1---    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10UnreachableT1,T2,T3
11UnreachableT1,T2,T3

 LINE       197
 EXPRESSION (timeout && ((!sync_child_rst)))
             ---1---    ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10UnreachableT1,T2,T3
11UnreachableT1,T2,T3

 LINE       213
 EXPRESSION (((!sync_child_rst)) && src_valid)
             ---------1---------    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       232
 EXPRESSION (sync_child_rst && src_valid)
             -------1------    ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       237
 EXPRESSION (sync_child_rst && timeout)
             -------1------    ---2---
-1--2-StatusTests
01UnreachableT1,T2,T3
10CoveredT1,T2,T3
11UnreachableT1,T2,T3

Toggle Coverage for Module : rstmgr_cnsty_chk
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_chk_rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
parent_rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sw_rst_req_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sw_rst_req_clr_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
fsm_err_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT


FSM Coverage for Module : rstmgr_cnsty_chk
Summary for FSM :: state_q
TotalCoveredPercent
States 8 8 100.00 (Not included in score)
Transitions 13 12 92.31
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
Error 186 Covered T1,T2,T3
FsmError 249 Covered T1,T2,T3
Idle 163 Covered T1,T2,T3
Reset 159 Covered T1,T2,T3
WaitForChild 177 Covered T1,T2,T3
WaitForChildRelease 217 Covered T1,T2,T3
WaitForParent 175 Covered T1,T2,T3
WaitForSrcRelease 173 Covered T1,T2,T3


transitionsLine No.CoveredTests
Idle->WaitForChild 177 Covered T1,T2,T3
Idle->WaitForParent 175 Covered T1,T2,T3
Idle->WaitForSrcRelease 173 Covered T1,T2,T3
Reset->Idle 163 Covered T1,T2,T3
WaitForChild->Error 198 Covered T1,T2,T3
WaitForChild->WaitForSrcRelease 200 Covered T1,T2,T3
WaitForChildRelease->Error 238 Covered T1,T2,T3
WaitForChildRelease->Idle 240 Covered T1,T2,T3
WaitForChildRelease->WaitForSrcRelease 235 Not Covered
WaitForParent->Error 186 Covered T1,T2,T3
WaitForParent->WaitForSrcRelease 188 Covered T1,T2,T3
WaitForSrcRelease->Error 214 Covered T1,T2,T3
WaitForSrcRelease->WaitForChildRelease 217 Covered T1,T2,T3



Branch Coverage for Module : rstmgr_cnsty_chk
Line No.TotalCoveredPercent
Branches 29 28 96.55
IF 41 2 2 100.00
IF 50 2 2 100.00
IF 113 2 2 100.00
IF 127 4 4 100.00
CASE 158 19 18 94.74

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_cnsty_chk_0/rtl/rstmgr_cnsty_chk.sv' or '../src/lowrisc_ip_rstmgr_cnsty_chk_0/rtl/rstmgr_cnsty_chk.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 41 if ((!parent_rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 50 if ((!child_rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 113 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 127 if ((!rst_ni)) -2-: 129 if (cnt_clr) -3-: 131 if ((cnt_inc && (!timeout)))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 158 case (state_q) -2-: 162 if (((!sync_child_rst) && (!sync_parent_rst))) -3-: 172 if ((sync_child_rst && src_valid)) -4-: 174 if ((sync_child_rst && (!sync_parent_rst))) -5-: 176 if ((sync_parent_rst && (!sync_child_rst))) -6-: 185 if ((timeout && (!sync_parent_rst))) -7-: 187 if (sync_parent_rst) -8-: 197 if ((timeout && (!sync_child_rst))) -9-: 199 if (sync_child_rst) -10-: 213 if (((!sync_child_rst) && src_valid)) -11-: 215 if ((!src_valid)) -12-: 232 if ((sync_child_rst && src_valid)) -13-: 237 if ((sync_child_rst && timeout)) -14-: 239 if ((!sync_child_rst))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14-StatusTests
Reset 1 - - - - - - - - - - - - Covered T1,T2,T3
Reset 0 - - - - - - - - - - - - Covered T1,T2,T3
Idle - 1 - - - - - - - - - - - Covered T1,T2,T3
Idle - 0 1 - - - - - - - - - - Covered T1,T2,T3
Idle - 0 0 1 - - - - - - - - - Covered T1,T2,T3
Idle - 0 0 0 - - - - - - - - - Covered T1,T2,T3
WaitForParent - - - - 1 - - - - - - - - Unreachable T1,T2,T3
WaitForParent - - - - 0 1 - - - - - - - Covered T1,T2,T3
WaitForParent - - - - 0 0 - - - - - - - Covered T1,T2,T3
WaitForChild - - - - - - 1 - - - - - - Unreachable T1,T2,T3
WaitForChild - - - - - - 0 1 - - - - - Covered T1,T2,T3
WaitForChild - - - - - - 0 0 - - - - - Covered T1,T2,T3
WaitForSrcRelease - - - - - - - - 1 - - - - Covered T1,T2,T3
WaitForSrcRelease - - - - - - - - 0 1 - - - Covered T1,T2,T3
WaitForSrcRelease - - - - - - - - 0 0 - - - Covered T1,T2,T3
WaitForChildRelease - - - - - - - - - - 1 - - Not Covered
WaitForChildRelease - - - - - - - - - - 0 1 - Unreachable T1,T2,T3
WaitForChildRelease - - - - - - - - - - 0 0 1 Covered T1,T2,T3
WaitForChildRelease - - - - - - - - - - 0 0 0 Covered T1,T2,T3
Error - - - - - - - - - - - - - Covered T1,T2,T3
FsmError - - - - - - - - - - - - - Covered T1,T2,T3
default - - - - - - - - - - - - - Covered T1,T2,T3


Assert Coverage for Module : rstmgr_cnsty_chk
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
u_state_regs_A 9635640 9188982 0 0


u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9635640 9188982 0 0
T1 929061 913659 0 0
T2 927147 865539 0 0
T3 927150 896346 0 0
T4 101142 949813 0 0
T5 102373 954430 0 0
T6 872571 826365 0 0
T7 942934 896728 0 0
T8 981228 935022 0 0
T9 109323 103933 0 0
T10 927150 911748 0 0

Line Coverage for Instance : tb.dut
Line No.TotalCoveredPercent
TOTAL575596.49
ALWAYS4133100.00
ALWAYS5033100.00
ALWAYS11333100.00
CONT_ASSIGN12400
ALWAYS12766100.00
CONT_ASSIGN14011100.00
ALWAYS151413995.12
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_cnsty_chk_0/rtl/rstmgr_cnsty_chk.sv' or '../src/lowrisc_ip_rstmgr_cnsty_chk_0/rtl/rstmgr_cnsty_chk.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
44 1 1
50 1 1
51 1 1
53 1 1
113 3 3
124 unreachable
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE
140 1 1
151 1 1
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
158 1 1
162 1 1
163 1 1
MISSING_ELSE
172 1 1
173 1 1
174 1 1
175 1 1
176 1 1
177 1 1
MISSING_ELSE
183 1 1
185 1 1
186 unreachable
187 1 1
188 1 1
189 1 1
MISSING_ELSE
195 1 1
197 1 1
198 unreachable
199 1 1
200 1 1
201 1 1
MISSING_ELSE
209 1 1
213 1 1
214 1 1
215 1 1
216 1 1
217 1 1
MISSING_ELSE
231 1 1
232 1 1
235 0 1
236 0 1
237 1 1
238 unreachable
239 1 1
240 1 1
241 1 1
MISSING_ELSE
246 1 1
250 1 1


Cond Coverage for Instance : tb.dut
TotalCoveredPercent
Conditions242291.67
Logical242291.67
Non-Logical00
Event00

 LINE       131
 EXPRESSION (cnt_inc && ((!timeout)))
             ---1---    ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10UnreachableT1,T2,T3
11CoveredT1,T2,T3

 LINE       140
 EXPRESSION (sync_parent_rst || sw_rst_req_i)
             -------1-------    ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       162
 EXPRESSION (((!sync_child_rst)) && ((!sync_parent_rst)))
             ---------1---------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       172
 EXPRESSION (sync_child_rst && src_valid)
             -------1------    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       174
 EXPRESSION (sync_child_rst && ((!sync_parent_rst)))
             -------1------    ----------2---------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       176
 EXPRESSION (sync_parent_rst && ((!sync_child_rst)))
             -------1-------    ---------2---------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       185
 EXPRESSION (timeout && ((!sync_parent_rst)))
             ---1---    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10UnreachableT1,T2,T3
11UnreachableT1,T2,T3

 LINE       197
 EXPRESSION (timeout && ((!sync_child_rst)))
             ---1---    ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10UnreachableT1,T2,T3
11UnreachableT1,T2,T3

 LINE       213
 EXPRESSION (((!sync_child_rst)) && src_valid)
             ---------1---------    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       232
 EXPRESSION (sync_child_rst && src_valid)
             -------1------    ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       237
 EXPRESSION (sync_child_rst && timeout)
             -------1------    ---2---
-1--2-StatusTests
01UnreachableT1,T2,T3
10CoveredT1,T2,T3
11UnreachableT1,T2,T3

Toggle Coverage for Instance : tb.dut
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_chk_rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
parent_rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sw_rst_req_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sw_rst_req_clr_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
fsm_err_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT


FSM Coverage for Instance : tb.dut
Summary for FSM :: state_q
TotalCoveredPercent
States 8 8 100.00 (Not included in score)
Transitions 13 12 92.31
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
Error 186 Covered T1,T2,T3
FsmError 249 Covered T1,T2,T3
Idle 163 Covered T1,T2,T3
Reset 159 Covered T1,T2,T3
WaitForChild 177 Covered T1,T2,T3
WaitForChildRelease 217 Covered T1,T2,T3
WaitForParent 175 Covered T1,T2,T3
WaitForSrcRelease 173 Covered T1,T2,T3


transitionsLine No.CoveredTests
Idle->WaitForChild 177 Covered T1,T2,T3
Idle->WaitForParent 175 Covered T1,T2,T3
Idle->WaitForSrcRelease 173 Covered T1,T2,T3
Reset->Idle 163 Covered T1,T2,T3
WaitForChild->Error 198 Covered T1,T2,T3
WaitForChild->WaitForSrcRelease 200 Covered T1,T2,T3
WaitForChildRelease->Error 238 Covered T1,T2,T3
WaitForChildRelease->Idle 240 Covered T1,T2,T3
WaitForChildRelease->WaitForSrcRelease 235 Not Covered
WaitForParent->Error 186 Covered T1,T2,T3
WaitForParent->WaitForSrcRelease 188 Covered T1,T2,T3
WaitForSrcRelease->Error 214 Covered T1,T2,T3
WaitForSrcRelease->WaitForChildRelease 217 Covered T1,T2,T3



Branch Coverage for Instance : tb.dut
Line No.TotalCoveredPercent
Branches 29 28 96.55
IF 41 2 2 100.00
IF 50 2 2 100.00
IF 113 2 2 100.00
IF 127 4 4 100.00
CASE 158 19 18 94.74

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_cnsty_chk_0/rtl/rstmgr_cnsty_chk.sv' or '../src/lowrisc_ip_rstmgr_cnsty_chk_0/rtl/rstmgr_cnsty_chk.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 41 if ((!parent_rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 50 if ((!child_rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 113 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 127 if ((!rst_ni)) -2-: 129 if (cnt_clr) -3-: 131 if ((cnt_inc && (!timeout)))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 158 case (state_q) -2-: 162 if (((!sync_child_rst) && (!sync_parent_rst))) -3-: 172 if ((sync_child_rst && src_valid)) -4-: 174 if ((sync_child_rst && (!sync_parent_rst))) -5-: 176 if ((sync_parent_rst && (!sync_child_rst))) -6-: 185 if ((timeout && (!sync_parent_rst))) -7-: 187 if (sync_parent_rst) -8-: 197 if ((timeout && (!sync_child_rst))) -9-: 199 if (sync_child_rst) -10-: 213 if (((!sync_child_rst) && src_valid)) -11-: 215 if ((!src_valid)) -12-: 232 if ((sync_child_rst && src_valid)) -13-: 237 if ((sync_child_rst && timeout)) -14-: 239 if ((!sync_child_rst))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14-StatusTests
Reset 1 - - - - - - - - - - - - Covered T1,T2,T3
Reset 0 - - - - - - - - - - - - Covered T1,T2,T3
Idle - 1 - - - - - - - - - - - Covered T1,T2,T3
Idle - 0 1 - - - - - - - - - - Covered T1,T2,T3
Idle - 0 0 1 - - - - - - - - - Covered T1,T2,T3
Idle - 0 0 0 - - - - - - - - - Covered T1,T2,T3
WaitForParent - - - - 1 - - - - - - - - Unreachable T1,T2,T3
WaitForParent - - - - 0 1 - - - - - - - Covered T1,T2,T3
WaitForParent - - - - 0 0 - - - - - - - Covered T1,T2,T3
WaitForChild - - - - - - 1 - - - - - - Unreachable T1,T2,T3
WaitForChild - - - - - - 0 1 - - - - - Covered T1,T2,T3
WaitForChild - - - - - - 0 0 - - - - - Covered T1,T2,T3
WaitForSrcRelease - - - - - - - - 1 - - - - Covered T1,T2,T3
WaitForSrcRelease - - - - - - - - 0 1 - - - Covered T1,T2,T3
WaitForSrcRelease - - - - - - - - 0 0 - - - Covered T1,T2,T3
WaitForChildRelease - - - - - - - - - - 1 - - Not Covered
WaitForChildRelease - - - - - - - - - - 0 1 - Unreachable T1,T2,T3
WaitForChildRelease - - - - - - - - - - 0 0 1 Covered T1,T2,T3
WaitForChildRelease - - - - - - - - - - 0 0 0 Covered T1,T2,T3
Error - - - - - - - - - - - - - Covered T1,T2,T3
FsmError - - - - - - - - - - - - - Covered T1,T2,T3
default - - - - - - - - - - - - - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
u_state_regs_A 9635640 9188982 0 0


u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9635640 9188982 0 0
T1 929061 913659 0 0
T2 927147 865539 0 0
T3 927150 896346 0 0
T4 101142 949813 0 0
T5 102373 954430 0 0
T6 872571 826365 0 0
T7 942934 896728 0 0
T8 981228 935022 0 0
T9 109323 103933 0 0
T10 927150 911748 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%