Unified Coverage Report :: Module :: rstmgr_cnsty_chk

Module : rstmgr_cnsty_chk

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.99	96.49	84.62	100.00	92.31	96.55	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_cnsty_chk_0/rtl/rstmgr_cnsty_chk.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	96.17	96.49	91.67	100.00	92.31	96.55	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.17	96.49	91.67	100.00	92.31	96.55	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.87	98.41	86.21	100.00	92.31	98.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_child_handshake	90.00	100.00	60.00			100.00	100.00
u_child_sync	100.00	100.00				100.00
u_parent_sync	100.00	100.00				100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : rstmgr_cnsty_chk

	Line No.	Total	Covered	Percent
TOTAL		57	55	96.49
ALWAYS	41	3	3	100.00
ALWAYS	50	3	3	100.00
ALWAYS	113	3	3	100.00
CONT_ASSIGN	124	0	0
ALWAYS	127	6	6	100.00
CONT_ASSIGN	140	1	1	100.00
ALWAYS	151	41	39	95.12

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_cnsty_chk_0/rtl/rstmgr_cnsty_chk.sv' or '../src/lowrisc_ip_rstmgr_cnsty_chk_0/rtl/rstmgr_cnsty_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
41	1	1
42	1	1
44	1	1
50	1	1
51	1	1
53	1	1
113	3	3
124		unreachable
127	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
			MISSING_ELSE
140	1	1
151	1	1
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
158	1	1
162	1	1
163	1	1
			MISSING_ELSE
172	1	1
173	1	1
174	1	1
175	1	1
176	1	1
177	1	1
			MISSING_ELSE
183	1	1
185	1	1
186		unreachable
187	1	1
188	1	1
189	1	1
			MISSING_ELSE
195	1	1
197	1	1
198		unreachable
199	1	1
200	1	1
201	1	1
			MISSING_ELSE
209	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
231	1	1
232	1	1
235	0	1
236	0	1
237	1	1
238		unreachable
239	1	1
240	1	1
241	1	1
			MISSING_ELSE
246	1	1
250	1	1

---

Cond Coverage for Module : rstmgr_cnsty_chk

	Total	Covered	Percent
Conditions	26	22	84.62
Logical	26	22	84.62
Non-Logical	0	0
Event	0	0

 LINE       131
 EXPRESSION (cnt_inc && ((!timeout)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (sync_parent_rst || sw_rst_req_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       162
 EXPRESSION (((!sync_child_rst)) && ((!sync_parent_rst)))
             ---------1---------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       172
 EXPRESSION (sync_child_rst && src_valid)
             -------1------    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       174
 EXPRESSION (sync_child_rst && ((!sync_parent_rst)))
             -------1------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       176
 EXPRESSION (sync_parent_rst && ((!sync_child_rst)))
             -------1-------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (timeout && ((!sync_parent_rst)))
             ---1---    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T1,T2,T3
1	1	Unreachable	T1,T2,T3

 LINE       197
 EXPRESSION (timeout && ((!sync_child_rst)))
             ---1---    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T1,T2,T3
1	1	Unreachable	T1,T2,T3

 LINE       213
 EXPRESSION (((!sync_child_rst)) && src_valid)
             ---------1---------    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       232
 EXPRESSION (sync_child_rst && src_valid)
             -------1------    ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       237
 EXPRESSION (sync_child_rst && timeout)
             -------1------    ---2---

-1-	-2-	Status	Tests
0	1	Unreachable	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Unreachable	T1,T2,T3

---

Toggle Coverage for Module : rstmgr_cnsty_chk

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00

Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_chk_rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
parent_rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
sw_rst_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
sw_rst_req_clr_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
fsm_err_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

---

FSM Coverage for Module : rstmgr_cnsty_chk

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
Error	186	Covered	T1,T2,T3
FsmError	249	Covered	T1,T2,T3
Idle	163	Covered	T1,T2,T3
Reset	159	Covered	T1,T2,T3
WaitForChild	177	Covered	T1,T2,T3
WaitForChildRelease	217	Covered	T1,T2,T3
WaitForParent	175	Covered	T1,T2,T3
WaitForSrcRelease	173	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
Idle->WaitForChild	177	Covered	T1,T2,T3
Idle->WaitForParent	175	Covered	T1,T2,T3
Idle->WaitForSrcRelease	173	Covered	T1,T2,T3
Reset->Idle	163	Covered	T1,T2,T3
WaitForChild->Error	198	Covered	T1,T2,T3
WaitForChild->WaitForSrcRelease	200	Covered	T1,T2,T3
WaitForChildRelease->Error	238	Covered	T1,T2,T3
WaitForChildRelease->Idle	240	Covered	T1,T2,T3
WaitForChildRelease->WaitForSrcRelease	235	Not Covered
WaitForParent->Error	186	Covered	T1,T2,T3
WaitForParent->WaitForSrcRelease	188	Covered	T1,T2,T3
WaitForSrcRelease->Error	214	Covered	T1,T2,T3
WaitForSrcRelease->WaitForChildRelease	217	Covered	T1,T2,T3

---

Branch Coverage for Module : rstmgr_cnsty_chk

	Line No.	Total	Covered	Percent
Branches		29	28	96.55
IF	41	2	2	100.00
IF	50	2	2	100.00
IF	113	2	2	100.00
IF	127	4	4	100.00
CASE	158	19	18	94.74

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_cnsty_chk_0/rtl/rstmgr_cnsty_chk.sv' or '../src/lowrisc_ip_rstmgr_cnsty_chk_0/rtl/rstmgr_cnsty_chk.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	41	if ((!parent_rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	50	if ((!child_rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	113	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	127	if ((!rst_ni))
-2-:	129	if (cnt_clr)
-3-:	131	if ((cnt_inc && (!timeout)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	158	case (state_q)
-2-:	162	if (((!sync_child_rst) && (!sync_parent_rst)))
-3-:	172	if ((sync_child_rst && src_valid))
-4-:	174	if ((sync_child_rst && (!sync_parent_rst)))
-5-:	176	if ((sync_parent_rst && (!sync_child_rst)))
-6-:	185	if ((timeout && (!sync_parent_rst)))
-7-:	187	if (sync_parent_rst)
-8-:	197	if ((timeout && (!sync_child_rst)))
-9-:	199	if (sync_child_rst)
-10-:	213	if (((!sync_child_rst) && src_valid))
-11-:	215	if ((!src_valid))
-12-:	232	if ((sync_child_rst && src_valid))
-13-:	237	if ((sync_child_rst && timeout))
-14-:	239	if ((!sync_child_rst))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
Reset	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Reset	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	-	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	-	0	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	-	0	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
WaitForParent	-	-	-	-	1	-	-	-	-	-	-	-	-	Unreachable	T1,T2,T3
WaitForParent	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
WaitForParent	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
WaitForChild	-	-	-	-	-	-	1	-	-	-	-	-	-	Unreachable	T1,T2,T3
WaitForChild	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
WaitForChild	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
WaitForSrcRelease	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T3
WaitForSrcRelease	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
WaitForSrcRelease	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
WaitForChildRelease	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
WaitForChildRelease	-	-	-	-	-	-	-	-	-	-	0	1	-	Unreachable	T1,T2,T3
WaitForChildRelease	-	-	-	-	-	-	-	-	-	-	0	0	1	Covered	T1,T2,T3
WaitForChildRelease	-	-	-	-	-	-	-	-	-	-	0	0	0	Covered	T1,T2,T3
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
FsmError	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cnsty_chk

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
u_state_regs_A	5095426	4841293	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5095426	4841293	0	0
T1	891726	837819	0	0
T2	110703	104542	0	0
T3	112031	108181	0	0
T4	952616	906410	0	0
T5	102373	969829	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		57	55	96.49
ALWAYS	41	3	3	100.00
ALWAYS	50	3	3	100.00
ALWAYS	113	3	3	100.00
CONT_ASSIGN	124	0	0
ALWAYS	127	6	6	100.00
CONT_ASSIGN	140	1	1	100.00
ALWAYS	151	41	39	95.12

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_cnsty_chk_0/rtl/rstmgr_cnsty_chk.sv' or '../src/lowrisc_ip_rstmgr_cnsty_chk_0/rtl/rstmgr_cnsty_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
41	1	1
42	1	1
44	1	1
50	1	1
51	1	1
53	1	1
113	3	3
124		unreachable
127	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
			MISSING_ELSE
140	1	1
151	1	1
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
158	1	1
162	1	1
163	1	1
			MISSING_ELSE
172	1	1
173	1	1
174	1	1
175	1	1
176	1	1
177	1	1
			MISSING_ELSE
183	1	1
185	1	1
186		unreachable
187	1	1
188	1	1
189	1	1
			MISSING_ELSE
195	1	1
197	1	1
198		unreachable
199	1	1
200	1	1
201	1	1
			MISSING_ELSE
209	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
231	1	1
232	1	1
235	0	1
236	0	1
237	1	1
238		unreachable
239	1	1
240	1	1
241	1	1
			MISSING_ELSE
246	1	1
250	1	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	24	22	91.67
Logical	24	22	91.67
Non-Logical	0	0
Event	0	0

 LINE       131
 EXPRESSION (cnt_inc && ((!timeout)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (sync_parent_rst || sw_rst_req_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       162
 EXPRESSION (((!sync_child_rst)) && ((!sync_parent_rst)))
             ---------1---------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       172
 EXPRESSION (sync_child_rst && src_valid)
             -------1------    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       174
 EXPRESSION (sync_child_rst && ((!sync_parent_rst)))
             -------1------    ----------2---------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       176
 EXPRESSION (sync_parent_rst && ((!sync_child_rst)))
             -------1-------    ---------2---------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (timeout && ((!sync_parent_rst)))
             ---1---    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T1,T2,T3
1	1	Unreachable	T1,T2,T3

 LINE       197
 EXPRESSION (timeout && ((!sync_child_rst)))
             ---1---    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T1,T2,T3
1	1	Unreachable	T1,T2,T3

 LINE       213
 EXPRESSION (((!sync_child_rst)) && src_valid)
             ---------1---------    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       232
 EXPRESSION (sync_child_rst && src_valid)
             -------1------    ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       237
 EXPRESSION (sync_child_rst && timeout)
             -------1------    ---2---

-1-	-2-	Status	Tests
0	1	Unreachable	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Unreachable	T1,T2,T3

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00

Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
child_chk_rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
parent_rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
sw_rst_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
sw_rst_req_clr_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
fsm_err_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

---

FSM Coverage for Instance : tb.dut

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
Error	186	Covered	T1,T2,T3
FsmError	249	Covered	T1,T2,T3
Idle	163	Covered	T1,T2,T3
Reset	159	Covered	T1,T2,T3
WaitForChild	177	Covered	T1,T2,T3
WaitForChildRelease	217	Covered	T1,T2,T3
WaitForParent	175	Covered	T1,T2,T3
WaitForSrcRelease	173	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
Idle->WaitForChild	177	Covered	T1,T2,T3
Idle->WaitForParent	175	Covered	T1,T2,T3
Idle->WaitForSrcRelease	173	Covered	T1,T2,T3
Reset->Idle	163	Covered	T1,T2,T3
WaitForChild->Error	198	Covered	T1,T2,T3
WaitForChild->WaitForSrcRelease	200	Covered	T1,T2,T3
WaitForChildRelease->Error	238	Covered	T1,T2,T3
WaitForChildRelease->Idle	240	Covered	T1,T2,T3
WaitForChildRelease->WaitForSrcRelease	235	Not Covered
WaitForParent->Error	186	Covered	T1,T2,T3
WaitForParent->WaitForSrcRelease	188	Covered	T1,T2,T3
WaitForSrcRelease->Error	214	Covered	T1,T2,T3
WaitForSrcRelease->WaitForChildRelease	217	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		29	28	96.55
IF	41	2	2	100.00
IF	50	2	2	100.00
IF	113	2	2	100.00
IF	127	4	4	100.00
CASE	158	19	18	94.74

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_cnsty_chk_0/rtl/rstmgr_cnsty_chk.sv' or '../src/lowrisc_ip_rstmgr_cnsty_chk_0/rtl/rstmgr_cnsty_chk.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	41	if ((!parent_rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	50	if ((!child_rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	113	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	127	if ((!rst_ni))
-2-:	129	if (cnt_clr)
-3-:	131	if ((cnt_inc && (!timeout)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	158	case (state_q)
-2-:	162	if (((!sync_child_rst) && (!sync_parent_rst)))
-3-:	172	if ((sync_child_rst && src_valid))
-4-:	174	if ((sync_child_rst && (!sync_parent_rst)))
-5-:	176	if ((sync_parent_rst && (!sync_child_rst)))
-6-:	185	if ((timeout && (!sync_parent_rst)))
-7-:	187	if (sync_parent_rst)
-8-:	197	if ((timeout && (!sync_child_rst)))
-9-:	199	if (sync_child_rst)
-10-:	213	if (((!sync_child_rst) && src_valid))
-11-:	215	if ((!src_valid))
-12-:	232	if ((sync_child_rst && src_valid))
-13-:	237	if ((sync_child_rst && timeout))
-14-:	239	if ((!sync_child_rst))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
Reset	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Reset	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	-	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	-	0	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	-	0	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
WaitForParent	-	-	-	-	1	-	-	-	-	-	-	-	-	Unreachable	T1,T2,T3
WaitForParent	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
WaitForParent	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
WaitForChild	-	-	-	-	-	-	1	-	-	-	-	-	-	Unreachable	T1,T2,T3
WaitForChild	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
WaitForChild	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
WaitForSrcRelease	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T3
WaitForSrcRelease	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
WaitForSrcRelease	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
WaitForChildRelease	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
WaitForChildRelease	-	-	-	-	-	-	-	-	-	-	0	1	-	Unreachable	T1,T2,T3
WaitForChildRelease	-	-	-	-	-	-	-	-	-	-	0	0	1	Covered	T1,T2,T3
WaitForChildRelease	-	-	-	-	-	-	-	-	-	-	0	0	0	Covered	T1,T2,T3
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
FsmError	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
u_state_regs_A	5095426	4841293	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5095426	4841293	0	0
T1	891726	837819	0	0
T2	110703	104542	0	0
T3	112031	108181	0	0
T4	952616	906410	0	0
T5	102373	969829	0	0